2 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
3 * Authors: Rusty Russell <rusty@rustcorp.com.au>
4 * Christoffer Dall <c.dall@virtualopensystems.com>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License, version 2, as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
20 #include <linux/kvm_host.h>
21 #include <linux/uaccess.h>
22 #include <asm/kvm_arm.h>
23 #include <asm/kvm_host.h>
24 #include <asm/kvm_emulate.h>
25 #include <asm/kvm_coproc.h>
26 #include <asm/kvm_mmu.h>
27 #include <asm/cacheflush.h>
28 #include <asm/cputype.h>
29 #include <trace/events/kvm.h>
31 #include "../vfp/vfpinstr.h"
37 /******************************************************************************
38 * Co-processor emulation
39 *****************************************************************************/
41 /* 3 bits per cache level, as per CLIDR, but non-existent caches always 0 */
42 static u32 cache_levels;
44 /* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */
48 * kvm_vcpu_arch.cp15 holds cp15 registers as an array of u32, but some
49 * of cp15 registers can be viewed either as couple of two u32 registers
50 * or one u64 register. Current u64 register encoding is that least
51 * significant u32 word is followed by most significant u32 word.
53 static inline void vcpu_cp15_reg64_set(struct kvm_vcpu *vcpu,
54 const struct coproc_reg *r,
57 vcpu_cp15(vcpu, r->reg) = val & 0xffffffff;
58 vcpu_cp15(vcpu, r->reg + 1) = val >> 32;
61 static inline u64 vcpu_cp15_reg64_get(struct kvm_vcpu *vcpu,
62 const struct coproc_reg *r)
66 val = vcpu_cp15(vcpu, r->reg + 1);
68 val = val | vcpu_cp15(vcpu, r->reg);
72 int kvm_handle_cp10_id(struct kvm_vcpu *vcpu, struct kvm_run *run)
74 kvm_inject_undefined(vcpu);
78 int kvm_handle_cp_0_13_access(struct kvm_vcpu *vcpu, struct kvm_run *run)
81 * We can get here, if the host has been built without VFPv3 support,
82 * but the guest attempted a floating point operation.
84 kvm_inject_undefined(vcpu);
88 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu, struct kvm_run *run)
90 kvm_inject_undefined(vcpu);
94 int kvm_handle_cp14_access(struct kvm_vcpu *vcpu, struct kvm_run *run)
96 kvm_inject_undefined(vcpu);
100 static void reset_mpidr(struct kvm_vcpu *vcpu, const struct coproc_reg *r)
103 * Compute guest MPIDR. We build a virtual cluster out of the
104 * vcpu_id, but we read the 'U' bit from the underlying
107 vcpu_cp15(vcpu, c0_MPIDR) = ((read_cpuid_mpidr() & MPIDR_SMP_BITMASK) |
108 ((vcpu->vcpu_id >> 2) << MPIDR_LEVEL_BITS) |
109 (vcpu->vcpu_id & 3));
112 /* TRM entries A7:4.3.31 A15:4.3.28 - RO WI */
113 static bool access_actlr(struct kvm_vcpu *vcpu,
114 const struct coproc_params *p,
115 const struct coproc_reg *r)
118 return ignore_write(vcpu, p);
120 *vcpu_reg(vcpu, p->Rt1) = vcpu_cp15(vcpu, c1_ACTLR);
124 /* TRM entries A7:4.3.56, A15:4.3.60 - R/O. */
125 static bool access_cbar(struct kvm_vcpu *vcpu,
126 const struct coproc_params *p,
127 const struct coproc_reg *r)
130 return write_to_read_only(vcpu, p);
131 return read_zero(vcpu, p);
134 /* TRM entries A7:4.3.49, A15:4.3.48 - R/O WI */
135 static bool access_l2ctlr(struct kvm_vcpu *vcpu,
136 const struct coproc_params *p,
137 const struct coproc_reg *r)
140 return ignore_write(vcpu, p);
142 *vcpu_reg(vcpu, p->Rt1) = vcpu_cp15(vcpu, c9_L2CTLR);
146 static void reset_l2ctlr(struct kvm_vcpu *vcpu, const struct coproc_reg *r)
150 asm volatile("mrc p15, 1, %0, c9, c0, 2\n" : "=r" (l2ctlr));
151 l2ctlr &= ~(3 << 24);
152 ncores = atomic_read(&vcpu->kvm->online_vcpus) - 1;
153 /* How many cores in the current cluster and the next ones */
154 ncores -= (vcpu->vcpu_id & ~3);
155 /* Cap it to the maximum number of cores in a single cluster */
156 ncores = min(ncores, 3U);
157 l2ctlr |= (ncores & 3) << 24;
159 vcpu_cp15(vcpu, c9_L2CTLR) = l2ctlr;
162 static void reset_actlr(struct kvm_vcpu *vcpu, const struct coproc_reg *r)
166 /* ACTLR contains SMP bit: make sure you create all cpus first! */
167 asm volatile("mrc p15, 0, %0, c1, c0, 1\n" : "=r" (actlr));
168 /* Make the SMP bit consistent with the guest configuration */
169 if (atomic_read(&vcpu->kvm->online_vcpus) > 1)
174 vcpu_cp15(vcpu, c1_ACTLR) = actlr;
178 * TRM entries: A7:4.3.50, A15:4.3.49
179 * R/O WI (even if NSACR.NS_L2ERR, a write of 1 is ignored).
181 static bool access_l2ectlr(struct kvm_vcpu *vcpu,
182 const struct coproc_params *p,
183 const struct coproc_reg *r)
186 return ignore_write(vcpu, p);
188 *vcpu_reg(vcpu, p->Rt1) = 0;
193 * See note at ARMv7 ARM B1.14.4 (TL;DR: S/W ops are not easily virtualized).
195 static bool access_dcsw(struct kvm_vcpu *vcpu,
196 const struct coproc_params *p,
197 const struct coproc_reg *r)
200 return read_from_write_only(vcpu, p);
202 kvm_set_way_flush(vcpu);
207 * Generic accessor for VM registers. Only called as long as HCR_TVM
208 * is set. If the guest enables the MMU, we stop trapping the VM
209 * sys_regs and leave it in complete control of the caches.
211 * Used by the cpu-specific code.
213 bool access_vm_reg(struct kvm_vcpu *vcpu,
214 const struct coproc_params *p,
215 const struct coproc_reg *r)
217 bool was_enabled = vcpu_has_cache_enabled(vcpu);
219 BUG_ON(!p->is_write);
221 vcpu_cp15(vcpu, r->reg) = *vcpu_reg(vcpu, p->Rt1);
223 vcpu_cp15(vcpu, r->reg + 1) = *vcpu_reg(vcpu, p->Rt2);
225 kvm_toggle_cache(vcpu, was_enabled);
230 * We could trap ID_DFR0 and tell the guest we don't support performance
231 * monitoring. Unfortunately the patch to make the kernel check ID_DFR0 was
232 * NAKed, so it will read the PMCR anyway.
234 * Therefore we tell the guest we have 0 counters. Unfortunately, we
235 * must always support PMCCNTR (the cycle counter): we just RAZ/WI for
236 * all PM registers, which doesn't crash the guest kernel at least.
238 static bool pm_fake(struct kvm_vcpu *vcpu,
239 const struct coproc_params *p,
240 const struct coproc_reg *r)
243 return ignore_write(vcpu, p);
245 return read_zero(vcpu, p);
248 #define access_pmcr pm_fake
249 #define access_pmcntenset pm_fake
250 #define access_pmcntenclr pm_fake
251 #define access_pmovsr pm_fake
252 #define access_pmselr pm_fake
253 #define access_pmceid0 pm_fake
254 #define access_pmceid1 pm_fake
255 #define access_pmccntr pm_fake
256 #define access_pmxevtyper pm_fake
257 #define access_pmxevcntr pm_fake
258 #define access_pmuserenr pm_fake
259 #define access_pmintenset pm_fake
260 #define access_pmintenclr pm_fake
262 /* Architected CP15 registers.
263 * CRn denotes the primary register number, but is copied to the CRm in the
264 * user space API for 64-bit register access in line with the terminology used
266 * Important: Must be sorted ascending by CRn, CRM, Op1, Op2 and with 64-bit
267 * registers preceding 32-bit ones.
269 static const struct coproc_reg cp15_regs[] = {
270 /* MPIDR: we use VMPIDR for guest access. */
271 { CRn( 0), CRm( 0), Op1( 0), Op2( 5), is32,
272 NULL, reset_mpidr, c0_MPIDR },
274 /* CSSELR: swapped by interrupt.S. */
275 { CRn( 0), CRm( 0), Op1( 2), Op2( 0), is32,
276 NULL, reset_unknown, c0_CSSELR },
278 /* ACTLR: trapped by HCR.TAC bit. */
279 { CRn( 1), CRm( 0), Op1( 0), Op2( 1), is32,
280 access_actlr, reset_actlr, c1_ACTLR },
282 /* CPACR: swapped by interrupt.S. */
283 { CRn( 1), CRm( 0), Op1( 0), Op2( 2), is32,
284 NULL, reset_val, c1_CPACR, 0x00000000 },
286 /* TTBR0/TTBR1/TTBCR: swapped by interrupt.S. */
287 { CRm64( 2), Op1( 0), is64, access_vm_reg, reset_unknown64, c2_TTBR0 },
288 { CRn(2), CRm( 0), Op1( 0), Op2( 0), is32,
289 access_vm_reg, reset_unknown, c2_TTBR0 },
290 { CRn(2), CRm( 0), Op1( 0), Op2( 1), is32,
291 access_vm_reg, reset_unknown, c2_TTBR1 },
292 { CRn( 2), CRm( 0), Op1( 0), Op2( 2), is32,
293 access_vm_reg, reset_val, c2_TTBCR, 0x00000000 },
294 { CRm64( 2), Op1( 1), is64, access_vm_reg, reset_unknown64, c2_TTBR1 },
297 /* DACR: swapped by interrupt.S. */
298 { CRn( 3), CRm( 0), Op1( 0), Op2( 0), is32,
299 access_vm_reg, reset_unknown, c3_DACR },
301 /* DFSR/IFSR/ADFSR/AIFSR: swapped by interrupt.S. */
302 { CRn( 5), CRm( 0), Op1( 0), Op2( 0), is32,
303 access_vm_reg, reset_unknown, c5_DFSR },
304 { CRn( 5), CRm( 0), Op1( 0), Op2( 1), is32,
305 access_vm_reg, reset_unknown, c5_IFSR },
306 { CRn( 5), CRm( 1), Op1( 0), Op2( 0), is32,
307 access_vm_reg, reset_unknown, c5_ADFSR },
308 { CRn( 5), CRm( 1), Op1( 0), Op2( 1), is32,
309 access_vm_reg, reset_unknown, c5_AIFSR },
311 /* DFAR/IFAR: swapped by interrupt.S. */
312 { CRn( 6), CRm( 0), Op1( 0), Op2( 0), is32,
313 access_vm_reg, reset_unknown, c6_DFAR },
314 { CRn( 6), CRm( 0), Op1( 0), Op2( 2), is32,
315 access_vm_reg, reset_unknown, c6_IFAR },
317 /* PAR swapped by interrupt.S */
318 { CRm64( 7), Op1( 0), is64, NULL, reset_unknown64, c7_PAR },
321 * DC{C,I,CI}SW operations:
323 { CRn( 7), CRm( 6), Op1( 0), Op2( 2), is32, access_dcsw},
324 { CRn( 7), CRm(10), Op1( 0), Op2( 2), is32, access_dcsw},
325 { CRn( 7), CRm(14), Op1( 0), Op2( 2), is32, access_dcsw},
327 * L2CTLR access (guest wants to know #CPUs).
329 { CRn( 9), CRm( 0), Op1( 1), Op2( 2), is32,
330 access_l2ctlr, reset_l2ctlr, c9_L2CTLR },
331 { CRn( 9), CRm( 0), Op1( 1), Op2( 3), is32, access_l2ectlr},
334 * Dummy performance monitor implementation.
336 { CRn( 9), CRm(12), Op1( 0), Op2( 0), is32, access_pmcr},
337 { CRn( 9), CRm(12), Op1( 0), Op2( 1), is32, access_pmcntenset},
338 { CRn( 9), CRm(12), Op1( 0), Op2( 2), is32, access_pmcntenclr},
339 { CRn( 9), CRm(12), Op1( 0), Op2( 3), is32, access_pmovsr},
340 { CRn( 9), CRm(12), Op1( 0), Op2( 5), is32, access_pmselr},
341 { CRn( 9), CRm(12), Op1( 0), Op2( 6), is32, access_pmceid0},
342 { CRn( 9), CRm(12), Op1( 0), Op2( 7), is32, access_pmceid1},
343 { CRn( 9), CRm(13), Op1( 0), Op2( 0), is32, access_pmccntr},
344 { CRn( 9), CRm(13), Op1( 0), Op2( 1), is32, access_pmxevtyper},
345 { CRn( 9), CRm(13), Op1( 0), Op2( 2), is32, access_pmxevcntr},
346 { CRn( 9), CRm(14), Op1( 0), Op2( 0), is32, access_pmuserenr},
347 { CRn( 9), CRm(14), Op1( 0), Op2( 1), is32, access_pmintenset},
348 { CRn( 9), CRm(14), Op1( 0), Op2( 2), is32, access_pmintenclr},
350 /* PRRR/NMRR (aka MAIR0/MAIR1): swapped by interrupt.S. */
351 { CRn(10), CRm( 2), Op1( 0), Op2( 0), is32,
352 access_vm_reg, reset_unknown, c10_PRRR},
353 { CRn(10), CRm( 2), Op1( 0), Op2( 1), is32,
354 access_vm_reg, reset_unknown, c10_NMRR},
356 /* AMAIR0/AMAIR1: swapped by interrupt.S. */
357 { CRn(10), CRm( 3), Op1( 0), Op2( 0), is32,
358 access_vm_reg, reset_unknown, c10_AMAIR0},
359 { CRn(10), CRm( 3), Op1( 0), Op2( 1), is32,
360 access_vm_reg, reset_unknown, c10_AMAIR1},
362 /* VBAR: swapped by interrupt.S. */
363 { CRn(12), CRm( 0), Op1( 0), Op2( 0), is32,
364 NULL, reset_val, c12_VBAR, 0x00000000 },
366 /* CONTEXTIDR/TPIDRURW/TPIDRURO/TPIDRPRW: swapped by interrupt.S. */
367 { CRn(13), CRm( 0), Op1( 0), Op2( 1), is32,
368 access_vm_reg, reset_val, c13_CID, 0x00000000 },
369 { CRn(13), CRm( 0), Op1( 0), Op2( 2), is32,
370 NULL, reset_unknown, c13_TID_URW },
371 { CRn(13), CRm( 0), Op1( 0), Op2( 3), is32,
372 NULL, reset_unknown, c13_TID_URO },
373 { CRn(13), CRm( 0), Op1( 0), Op2( 4), is32,
374 NULL, reset_unknown, c13_TID_PRIV },
376 /* CNTKCTL: swapped by interrupt.S. */
377 { CRn(14), CRm( 1), Op1( 0), Op2( 0), is32,
378 NULL, reset_val, c14_CNTKCTL, 0x00000000 },
380 /* The Configuration Base Address Register. */
381 { CRn(15), CRm( 0), Op1( 4), Op2( 0), is32, access_cbar},
384 static int check_reg_table(const struct coproc_reg *table, unsigned int n)
388 for (i = 1; i < n; i++) {
389 if (cmp_reg(&table[i-1], &table[i]) >= 0) {
390 kvm_err("reg table %p out of order (%d)\n", table, i - 1);
398 /* Target specific emulation tables */
399 static struct kvm_coproc_target_table *target_tables[KVM_ARM_NUM_TARGETS];
401 void kvm_register_target_coproc_table(struct kvm_coproc_target_table *table)
403 BUG_ON(check_reg_table(table->table, table->num));
404 target_tables[table->target] = table;
407 /* Get specific register table for this target. */
408 static const struct coproc_reg *get_target_table(unsigned target, size_t *num)
410 struct kvm_coproc_target_table *table;
412 table = target_tables[target];
417 static const struct coproc_reg *find_reg(const struct coproc_params *params,
418 const struct coproc_reg table[],
423 for (i = 0; i < num; i++) {
424 const struct coproc_reg *r = &table[i];
426 if (params->is_64bit != r->is_64bit)
428 if (params->CRn != r->CRn)
430 if (params->CRm != r->CRm)
432 if (params->Op1 != r->Op1)
434 if (params->Op2 != r->Op2)
442 static int emulate_cp15(struct kvm_vcpu *vcpu,
443 const struct coproc_params *params)
446 const struct coproc_reg *table, *r;
448 trace_kvm_emulate_cp15_imp(params->Op1, params->Rt1, params->CRn,
449 params->CRm, params->Op2, params->is_write);
451 table = get_target_table(vcpu->arch.target, &num);
453 /* Search target-specific then generic table. */
454 r = find_reg(params, table, num);
456 r = find_reg(params, cp15_regs, ARRAY_SIZE(cp15_regs));
459 /* If we don't have an accessor, we should never get here! */
462 if (likely(r->access(vcpu, params, r))) {
463 /* Skip instruction, since it was emulated */
464 kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
467 /* If access function fails, it should complain. */
469 kvm_err("Unsupported guest CP15 access at: %08lx\n",
471 print_cp_instr(params);
473 kvm_inject_undefined(vcpu);
478 * kvm_handle_cp15_64 -- handles a mrrc/mcrr trap on a guest CP15 access
479 * @vcpu: The VCPU pointer
480 * @run: The kvm_run struct
482 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu, struct kvm_run *run)
484 struct coproc_params params;
486 params.CRn = (kvm_vcpu_get_hsr(vcpu) >> 1) & 0xf;
487 params.Rt1 = (kvm_vcpu_get_hsr(vcpu) >> 5) & 0xf;
488 params.is_write = ((kvm_vcpu_get_hsr(vcpu) & 1) == 0);
489 params.is_64bit = true;
491 params.Op1 = (kvm_vcpu_get_hsr(vcpu) >> 16) & 0xf;
493 params.Rt2 = (kvm_vcpu_get_hsr(vcpu) >> 10) & 0xf;
496 return emulate_cp15(vcpu, ¶ms);
499 static void reset_coproc_regs(struct kvm_vcpu *vcpu,
500 const struct coproc_reg *table, size_t num)
504 for (i = 0; i < num; i++)
506 table[i].reset(vcpu, &table[i]);
510 * kvm_handle_cp15_32 -- handles a mrc/mcr trap on a guest CP15 access
511 * @vcpu: The VCPU pointer
512 * @run: The kvm_run struct
514 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu, struct kvm_run *run)
516 struct coproc_params params;
518 params.CRm = (kvm_vcpu_get_hsr(vcpu) >> 1) & 0xf;
519 params.Rt1 = (kvm_vcpu_get_hsr(vcpu) >> 5) & 0xf;
520 params.is_write = ((kvm_vcpu_get_hsr(vcpu) & 1) == 0);
521 params.is_64bit = false;
523 params.CRn = (kvm_vcpu_get_hsr(vcpu) >> 10) & 0xf;
524 params.Op1 = (kvm_vcpu_get_hsr(vcpu) >> 14) & 0x7;
525 params.Op2 = (kvm_vcpu_get_hsr(vcpu) >> 17) & 0x7;
528 return emulate_cp15(vcpu, ¶ms);
531 /******************************************************************************
533 *****************************************************************************/
535 static bool index_to_params(u64 id, struct coproc_params *params)
537 switch (id & KVM_REG_SIZE_MASK) {
538 case KVM_REG_SIZE_U32:
539 /* Any unused index bits means it's not valid. */
540 if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK
541 | KVM_REG_ARM_COPROC_MASK
542 | KVM_REG_ARM_32_CRN_MASK
543 | KVM_REG_ARM_CRM_MASK
544 | KVM_REG_ARM_OPC1_MASK
545 | KVM_REG_ARM_32_OPC2_MASK))
548 params->is_64bit = false;
549 params->CRn = ((id & KVM_REG_ARM_32_CRN_MASK)
550 >> KVM_REG_ARM_32_CRN_SHIFT);
551 params->CRm = ((id & KVM_REG_ARM_CRM_MASK)
552 >> KVM_REG_ARM_CRM_SHIFT);
553 params->Op1 = ((id & KVM_REG_ARM_OPC1_MASK)
554 >> KVM_REG_ARM_OPC1_SHIFT);
555 params->Op2 = ((id & KVM_REG_ARM_32_OPC2_MASK)
556 >> KVM_REG_ARM_32_OPC2_SHIFT);
558 case KVM_REG_SIZE_U64:
559 /* Any unused index bits means it's not valid. */
560 if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK
561 | KVM_REG_ARM_COPROC_MASK
562 | KVM_REG_ARM_CRM_MASK
563 | KVM_REG_ARM_OPC1_MASK))
565 params->is_64bit = true;
566 /* CRm to CRn: see cp15_to_index for details */
567 params->CRn = ((id & KVM_REG_ARM_CRM_MASK)
568 >> KVM_REG_ARM_CRM_SHIFT);
569 params->Op1 = ((id & KVM_REG_ARM_OPC1_MASK)
570 >> KVM_REG_ARM_OPC1_SHIFT);
579 /* Decode an index value, and find the cp15 coproc_reg entry. */
580 static const struct coproc_reg *index_to_coproc_reg(struct kvm_vcpu *vcpu,
584 const struct coproc_reg *table, *r;
585 struct coproc_params params;
587 /* We only do cp15 for now. */
588 if ((id & KVM_REG_ARM_COPROC_MASK) >> KVM_REG_ARM_COPROC_SHIFT != 15)
591 if (!index_to_params(id, ¶ms))
594 table = get_target_table(vcpu->arch.target, &num);
595 r = find_reg(¶ms, table, num);
597 r = find_reg(¶ms, cp15_regs, ARRAY_SIZE(cp15_regs));
599 /* Not saved in the cp15 array? */
607 * These are the invariant cp15 registers: we let the guest see the host
608 * versions of these, so they're part of the guest state.
610 * A future CPU may provide a mechanism to present different values to
611 * the guest, or a future kvm may trap them.
613 /* Unfortunately, there's no register-argument for mrc, so generate. */
614 #define FUNCTION_FOR32(crn, crm, op1, op2, name) \
615 static void get_##name(struct kvm_vcpu *v, \
616 const struct coproc_reg *r) \
620 asm volatile("mrc p15, " __stringify(op1) \
621 ", %0, c" __stringify(crn) \
622 ", c" __stringify(crm) \
623 ", " __stringify(op2) "\n" : "=r" (val)); \
624 ((struct coproc_reg *)r)->val = val; \
627 FUNCTION_FOR32(0, 0, 0, 0, MIDR)
628 FUNCTION_FOR32(0, 0, 0, 1, CTR)
629 FUNCTION_FOR32(0, 0, 0, 2, TCMTR)
630 FUNCTION_FOR32(0, 0, 0, 3, TLBTR)
631 FUNCTION_FOR32(0, 0, 0, 6, REVIDR)
632 FUNCTION_FOR32(0, 1, 0, 0, ID_PFR0)
633 FUNCTION_FOR32(0, 1, 0, 1, ID_PFR1)
634 FUNCTION_FOR32(0, 1, 0, 2, ID_DFR0)
635 FUNCTION_FOR32(0, 1, 0, 3, ID_AFR0)
636 FUNCTION_FOR32(0, 1, 0, 4, ID_MMFR0)
637 FUNCTION_FOR32(0, 1, 0, 5, ID_MMFR1)
638 FUNCTION_FOR32(0, 1, 0, 6, ID_MMFR2)
639 FUNCTION_FOR32(0, 1, 0, 7, ID_MMFR3)
640 FUNCTION_FOR32(0, 2, 0, 0, ID_ISAR0)
641 FUNCTION_FOR32(0, 2, 0, 1, ID_ISAR1)
642 FUNCTION_FOR32(0, 2, 0, 2, ID_ISAR2)
643 FUNCTION_FOR32(0, 2, 0, 3, ID_ISAR3)
644 FUNCTION_FOR32(0, 2, 0, 4, ID_ISAR4)
645 FUNCTION_FOR32(0, 2, 0, 5, ID_ISAR5)
646 FUNCTION_FOR32(0, 0, 1, 1, CLIDR)
647 FUNCTION_FOR32(0, 0, 1, 7, AIDR)
649 /* ->val is filled in by kvm_invariant_coproc_table_init() */
650 static struct coproc_reg invariant_cp15[] = {
651 { CRn( 0), CRm( 0), Op1( 0), Op2( 0), is32, NULL, get_MIDR },
652 { CRn( 0), CRm( 0), Op1( 0), Op2( 1), is32, NULL, get_CTR },
653 { CRn( 0), CRm( 0), Op1( 0), Op2( 2), is32, NULL, get_TCMTR },
654 { CRn( 0), CRm( 0), Op1( 0), Op2( 3), is32, NULL, get_TLBTR },
655 { CRn( 0), CRm( 0), Op1( 0), Op2( 6), is32, NULL, get_REVIDR },
657 { CRn( 0), CRm( 0), Op1( 1), Op2( 1), is32, NULL, get_CLIDR },
658 { CRn( 0), CRm( 0), Op1( 1), Op2( 7), is32, NULL, get_AIDR },
660 { CRn( 0), CRm( 1), Op1( 0), Op2( 0), is32, NULL, get_ID_PFR0 },
661 { CRn( 0), CRm( 1), Op1( 0), Op2( 1), is32, NULL, get_ID_PFR1 },
662 { CRn( 0), CRm( 1), Op1( 0), Op2( 2), is32, NULL, get_ID_DFR0 },
663 { CRn( 0), CRm( 1), Op1( 0), Op2( 3), is32, NULL, get_ID_AFR0 },
664 { CRn( 0), CRm( 1), Op1( 0), Op2( 4), is32, NULL, get_ID_MMFR0 },
665 { CRn( 0), CRm( 1), Op1( 0), Op2( 5), is32, NULL, get_ID_MMFR1 },
666 { CRn( 0), CRm( 1), Op1( 0), Op2( 6), is32, NULL, get_ID_MMFR2 },
667 { CRn( 0), CRm( 1), Op1( 0), Op2( 7), is32, NULL, get_ID_MMFR3 },
669 { CRn( 0), CRm( 2), Op1( 0), Op2( 0), is32, NULL, get_ID_ISAR0 },
670 { CRn( 0), CRm( 2), Op1( 0), Op2( 1), is32, NULL, get_ID_ISAR1 },
671 { CRn( 0), CRm( 2), Op1( 0), Op2( 2), is32, NULL, get_ID_ISAR2 },
672 { CRn( 0), CRm( 2), Op1( 0), Op2( 3), is32, NULL, get_ID_ISAR3 },
673 { CRn( 0), CRm( 2), Op1( 0), Op2( 4), is32, NULL, get_ID_ISAR4 },
674 { CRn( 0), CRm( 2), Op1( 0), Op2( 5), is32, NULL, get_ID_ISAR5 },
678 * Reads a register value from a userspace address to a kernel
679 * variable. Make sure that register size matches sizeof(*__val).
681 static int reg_from_user(void *val, const void __user *uaddr, u64 id)
683 if (copy_from_user(val, uaddr, KVM_REG_SIZE(id)) != 0)
689 * Writes a register value to a userspace address from a kernel variable.
690 * Make sure that register size matches sizeof(*__val).
692 static int reg_to_user(void __user *uaddr, const void *val, u64 id)
694 if (copy_to_user(uaddr, val, KVM_REG_SIZE(id)) != 0)
699 static int get_invariant_cp15(u64 id, void __user *uaddr)
701 struct coproc_params params;
702 const struct coproc_reg *r;
705 if (!index_to_params(id, ¶ms))
708 r = find_reg(¶ms, invariant_cp15, ARRAY_SIZE(invariant_cp15));
713 if (KVM_REG_SIZE(id) == 4) {
716 ret = reg_to_user(uaddr, &val, id);
717 } else if (KVM_REG_SIZE(id) == 8) {
718 ret = reg_to_user(uaddr, &r->val, id);
723 static int set_invariant_cp15(u64 id, void __user *uaddr)
725 struct coproc_params params;
726 const struct coproc_reg *r;
730 if (!index_to_params(id, ¶ms))
732 r = find_reg(¶ms, invariant_cp15, ARRAY_SIZE(invariant_cp15));
737 if (KVM_REG_SIZE(id) == 4) {
740 err = reg_from_user(&val32, uaddr, id);
743 } else if (KVM_REG_SIZE(id) == 8) {
744 err = reg_from_user(&val, uaddr, id);
749 /* This is what we mean by invariant: you can't change it. */
756 static bool is_valid_cache(u32 val)
760 if (val >= CSSELR_MAX)
763 /* Bottom bit is Instruction or Data bit. Next 3 bits are level. */
765 ctype = (cache_levels >> (level * 3)) & 7;
768 case 0: /* No cache */
770 case 1: /* Instruction cache only */
772 case 2: /* Data cache only */
773 case 4: /* Unified cache */
775 case 3: /* Separate instruction and data caches */
777 default: /* Reserved: we can't know instruction or data. */
782 /* Which cache CCSIDR represents depends on CSSELR value. */
783 static u32 get_ccsidr(u32 csselr)
787 /* Make sure noone else changes CSSELR during this! */
789 /* Put value into CSSELR */
790 asm volatile("mcr p15, 2, %0, c0, c0, 0" : : "r" (csselr));
792 /* Read result out of CCSIDR */
793 asm volatile("mrc p15, 1, %0, c0, c0, 0" : "=r" (ccsidr));
799 static int demux_c15_get(u64 id, void __user *uaddr)
802 u32 __user *uval = uaddr;
804 /* Fail if we have unknown bits set. */
805 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
806 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
809 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
810 case KVM_REG_ARM_DEMUX_ID_CCSIDR:
811 if (KVM_REG_SIZE(id) != 4)
813 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
814 >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
815 if (!is_valid_cache(val))
818 return put_user(get_ccsidr(val), uval);
824 static int demux_c15_set(u64 id, void __user *uaddr)
827 u32 __user *uval = uaddr;
829 /* Fail if we have unknown bits set. */
830 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
831 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
834 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
835 case KVM_REG_ARM_DEMUX_ID_CCSIDR:
836 if (KVM_REG_SIZE(id) != 4)
838 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
839 >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
840 if (!is_valid_cache(val))
843 if (get_user(newval, uval))
846 /* This is also invariant: you can't change it. */
847 if (newval != get_ccsidr(val))
856 static const int vfp_sysregs[] = { KVM_REG_ARM_VFP_FPEXC,
857 KVM_REG_ARM_VFP_FPSCR,
858 KVM_REG_ARM_VFP_FPINST,
859 KVM_REG_ARM_VFP_FPINST2,
860 KVM_REG_ARM_VFP_MVFR0,
861 KVM_REG_ARM_VFP_MVFR1,
862 KVM_REG_ARM_VFP_FPSID };
864 static unsigned int num_fp_regs(void)
866 if (((fmrx(MVFR0) & MVFR0_A_SIMD_MASK) >> MVFR0_A_SIMD_BIT) == 2)
872 static unsigned int num_vfp_regs(void)
874 /* Normal FP regs + control regs. */
875 return num_fp_regs() + ARRAY_SIZE(vfp_sysregs);
878 static int copy_vfp_regids(u64 __user *uindices)
881 const u64 u32reg = KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_VFP;
882 const u64 u64reg = KVM_REG_ARM | KVM_REG_SIZE_U64 | KVM_REG_ARM_VFP;
884 for (i = 0; i < num_fp_regs(); i++) {
885 if (put_user((u64reg | KVM_REG_ARM_VFP_BASE_REG) + i,
891 for (i = 0; i < ARRAY_SIZE(vfp_sysregs); i++) {
892 if (put_user(u32reg | vfp_sysregs[i], uindices))
897 return num_vfp_regs();
900 static int vfp_get_reg(const struct kvm_vcpu *vcpu, u64 id, void __user *uaddr)
902 u32 vfpid = (id & KVM_REG_ARM_VFP_MASK);
905 /* Fail if we have unknown bits set. */
906 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
907 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
910 if (vfpid < num_fp_regs()) {
911 if (KVM_REG_SIZE(id) != 8)
913 return reg_to_user(uaddr, &vcpu->arch.ctxt.vfp.fpregs[vfpid],
917 /* FP control registers are all 32 bit. */
918 if (KVM_REG_SIZE(id) != 4)
922 case KVM_REG_ARM_VFP_FPEXC:
923 return reg_to_user(uaddr, &vcpu->arch.ctxt.vfp.fpexc, id);
924 case KVM_REG_ARM_VFP_FPSCR:
925 return reg_to_user(uaddr, &vcpu->arch.ctxt.vfp.fpscr, id);
926 case KVM_REG_ARM_VFP_FPINST:
927 return reg_to_user(uaddr, &vcpu->arch.ctxt.vfp.fpinst, id);
928 case KVM_REG_ARM_VFP_FPINST2:
929 return reg_to_user(uaddr, &vcpu->arch.ctxt.vfp.fpinst2, id);
930 case KVM_REG_ARM_VFP_MVFR0:
932 return reg_to_user(uaddr, &val, id);
933 case KVM_REG_ARM_VFP_MVFR1:
935 return reg_to_user(uaddr, &val, id);
936 case KVM_REG_ARM_VFP_FPSID:
938 return reg_to_user(uaddr, &val, id);
944 static int vfp_set_reg(struct kvm_vcpu *vcpu, u64 id, const void __user *uaddr)
946 u32 vfpid = (id & KVM_REG_ARM_VFP_MASK);
949 /* Fail if we have unknown bits set. */
950 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
951 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
954 if (vfpid < num_fp_regs()) {
955 if (KVM_REG_SIZE(id) != 8)
957 return reg_from_user(&vcpu->arch.ctxt.vfp.fpregs[vfpid],
961 /* FP control registers are all 32 bit. */
962 if (KVM_REG_SIZE(id) != 4)
966 case KVM_REG_ARM_VFP_FPEXC:
967 return reg_from_user(&vcpu->arch.ctxt.vfp.fpexc, uaddr, id);
968 case KVM_REG_ARM_VFP_FPSCR:
969 return reg_from_user(&vcpu->arch.ctxt.vfp.fpscr, uaddr, id);
970 case KVM_REG_ARM_VFP_FPINST:
971 return reg_from_user(&vcpu->arch.ctxt.vfp.fpinst, uaddr, id);
972 case KVM_REG_ARM_VFP_FPINST2:
973 return reg_from_user(&vcpu->arch.ctxt.vfp.fpinst2, uaddr, id);
974 /* These are invariant. */
975 case KVM_REG_ARM_VFP_MVFR0:
976 if (reg_from_user(&val, uaddr, id))
978 if (val != fmrx(MVFR0))
981 case KVM_REG_ARM_VFP_MVFR1:
982 if (reg_from_user(&val, uaddr, id))
984 if (val != fmrx(MVFR1))
987 case KVM_REG_ARM_VFP_FPSID:
988 if (reg_from_user(&val, uaddr, id))
990 if (val != fmrx(FPSID))
997 #else /* !CONFIG_VFPv3 */
998 static unsigned int num_vfp_regs(void)
1003 static int copy_vfp_regids(u64 __user *uindices)
1008 static int vfp_get_reg(const struct kvm_vcpu *vcpu, u64 id, void __user *uaddr)
1013 static int vfp_set_reg(struct kvm_vcpu *vcpu, u64 id, const void __user *uaddr)
1017 #endif /* !CONFIG_VFPv3 */
1019 int kvm_arm_coproc_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
1021 const struct coproc_reg *r;
1022 void __user *uaddr = (void __user *)(long)reg->addr;
1025 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
1026 return demux_c15_get(reg->id, uaddr);
1028 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_VFP)
1029 return vfp_get_reg(vcpu, reg->id, uaddr);
1031 r = index_to_coproc_reg(vcpu, reg->id);
1033 return get_invariant_cp15(reg->id, uaddr);
1036 if (KVM_REG_SIZE(reg->id) == 8) {
1039 val = vcpu_cp15_reg64_get(vcpu, r);
1040 ret = reg_to_user(uaddr, &val, reg->id);
1041 } else if (KVM_REG_SIZE(reg->id) == 4) {
1042 ret = reg_to_user(uaddr, &vcpu_cp15(vcpu, r->reg), reg->id);
1048 int kvm_arm_coproc_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
1050 const struct coproc_reg *r;
1051 void __user *uaddr = (void __user *)(long)reg->addr;
1054 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
1055 return demux_c15_set(reg->id, uaddr);
1057 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_VFP)
1058 return vfp_set_reg(vcpu, reg->id, uaddr);
1060 r = index_to_coproc_reg(vcpu, reg->id);
1062 return set_invariant_cp15(reg->id, uaddr);
1065 if (KVM_REG_SIZE(reg->id) == 8) {
1068 ret = reg_from_user(&val, uaddr, reg->id);
1070 vcpu_cp15_reg64_set(vcpu, r, val);
1071 } else if (KVM_REG_SIZE(reg->id) == 4) {
1072 ret = reg_from_user(&vcpu_cp15(vcpu, r->reg), uaddr, reg->id);
1078 static unsigned int num_demux_regs(void)
1080 unsigned int i, count = 0;
1082 for (i = 0; i < CSSELR_MAX; i++)
1083 if (is_valid_cache(i))
1089 static int write_demux_regids(u64 __user *uindices)
1091 u64 val = KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX;
1094 val |= KVM_REG_ARM_DEMUX_ID_CCSIDR;
1095 for (i = 0; i < CSSELR_MAX; i++) {
1096 if (!is_valid_cache(i))
1098 if (put_user(val | i, uindices))
1105 static u64 cp15_to_index(const struct coproc_reg *reg)
1107 u64 val = KVM_REG_ARM | (15 << KVM_REG_ARM_COPROC_SHIFT);
1108 if (reg->is_64bit) {
1109 val |= KVM_REG_SIZE_U64;
1110 val |= (reg->Op1 << KVM_REG_ARM_OPC1_SHIFT);
1112 * CRn always denotes the primary coproc. reg. nr. for the
1113 * in-kernel representation, but the user space API uses the
1114 * CRm for the encoding, because it is modelled after the
1115 * MRRC/MCRR instructions: see the ARM ARM rev. c page
1118 val |= (reg->CRn << KVM_REG_ARM_CRM_SHIFT);
1120 val |= KVM_REG_SIZE_U32;
1121 val |= (reg->Op1 << KVM_REG_ARM_OPC1_SHIFT);
1122 val |= (reg->Op2 << KVM_REG_ARM_32_OPC2_SHIFT);
1123 val |= (reg->CRm << KVM_REG_ARM_CRM_SHIFT);
1124 val |= (reg->CRn << KVM_REG_ARM_32_CRN_SHIFT);
1129 static bool copy_reg_to_user(const struct coproc_reg *reg, u64 __user **uind)
1134 if (put_user(cp15_to_index(reg), *uind))
1141 /* Assumed ordered tables, see kvm_coproc_table_init. */
1142 static int walk_cp15(struct kvm_vcpu *vcpu, u64 __user *uind)
1144 const struct coproc_reg *i1, *i2, *end1, *end2;
1145 unsigned int total = 0;
1148 /* We check for duplicates here, to allow arch-specific overrides. */
1149 i1 = get_target_table(vcpu->arch.target, &num);
1152 end2 = cp15_regs + ARRAY_SIZE(cp15_regs);
1154 BUG_ON(i1 == end1 || i2 == end2);
1156 /* Walk carefully, as both tables may refer to the same register. */
1158 int cmp = cmp_reg(i1, i2);
1159 /* target-specific overrides generic entry. */
1161 /* Ignore registers we trap but don't save. */
1163 if (!copy_reg_to_user(i1, &uind))
1168 /* Ignore registers we trap but don't save. */
1170 if (!copy_reg_to_user(i2, &uind))
1176 if (cmp <= 0 && ++i1 == end1)
1178 if (cmp >= 0 && ++i2 == end2)
1184 unsigned long kvm_arm_num_coproc_regs(struct kvm_vcpu *vcpu)
1186 return ARRAY_SIZE(invariant_cp15)
1189 + walk_cp15(vcpu, (u64 __user *)NULL);
1192 int kvm_arm_copy_coproc_indices(struct kvm_vcpu *vcpu, u64 __user *uindices)
1197 /* Then give them all the invariant registers' indices. */
1198 for (i = 0; i < ARRAY_SIZE(invariant_cp15); i++) {
1199 if (put_user(cp15_to_index(&invariant_cp15[i]), uindices))
1204 err = walk_cp15(vcpu, uindices);
1209 err = copy_vfp_regids(uindices);
1214 return write_demux_regids(uindices);
1217 void kvm_coproc_table_init(void)
1221 /* Make sure tables are unique and in order. */
1222 BUG_ON(check_reg_table(cp15_regs, ARRAY_SIZE(cp15_regs)));
1223 BUG_ON(check_reg_table(invariant_cp15, ARRAY_SIZE(invariant_cp15)));
1225 /* We abuse the reset function to overwrite the table itself. */
1226 for (i = 0; i < ARRAY_SIZE(invariant_cp15); i++)
1227 invariant_cp15[i].reset(NULL, &invariant_cp15[i]);
1230 * CLIDR format is awkward, so clean it up. See ARM B4.1.20:
1232 * If software reads the Cache Type fields from Ctype1
1233 * upwards, once it has seen a value of 0b000, no caches
1234 * exist at further-out levels of the hierarchy. So, for
1235 * example, if Ctype3 is the first Cache Type field with a
1236 * value of 0b000, the values of Ctype4 to Ctype7 must be
1239 asm volatile("mrc p15, 1, %0, c0, c0, 1" : "=r" (cache_levels));
1240 for (i = 0; i < 7; i++)
1241 if (((cache_levels >> (i*3)) & 7) == 0)
1243 /* Clear all higher bits. */
1244 cache_levels &= (1 << (i*3))-1;
1248 * kvm_reset_coprocs - sets cp15 registers to reset value
1249 * @vcpu: The VCPU pointer
1251 * This function finds the right table above and sets the registers on the
1252 * virtual CPU struct to their architecturally defined reset values.
1254 void kvm_reset_coprocs(struct kvm_vcpu *vcpu)
1257 const struct coproc_reg *table;
1259 /* Catch someone adding a register without putting in reset entry. */
1260 memset(vcpu->arch.ctxt.cp15, 0x42, sizeof(vcpu->arch.ctxt.cp15));
1262 /* Generic chip reset first (so target could override). */
1263 reset_coproc_regs(vcpu, cp15_regs, ARRAY_SIZE(cp15_regs));
1265 table = get_target_table(vcpu->arch.target, &num);
1266 reset_coproc_regs(vcpu, table, num);
1268 for (num = 1; num < NR_CP15_REGS; num++)
1269 if (vcpu_cp15(vcpu, num) == 0x42424242)
1270 panic("Didn't reset vcpu_cp15(vcpu, %zi)", num);