2 * arch/arm/mach-at91/at572d940hf.c
4 * Antonio R. Costa <costa.antonior@gmail.com>
5 * Copyright (C) 2008 Atmel
7 * Copyright (C) 2005 SAN People
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 #include <linux/module.h>
27 #include <asm/mach/irq.h>
28 #include <asm/mach/arch.h>
29 #include <asm/mach/map.h>
30 #include <mach/at572d940hf.h>
31 #include <mach/at91_pmc.h>
32 #include <mach/at91_rstc.h>
37 static struct map_desc at572d940hf_io_desc[] __initdata = {
39 .virtual = AT91_VA_BASE_SYS,
40 .pfn = __phys_to_pfn(AT91_BASE_SYS),
44 .virtual = AT91_IO_VIRT_BASE - AT572D940HF_SRAM_SIZE,
45 .pfn = __phys_to_pfn(AT572D940HF_SRAM_BASE),
46 .length = AT572D940HF_SRAM_SIZE,
51 /* --------------------------------------------------------------------
53 * -------------------------------------------------------------------- */
56 * The peripheral clocks.
58 static struct clk pioA_clk = {
60 .pmc_mask = 1 << AT572D940HF_ID_PIOA,
61 .type = CLK_TYPE_PERIPHERAL,
63 static struct clk pioB_clk = {
65 .pmc_mask = 1 << AT572D940HF_ID_PIOB,
66 .type = CLK_TYPE_PERIPHERAL,
68 static struct clk pioC_clk = {
70 .pmc_mask = 1 << AT572D940HF_ID_PIOC,
71 .type = CLK_TYPE_PERIPHERAL,
73 static struct clk macb_clk = {
75 .pmc_mask = 1 << AT572D940HF_ID_EMAC,
76 .type = CLK_TYPE_PERIPHERAL,
78 static struct clk usart0_clk = {
80 .pmc_mask = 1 << AT572D940HF_ID_US0,
81 .type = CLK_TYPE_PERIPHERAL,
83 static struct clk usart1_clk = {
85 .pmc_mask = 1 << AT572D940HF_ID_US1,
86 .type = CLK_TYPE_PERIPHERAL,
88 static struct clk usart2_clk = {
90 .pmc_mask = 1 << AT572D940HF_ID_US2,
91 .type = CLK_TYPE_PERIPHERAL,
93 static struct clk mmc_clk = {
95 .pmc_mask = 1 << AT572D940HF_ID_MCI,
96 .type = CLK_TYPE_PERIPHERAL,
98 static struct clk udc_clk = {
100 .pmc_mask = 1 << AT572D940HF_ID_UDP,
101 .type = CLK_TYPE_PERIPHERAL,
103 static struct clk twi0_clk = {
105 .pmc_mask = 1 << AT572D940HF_ID_TWI0,
106 .type = CLK_TYPE_PERIPHERAL,
108 static struct clk spi0_clk = {
110 .pmc_mask = 1 << AT572D940HF_ID_SPI0,
111 .type = CLK_TYPE_PERIPHERAL,
113 static struct clk spi1_clk = {
115 .pmc_mask = 1 << AT572D940HF_ID_SPI1,
116 .type = CLK_TYPE_PERIPHERAL,
118 static struct clk ssc0_clk = {
120 .pmc_mask = 1 << AT572D940HF_ID_SSC0,
121 .type = CLK_TYPE_PERIPHERAL,
123 static struct clk ssc1_clk = {
125 .pmc_mask = 1 << AT572D940HF_ID_SSC1,
126 .type = CLK_TYPE_PERIPHERAL,
128 static struct clk ssc2_clk = {
130 .pmc_mask = 1 << AT572D940HF_ID_SSC2,
131 .type = CLK_TYPE_PERIPHERAL,
133 static struct clk tc0_clk = {
135 .pmc_mask = 1 << AT572D940HF_ID_TC0,
136 .type = CLK_TYPE_PERIPHERAL,
138 static struct clk tc1_clk = {
140 .pmc_mask = 1 << AT572D940HF_ID_TC1,
141 .type = CLK_TYPE_PERIPHERAL,
143 static struct clk tc2_clk = {
145 .pmc_mask = 1 << AT572D940HF_ID_TC2,
146 .type = CLK_TYPE_PERIPHERAL,
148 static struct clk ohci_clk = {
150 .pmc_mask = 1 << AT572D940HF_ID_UHP,
151 .type = CLK_TYPE_PERIPHERAL,
153 static struct clk ssc3_clk = {
155 .pmc_mask = 1 << AT572D940HF_ID_SSC3,
156 .type = CLK_TYPE_PERIPHERAL,
158 static struct clk twi1_clk = {
160 .pmc_mask = 1 << AT572D940HF_ID_TWI1,
161 .type = CLK_TYPE_PERIPHERAL,
163 static struct clk can0_clk = {
165 .pmc_mask = 1 << AT572D940HF_ID_CAN0,
166 .type = CLK_TYPE_PERIPHERAL,
168 static struct clk can1_clk = {
170 .pmc_mask = 1 << AT572D940HF_ID_CAN1,
171 .type = CLK_TYPE_PERIPHERAL,
173 static struct clk mAgicV_clk = {
174 .name = "mAgicV_clk",
175 .pmc_mask = 1 << AT572D940HF_ID_MSIRQ0,
176 .type = CLK_TYPE_PERIPHERAL,
180 static struct clk *periph_clocks[] __initdata = {
209 * The five programmable clocks.
210 * You must configure pin multiplexing to bring these signals out.
212 static struct clk pck0 = {
214 .pmc_mask = AT91_PMC_PCK0,
215 .type = CLK_TYPE_PROGRAMMABLE,
218 static struct clk pck1 = {
220 .pmc_mask = AT91_PMC_PCK1,
221 .type = CLK_TYPE_PROGRAMMABLE,
224 static struct clk pck2 = {
226 .pmc_mask = AT91_PMC_PCK2,
227 .type = CLK_TYPE_PROGRAMMABLE,
230 static struct clk pck3 = {
232 .pmc_mask = AT91_PMC_PCK3,
233 .type = CLK_TYPE_PROGRAMMABLE,
237 static struct clk mAgicV_mem_clk = {
238 .name = "mAgicV_mem_clk",
239 .pmc_mask = AT91_PMC_PCK4,
240 .type = CLK_TYPE_PROGRAMMABLE,
245 static struct clk hck0 = {
247 .pmc_mask = AT91_PMC_HCK0,
248 .type = CLK_TYPE_SYSTEM,
251 static struct clk hck1 = {
253 .pmc_mask = AT91_PMC_HCK1,
254 .type = CLK_TYPE_SYSTEM,
258 static void __init at572d940hf_register_clocks(void)
262 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
263 clk_register(periph_clocks[i]);
269 clk_register(&mAgicV_mem_clk);
275 /* --------------------------------------------------------------------
277 * -------------------------------------------------------------------- */
279 static struct at91_gpio_bank at572d940hf_gpio[] = {
281 .id = AT572D940HF_ID_PIOA,
285 .id = AT572D940HF_ID_PIOB,
289 .id = AT572D940HF_ID_PIOC,
295 static void at572d940hf_reset(void)
297 at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
301 /* --------------------------------------------------------------------
302 * AT572D940HF processor initialization
303 * -------------------------------------------------------------------- */
305 void __init at572d940hf_initialize(unsigned long main_clock)
307 /* Map peripherals */
308 iotable_init(at572d940hf_io_desc, ARRAY_SIZE(at572d940hf_io_desc));
310 at91_arch_reset = at572d940hf_reset;
311 at91_extern_irq = (1 << AT572D940HF_ID_IRQ0) | (1 << AT572D940HF_ID_IRQ1)
312 | (1 << AT572D940HF_ID_IRQ2);
314 /* Init clock subsystem */
315 at91_clock_init(main_clock);
317 /* Register the processor-specific clocks */
318 at572d940hf_register_clocks();
320 /* Register GPIO subsystem */
321 at91_gpio_init(at572d940hf_gpio, 3);
324 /* --------------------------------------------------------------------
325 * Interrupt initialization
326 * -------------------------------------------------------------------- */
329 * The default interrupt priority levels (0 = lowest, 7 = highest).
331 static unsigned int at572d940hf_default_irq_priority[NR_AIC_IRQS] __initdata = {
332 7, /* Advanced Interrupt Controller */
333 7, /* System Peripherals */
334 0, /* Parallel IO Controller A */
335 0, /* Parallel IO Controller B */
336 0, /* Parallel IO Controller C */
341 0, /* Multimedia Card Interface */
342 4, /* USB Device Port */
343 0, /* Two-Wire Interface 0 */
344 6, /* Serial Peripheral Interface 0 */
345 6, /* Serial Peripheral Interface 1 */
346 5, /* Serial Synchronous Controller 0 */
347 5, /* Serial Synchronous Controller 1 */
348 5, /* Serial Synchronous Controller 2 */
349 0, /* Timer Counter 0 */
350 0, /* Timer Counter 1 */
351 0, /* Timer Counter 2 */
352 3, /* USB Host port */
353 3, /* Serial Synchronous Controller 3 */
354 0, /* Two-Wire Interface 1 */
355 0, /* CAN Controller 0 */
356 0, /* CAN Controller 1 */
357 0, /* mAgicV HALT line */
358 0, /* mAgicV SIRQ0 line */
359 0, /* mAgicV exception line */
360 0, /* mAgicV end of DMA line */
361 0, /* Advanced Interrupt Controller */
362 0, /* Advanced Interrupt Controller */
363 0, /* Advanced Interrupt Controller */
366 void __init at572d940hf_init_interrupts(unsigned int priority[NR_AIC_IRQS])
369 priority = at572d940hf_default_irq_priority;
371 /* Initialize the AIC interrupt controller */
372 at91_aic_init(priority);
374 /* Enable GPIO interrupts */
375 at91_gpio_irq_setup();