2 * arch/arm/mach-at91/at91cap9.c
4 * Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com>
5 * Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
6 * Copyright (C) 2007 Atmel Corporation.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
15 #include <linux/module.h>
18 #include <asm/mach/arch.h>
19 #include <asm/mach/map.h>
22 #include <mach/at91cap9.h>
23 #include <mach/at91_pmc.h>
24 #include <mach/at91_rstc.h>
31 /* --------------------------------------------------------------------
33 * -------------------------------------------------------------------- */
36 * The peripheral clocks.
38 static struct clk pioABCD_clk = {
39 .name = "pioABCD_clk",
40 .pmc_mask = 1 << AT91CAP9_ID_PIOABCD,
41 .type = CLK_TYPE_PERIPHERAL,
43 static struct clk mpb0_clk = {
45 .pmc_mask = 1 << AT91CAP9_ID_MPB0,
46 .type = CLK_TYPE_PERIPHERAL,
48 static struct clk mpb1_clk = {
50 .pmc_mask = 1 << AT91CAP9_ID_MPB1,
51 .type = CLK_TYPE_PERIPHERAL,
53 static struct clk mpb2_clk = {
55 .pmc_mask = 1 << AT91CAP9_ID_MPB2,
56 .type = CLK_TYPE_PERIPHERAL,
58 static struct clk mpb3_clk = {
60 .pmc_mask = 1 << AT91CAP9_ID_MPB3,
61 .type = CLK_TYPE_PERIPHERAL,
63 static struct clk mpb4_clk = {
65 .pmc_mask = 1 << AT91CAP9_ID_MPB4,
66 .type = CLK_TYPE_PERIPHERAL,
68 static struct clk usart0_clk = {
70 .pmc_mask = 1 << AT91CAP9_ID_US0,
71 .type = CLK_TYPE_PERIPHERAL,
73 static struct clk usart1_clk = {
75 .pmc_mask = 1 << AT91CAP9_ID_US1,
76 .type = CLK_TYPE_PERIPHERAL,
78 static struct clk usart2_clk = {
80 .pmc_mask = 1 << AT91CAP9_ID_US2,
81 .type = CLK_TYPE_PERIPHERAL,
83 static struct clk mmc0_clk = {
85 .pmc_mask = 1 << AT91CAP9_ID_MCI0,
86 .type = CLK_TYPE_PERIPHERAL,
88 static struct clk mmc1_clk = {
90 .pmc_mask = 1 << AT91CAP9_ID_MCI1,
91 .type = CLK_TYPE_PERIPHERAL,
93 static struct clk can_clk = {
95 .pmc_mask = 1 << AT91CAP9_ID_CAN,
96 .type = CLK_TYPE_PERIPHERAL,
98 static struct clk twi_clk = {
100 .pmc_mask = 1 << AT91CAP9_ID_TWI,
101 .type = CLK_TYPE_PERIPHERAL,
103 static struct clk spi0_clk = {
105 .pmc_mask = 1 << AT91CAP9_ID_SPI0,
106 .type = CLK_TYPE_PERIPHERAL,
108 static struct clk spi1_clk = {
110 .pmc_mask = 1 << AT91CAP9_ID_SPI1,
111 .type = CLK_TYPE_PERIPHERAL,
113 static struct clk ssc0_clk = {
115 .pmc_mask = 1 << AT91CAP9_ID_SSC0,
116 .type = CLK_TYPE_PERIPHERAL,
118 static struct clk ssc1_clk = {
120 .pmc_mask = 1 << AT91CAP9_ID_SSC1,
121 .type = CLK_TYPE_PERIPHERAL,
123 static struct clk ac97_clk = {
125 .pmc_mask = 1 << AT91CAP9_ID_AC97C,
126 .type = CLK_TYPE_PERIPHERAL,
128 static struct clk tcb_clk = {
130 .pmc_mask = 1 << AT91CAP9_ID_TCB,
131 .type = CLK_TYPE_PERIPHERAL,
133 static struct clk pwm_clk = {
135 .pmc_mask = 1 << AT91CAP9_ID_PWMC,
136 .type = CLK_TYPE_PERIPHERAL,
138 static struct clk macb_clk = {
140 .pmc_mask = 1 << AT91CAP9_ID_EMAC,
141 .type = CLK_TYPE_PERIPHERAL,
143 static struct clk aestdes_clk = {
144 .name = "aestdes_clk",
145 .pmc_mask = 1 << AT91CAP9_ID_AESTDES,
146 .type = CLK_TYPE_PERIPHERAL,
148 static struct clk adc_clk = {
150 .pmc_mask = 1 << AT91CAP9_ID_ADC,
151 .type = CLK_TYPE_PERIPHERAL,
153 static struct clk isi_clk = {
155 .pmc_mask = 1 << AT91CAP9_ID_ISI,
156 .type = CLK_TYPE_PERIPHERAL,
158 static struct clk lcdc_clk = {
160 .pmc_mask = 1 << AT91CAP9_ID_LCDC,
161 .type = CLK_TYPE_PERIPHERAL,
163 static struct clk dma_clk = {
165 .pmc_mask = 1 << AT91CAP9_ID_DMA,
166 .type = CLK_TYPE_PERIPHERAL,
168 static struct clk udphs_clk = {
170 .pmc_mask = 1 << AT91CAP9_ID_UDPHS,
171 .type = CLK_TYPE_PERIPHERAL,
173 static struct clk ohci_clk = {
175 .pmc_mask = 1 << AT91CAP9_ID_UHP,
176 .type = CLK_TYPE_PERIPHERAL,
179 static struct clk *periph_clocks[] __initdata = {
211 static struct clk_lookup periph_clocks_lookups[] = {
212 /* One additional fake clock for macb_hclk */
213 CLKDEV_CON_ID("hclk", &macb_clk),
214 CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
215 CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
216 CLKDEV_CON_DEV_ID("mci_clk", "at91_mci.0", &mmc0_clk),
217 CLKDEV_CON_DEV_ID("mci_clk", "at91_mci.1", &mmc1_clk),
218 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
219 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
220 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb_clk),
221 CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
222 CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
223 /* fake hclk clock */
224 CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
225 CLKDEV_CON_ID("pioA", &pioABCD_clk),
226 CLKDEV_CON_ID("pioB", &pioABCD_clk),
227 CLKDEV_CON_ID("pioC", &pioABCD_clk),
228 CLKDEV_CON_ID("pioD", &pioABCD_clk),
231 static struct clk_lookup usart_clocks_lookups[] = {
232 CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
233 CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
234 CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
235 CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
239 * The four programmable clocks.
240 * You must configure pin multiplexing to bring these signals out.
242 static struct clk pck0 = {
244 .pmc_mask = AT91_PMC_PCK0,
245 .type = CLK_TYPE_PROGRAMMABLE,
248 static struct clk pck1 = {
250 .pmc_mask = AT91_PMC_PCK1,
251 .type = CLK_TYPE_PROGRAMMABLE,
254 static struct clk pck2 = {
256 .pmc_mask = AT91_PMC_PCK2,
257 .type = CLK_TYPE_PROGRAMMABLE,
260 static struct clk pck3 = {
262 .pmc_mask = AT91_PMC_PCK3,
263 .type = CLK_TYPE_PROGRAMMABLE,
267 static void __init at91cap9_register_clocks(void)
271 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
272 clk_register(periph_clocks[i]);
274 clkdev_add_table(periph_clocks_lookups,
275 ARRAY_SIZE(periph_clocks_lookups));
276 clkdev_add_table(usart_clocks_lookups,
277 ARRAY_SIZE(usart_clocks_lookups));
285 static struct clk_lookup console_clock_lookup;
287 void __init at91cap9_set_console_clock(int id)
289 if (id >= ARRAY_SIZE(usart_clocks_lookups))
292 console_clock_lookup.con_id = "usart";
293 console_clock_lookup.clk = usart_clocks_lookups[id].clk;
294 clkdev_add(&console_clock_lookup);
297 /* --------------------------------------------------------------------
299 * -------------------------------------------------------------------- */
301 static struct at91_gpio_bank at91cap9_gpio[] __initdata = {
303 .id = AT91CAP9_ID_PIOABCD,
304 .regbase = AT91CAP9_BASE_PIOA,
306 .id = AT91CAP9_ID_PIOABCD,
307 .regbase = AT91CAP9_BASE_PIOB,
309 .id = AT91CAP9_ID_PIOABCD,
310 .regbase = AT91CAP9_BASE_PIOC,
312 .id = AT91CAP9_ID_PIOABCD,
313 .regbase = AT91CAP9_BASE_PIOD,
317 static void at91cap9_restart(char mode, const char *cmd)
319 at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
322 /* --------------------------------------------------------------------
323 * AT91CAP9 processor initialization
324 * -------------------------------------------------------------------- */
326 static void __init at91cap9_map_io(void)
328 at91_init_sram(0, AT91CAP9_SRAM_BASE, AT91CAP9_SRAM_SIZE);
331 static void __init at91cap9_ioremap_registers(void)
333 at91_ioremap_shdwc(AT91CAP9_BASE_SHDWC);
334 at91sam926x_ioremap_pit(AT91CAP9_BASE_PIT);
335 at91sam9_ioremap_smc(0, AT91CAP9_BASE_SMC);
338 static void __init at91cap9_initialize(void)
340 arm_pm_restart = at91cap9_restart;
341 at91_extern_irq = (1 << AT91CAP9_ID_IRQ0) | (1 << AT91CAP9_ID_IRQ1);
343 /* Register GPIO subsystem */
344 at91_gpio_init(at91cap9_gpio, 4);
346 /* Remember the silicon revision */
347 if (cpu_is_at91cap9_revB())
349 else if (cpu_is_at91cap9_revC())
353 /* --------------------------------------------------------------------
354 * Interrupt initialization
355 * -------------------------------------------------------------------- */
358 * The default interrupt priority levels (0 = lowest, 7 = highest).
360 static unsigned int at91cap9_default_irq_priority[NR_AIC_IRQS] __initdata = {
361 7, /* Advanced Interrupt Controller (FIQ) */
362 7, /* System Peripherals */
363 1, /* Parallel IO Controller A, B, C and D */
364 0, /* MP Block Peripheral 0 */
365 0, /* MP Block Peripheral 1 */
366 0, /* MP Block Peripheral 2 */
367 0, /* MP Block Peripheral 3 */
368 0, /* MP Block Peripheral 4 */
372 0, /* Multimedia Card Interface 0 */
373 0, /* Multimedia Card Interface 1 */
375 6, /* Two-Wire Interface */
376 5, /* Serial Peripheral Interface 0 */
377 5, /* Serial Peripheral Interface 1 */
378 4, /* Serial Synchronous Controller 0 */
379 4, /* Serial Synchronous Controller 1 */
380 5, /* AC97 Controller */
381 0, /* Timer Counter 0, 1 and 2 */
382 0, /* Pulse Width Modulation Controller */
384 0, /* Advanced Encryption Standard, Triple DES*/
385 0, /* Analog-to-Digital Converter */
386 0, /* Image Sensor Interface */
387 3, /* LCD Controller */
388 0, /* DMA Controller */
389 2, /* USB Device Port */
390 2, /* USB Host port */
391 0, /* Advanced Interrupt Controller (IRQ0) */
392 0, /* Advanced Interrupt Controller (IRQ1) */
395 struct at91_init_soc __initdata at91cap9_soc = {
396 .map_io = at91cap9_map_io,
397 .default_irq_priority = at91cap9_default_irq_priority,
398 .ioremap_registers = at91cap9_ioremap_registers,
399 .register_clocks = at91cap9_register_clocks,
400 .init = at91cap9_initialize,