arch/arm/mach-at91/at91cap9.c

   1 /*
   2  * arch/arm/mach-at91/at91cap9.c
   3  *
   4  *  Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com>
   5  *  Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
   6  *  Copyright (C) 2007 Atmel Corporation.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  */
  14
  15 #include <linux/module.h>
  16
  17 #include <asm/irq.h>
  18 #include <asm/mach/arch.h>
  19 #include <asm/mach/map.h>
  20
  21 #include <mach/cpu.h>
  22 #include <mach/at91cap9.h>
  23 #include <mach/at91_pmc.h>
  24 #include <mach/at91_rstc.h>
  25
  26 #include "soc.h"
  27 #include "generic.h"
  28 #include "clock.h"
  29 #include "sam9_smc.h"
  30
  31 /* --------------------------------------------------------------------
  32  *  Clocks
  33  * -------------------------------------------------------------------- */
  34
  35 /*
  36  * The peripheral clocks.
  37  */
  38 static struct clk pioABCD_clk = {
  39         .name           = "pioABCD_clk",
  40         .pmc_mask       = 1 << AT91CAP9_ID_PIOABCD,
  41         .type           = CLK_TYPE_PERIPHERAL,
  42 };
  43 static struct clk mpb0_clk = {
  44         .name           = "mpb0_clk",
  45         .pmc_mask       = 1 << AT91CAP9_ID_MPB0,
  46         .type           = CLK_TYPE_PERIPHERAL,
  47 };
  48 static struct clk mpb1_clk = {
  49         .name           = "mpb1_clk",
  50         .pmc_mask       = 1 << AT91CAP9_ID_MPB1,
  51         .type           = CLK_TYPE_PERIPHERAL,
  52 };
  53 static struct clk mpb2_clk = {
  54         .name           = "mpb2_clk",
  55         .pmc_mask       = 1 << AT91CAP9_ID_MPB2,
  56         .type           = CLK_TYPE_PERIPHERAL,
  57 };
  58 static struct clk mpb3_clk = {
  59         .name           = "mpb3_clk",
  60         .pmc_mask       = 1 << AT91CAP9_ID_MPB3,
  61         .type           = CLK_TYPE_PERIPHERAL,
  62 };
  63 static struct clk mpb4_clk = {
  64         .name           = "mpb4_clk",
  65         .pmc_mask       = 1 << AT91CAP9_ID_MPB4,
  66         .type           = CLK_TYPE_PERIPHERAL,
  67 };
  68 static struct clk usart0_clk = {
  69         .name           = "usart0_clk",
  70         .pmc_mask       = 1 << AT91CAP9_ID_US0,
  71         .type           = CLK_TYPE_PERIPHERAL,
  72 };
  73 static struct clk usart1_clk = {
  74         .name           = "usart1_clk",
  75         .pmc_mask       = 1 << AT91CAP9_ID_US1,
  76         .type           = CLK_TYPE_PERIPHERAL,
  77 };
  78 static struct clk usart2_clk = {
  79         .name           = "usart2_clk",
  80         .pmc_mask       = 1 << AT91CAP9_ID_US2,
  81         .type           = CLK_TYPE_PERIPHERAL,
  82 };
  83 static struct clk mmc0_clk = {
  84         .name           = "mci0_clk",
  85         .pmc_mask       = 1 << AT91CAP9_ID_MCI0,
  86         .type           = CLK_TYPE_PERIPHERAL,
  87 };
  88 static struct clk mmc1_clk = {
  89         .name           = "mci1_clk",
  90         .pmc_mask       = 1 << AT91CAP9_ID_MCI1,
  91         .type           = CLK_TYPE_PERIPHERAL,
  92 };
  93 static struct clk can_clk = {
  94         .name           = "can_clk",
  95         .pmc_mask       = 1 << AT91CAP9_ID_CAN,
  96         .type           = CLK_TYPE_PERIPHERAL,
  97 };
  98 static struct clk twi_clk = {
  99         .name           = "twi_clk",
 100         .pmc_mask       = 1 << AT91CAP9_ID_TWI,
 101         .type           = CLK_TYPE_PERIPHERAL,
 102 };
 103 static struct clk spi0_clk = {
 104         .name           = "spi0_clk",
 105         .pmc_mask       = 1 << AT91CAP9_ID_SPI0,
 106         .type           = CLK_TYPE_PERIPHERAL,
 107 };
 108 static struct clk spi1_clk = {
 109         .name           = "spi1_clk",
 110         .pmc_mask       = 1 << AT91CAP9_ID_SPI1,
 111         .type           = CLK_TYPE_PERIPHERAL,
 112 };
 113 static struct clk ssc0_clk = {
 114         .name           = "ssc0_clk",
 115         .pmc_mask       = 1 << AT91CAP9_ID_SSC0,
 116         .type           = CLK_TYPE_PERIPHERAL,
 117 };
 118 static struct clk ssc1_clk = {
 119         .name           = "ssc1_clk",
 120         .pmc_mask       = 1 << AT91CAP9_ID_SSC1,
 121         .type           = CLK_TYPE_PERIPHERAL,
 122 };
 123 static struct clk ac97_clk = {
 124         .name           = "ac97_clk",
 125         .pmc_mask       = 1 << AT91CAP9_ID_AC97C,
 126         .type           = CLK_TYPE_PERIPHERAL,
 127 };
 128 static struct clk tcb_clk = {
 129         .name           = "tcb_clk",
 130         .pmc_mask       = 1 << AT91CAP9_ID_TCB,
 131         .type           = CLK_TYPE_PERIPHERAL,
 132 };
 133 static struct clk pwm_clk = {
 134         .name           = "pwm_clk",
 135         .pmc_mask       = 1 << AT91CAP9_ID_PWMC,
 136         .type           = CLK_TYPE_PERIPHERAL,
 137 };
 138 static struct clk macb_clk = {
 139         .name           = "pclk",
 140         .pmc_mask       = 1 << AT91CAP9_ID_EMAC,
 141         .type           = CLK_TYPE_PERIPHERAL,
 142 };
 143 static struct clk aestdes_clk = {
 144         .name           = "aestdes_clk",
 145         .pmc_mask       = 1 << AT91CAP9_ID_AESTDES,
 146         .type           = CLK_TYPE_PERIPHERAL,
 147 };
 148 static struct clk adc_clk = {
 149         .name           = "adc_clk",
 150         .pmc_mask       = 1 << AT91CAP9_ID_ADC,
 151         .type           = CLK_TYPE_PERIPHERAL,
 152 };
 153 static struct clk isi_clk = {
 154         .name           = "isi_clk",
 155         .pmc_mask       = 1 << AT91CAP9_ID_ISI,
 156         .type           = CLK_TYPE_PERIPHERAL,
 157 };
 158 static struct clk lcdc_clk = {
 159         .name           = "lcdc_clk",
 160         .pmc_mask       = 1 << AT91CAP9_ID_LCDC,
 161         .type           = CLK_TYPE_PERIPHERAL,
 162 };
 163 static struct clk dma_clk = {
 164         .name           = "dma_clk",
 165         .pmc_mask       = 1 << AT91CAP9_ID_DMA,
 166         .type           = CLK_TYPE_PERIPHERAL,
 167 };
 168 static struct clk udphs_clk = {
 169         .name           = "udphs_clk",
 170         .pmc_mask       = 1 << AT91CAP9_ID_UDPHS,
 171         .type           = CLK_TYPE_PERIPHERAL,
 172 };
 173 static struct clk ohci_clk = {
 174         .name           = "ohci_clk",
 175         .pmc_mask       = 1 << AT91CAP9_ID_UHP,
 176         .type           = CLK_TYPE_PERIPHERAL,
 177 };
 178
 179 static struct clk *periph_clocks[] __initdata = {
 180         &pioABCD_clk,
 181         &mpb0_clk,
 182         &mpb1_clk,
 183         &mpb2_clk,
 184         &mpb3_clk,
 185         &mpb4_clk,
 186         &usart0_clk,
 187         &usart1_clk,
 188         &usart2_clk,
 189         &mmc0_clk,
 190         &mmc1_clk,
 191         &can_clk,
 192         &twi_clk,
 193         &spi0_clk,
 194         &spi1_clk,
 195         &ssc0_clk,
 196         &ssc1_clk,
 197         &ac97_clk,
 198         &tcb_clk,
 199         &pwm_clk,
 200         &macb_clk,
 201         &aestdes_clk,
 202         &adc_clk,
 203         &isi_clk,
 204         &lcdc_clk,
 205         &dma_clk,
 206         &udphs_clk,
 207         &ohci_clk,
 208         // irq0 .. irq1
 209 };
 210
 211 static struct clk_lookup periph_clocks_lookups[] = {
 212         /* One additional fake clock for macb_hclk */
 213         CLKDEV_CON_ID("hclk", &macb_clk),
 214         CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
 215         CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
 216         CLKDEV_CON_DEV_ID("mci_clk", "at91_mci.0", &mmc0_clk),
 217         CLKDEV_CON_DEV_ID("mci_clk", "at91_mci.1", &mmc1_clk),
 218         CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
 219         CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
 220         CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb_clk),
 221         CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
 222         CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
 223         /* fake hclk clock */
 224         CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
 225         CLKDEV_CON_ID("pioA", &pioABCD_clk),
 226         CLKDEV_CON_ID("pioB", &pioABCD_clk),
 227         CLKDEV_CON_ID("pioC", &pioABCD_clk),
 228         CLKDEV_CON_ID("pioD", &pioABCD_clk),
 229 };
 230
 231 static struct clk_lookup usart_clocks_lookups[] = {
 232         CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
 233         CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
 234         CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
 235         CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
 236 };
 237
 238 /*
 239  * The four programmable clocks.
 240  * You must configure pin multiplexing to bring these signals out.
 241  */
 242 static struct clk pck0 = {
 243         .name           = "pck0",
 244         .pmc_mask       = AT91_PMC_PCK0,
 245         .type           = CLK_TYPE_PROGRAMMABLE,
 246         .id             = 0,
 247 };
 248 static struct clk pck1 = {
 249         .name           = "pck1",
 250         .pmc_mask       = AT91_PMC_PCK1,
 251         .type           = CLK_TYPE_PROGRAMMABLE,
 252         .id             = 1,
 253 };
 254 static struct clk pck2 = {
 255         .name           = "pck2",
 256         .pmc_mask       = AT91_PMC_PCK2,
 257         .type           = CLK_TYPE_PROGRAMMABLE,
 258         .id             = 2,
 259 };
 260 static struct clk pck3 = {
 261         .name           = "pck3",
 262         .pmc_mask       = AT91_PMC_PCK3,
 263         .type           = CLK_TYPE_PROGRAMMABLE,
 264         .id             = 3,
 265 };
 266
 267 static void __init at91cap9_register_clocks(void)
 268 {
 269         int i;
 270
 271         for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
 272                 clk_register(periph_clocks[i]);
 273
 274         clkdev_add_table(periph_clocks_lookups,
 275                          ARRAY_SIZE(periph_clocks_lookups));
 276         clkdev_add_table(usart_clocks_lookups,
 277                          ARRAY_SIZE(usart_clocks_lookups));
 278
 279         clk_register(&pck0);
 280         clk_register(&pck1);
 281         clk_register(&pck2);
 282         clk_register(&pck3);
 283 }
 284
 285 static struct clk_lookup console_clock_lookup;
 286
 287 void __init at91cap9_set_console_clock(int id)
 288 {
 289         if (id >= ARRAY_SIZE(usart_clocks_lookups))
 290                 return;
 291
 292         console_clock_lookup.con_id = "usart";
 293         console_clock_lookup.clk = usart_clocks_lookups[id].clk;
 294         clkdev_add(&console_clock_lookup);
 295 }
 296
 297 /* --------------------------------------------------------------------
 298  *  GPIO
 299  * -------------------------------------------------------------------- */
 300
 301 static struct at91_gpio_bank at91cap9_gpio[] __initdata = {
 302         {
 303                 .id             = AT91CAP9_ID_PIOABCD,
 304                 .regbase        = AT91CAP9_BASE_PIOA,
 305         }, {
 306                 .id             = AT91CAP9_ID_PIOABCD,
 307                 .regbase        = AT91CAP9_BASE_PIOB,
 308         }, {
 309                 .id             = AT91CAP9_ID_PIOABCD,
 310                 .regbase        = AT91CAP9_BASE_PIOC,
 311         }, {
 312                 .id             = AT91CAP9_ID_PIOABCD,
 313                 .regbase        = AT91CAP9_BASE_PIOD,
 314         }
 315 };
 316
 317 static void at91cap9_restart(char mode, const char *cmd)
 318 {
 319         at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
 320 }
 321
 322 /* --------------------------------------------------------------------
 323  *  AT91CAP9 processor initialization
 324  * -------------------------------------------------------------------- */
 325
 326 static void __init at91cap9_map_io(void)
 327 {
 328         at91_init_sram(0, AT91CAP9_SRAM_BASE, AT91CAP9_SRAM_SIZE);
 329 }
 330
 331 static void __init at91cap9_ioremap_registers(void)
 332 {
 333         at91_ioremap_shdwc(AT91CAP9_BASE_SHDWC);
 334         at91sam926x_ioremap_pit(AT91CAP9_BASE_PIT);
 335         at91sam9_ioremap_smc(0, AT91CAP9_BASE_SMC);
 336 }
 337
 338 static void __init at91cap9_initialize(void)
 339 {
 340         arm_pm_restart = at91cap9_restart;
 341         at91_extern_irq = (1 << AT91CAP9_ID_IRQ0) | (1 << AT91CAP9_ID_IRQ1);
 342
 343         /* Register GPIO subsystem */
 344         at91_gpio_init(at91cap9_gpio, 4);
 345
 346         /* Remember the silicon revision */
 347         if (cpu_is_at91cap9_revB())
 348                 system_rev = 0xB;
 349         else if (cpu_is_at91cap9_revC())
 350                 system_rev = 0xC;
 351 }
 352
 353 /* --------------------------------------------------------------------
 354  *  Interrupt initialization
 355  * -------------------------------------------------------------------- */
 356
 357 /*
 358  * The default interrupt priority levels (0 = lowest, 7 = highest).
 359  */
 360 static unsigned int at91cap9_default_irq_priority[NR_AIC_IRQS] __initdata = {
 361         7,      /* Advanced Interrupt Controller (FIQ) */
 362         7,      /* System Peripherals */
 363         1,      /* Parallel IO Controller A, B, C and D */
 364         0,      /* MP Block Peripheral 0 */
 365         0,      /* MP Block Peripheral 1 */
 366         0,      /* MP Block Peripheral 2 */
 367         0,      /* MP Block Peripheral 3 */
 368         0,      /* MP Block Peripheral 4 */
 369         5,      /* USART 0 */
 370         5,      /* USART 1 */
 371         5,      /* USART 2 */
 372         0,      /* Multimedia Card Interface 0 */
 373         0,      /* Multimedia Card Interface 1 */
 374         3,      /* CAN */
 375         6,      /* Two-Wire Interface */
 376         5,      /* Serial Peripheral Interface 0 */
 377         5,      /* Serial Peripheral Interface 1 */
 378         4,      /* Serial Synchronous Controller 0 */
 379         4,      /* Serial Synchronous Controller 1 */
 380         5,      /* AC97 Controller */
 381         0,      /* Timer Counter 0, 1 and 2 */
 382         0,      /* Pulse Width Modulation Controller */
 383         3,      /* Ethernet */
 384         0,      /* Advanced Encryption Standard, Triple DES*/
 385         0,      /* Analog-to-Digital Converter */
 386         0,      /* Image Sensor Interface */
 387         3,      /* LCD Controller */
 388         0,      /* DMA Controller */
 389         2,      /* USB Device Port */
 390         2,      /* USB Host port */
 391         0,      /* Advanced Interrupt Controller (IRQ0) */
 392         0,      /* Advanced Interrupt Controller (IRQ1) */
 393 };
 394
 395 struct at91_init_soc __initdata at91cap9_soc = {
 396         .map_io = at91cap9_map_io,
 397         .default_irq_priority = at91cap9_default_irq_priority,
 398         .ioremap_registers = at91cap9_ioremap_registers,
 399         .register_clocks = at91cap9_register_clocks,
 400         .init = at91cap9_initialize,
 401 };