2 * arch/arm/mach-at91/at91rm9200.c
4 * Copyright (C) 2005 SAN People
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
13 #include <linux/module.h>
14 #include <linux/reboot.h>
17 #include <asm/mach/arch.h>
18 #include <asm/mach/map.h>
19 #include <asm/system_misc.h>
20 #include <mach/at91rm9200.h>
21 #include <mach/at91_pmc.h>
22 #include <mach/at91_st.h>
32 /* --------------------------------------------------------------------
34 * -------------------------------------------------------------------- */
37 * The peripheral clocks.
39 static struct clk udc_clk = {
41 .pmc_mask = 1 << AT91RM9200_ID_UDP,
42 .type = CLK_TYPE_PERIPHERAL,
44 static struct clk ohci_clk = {
46 .pmc_mask = 1 << AT91RM9200_ID_UHP,
47 .type = CLK_TYPE_PERIPHERAL,
49 static struct clk ether_clk = {
51 .pmc_mask = 1 << AT91RM9200_ID_EMAC,
52 .type = CLK_TYPE_PERIPHERAL,
54 static struct clk mmc_clk = {
56 .pmc_mask = 1 << AT91RM9200_ID_MCI,
57 .type = CLK_TYPE_PERIPHERAL,
59 static struct clk twi_clk = {
61 .pmc_mask = 1 << AT91RM9200_ID_TWI,
62 .type = CLK_TYPE_PERIPHERAL,
64 static struct clk usart0_clk = {
66 .pmc_mask = 1 << AT91RM9200_ID_US0,
67 .type = CLK_TYPE_PERIPHERAL,
69 static struct clk usart1_clk = {
71 .pmc_mask = 1 << AT91RM9200_ID_US1,
72 .type = CLK_TYPE_PERIPHERAL,
74 static struct clk usart2_clk = {
76 .pmc_mask = 1 << AT91RM9200_ID_US2,
77 .type = CLK_TYPE_PERIPHERAL,
79 static struct clk usart3_clk = {
81 .pmc_mask = 1 << AT91RM9200_ID_US3,
82 .type = CLK_TYPE_PERIPHERAL,
84 static struct clk spi_clk = {
86 .pmc_mask = 1 << AT91RM9200_ID_SPI,
87 .type = CLK_TYPE_PERIPHERAL,
89 static struct clk pioA_clk = {
91 .pmc_mask = 1 << AT91RM9200_ID_PIOA,
92 .type = CLK_TYPE_PERIPHERAL,
94 static struct clk pioB_clk = {
96 .pmc_mask = 1 << AT91RM9200_ID_PIOB,
97 .type = CLK_TYPE_PERIPHERAL,
99 static struct clk pioC_clk = {
101 .pmc_mask = 1 << AT91RM9200_ID_PIOC,
102 .type = CLK_TYPE_PERIPHERAL,
104 static struct clk pioD_clk = {
106 .pmc_mask = 1 << AT91RM9200_ID_PIOD,
107 .type = CLK_TYPE_PERIPHERAL,
109 static struct clk ssc0_clk = {
111 .pmc_mask = 1 << AT91RM9200_ID_SSC0,
112 .type = CLK_TYPE_PERIPHERAL,
114 static struct clk ssc1_clk = {
116 .pmc_mask = 1 << AT91RM9200_ID_SSC1,
117 .type = CLK_TYPE_PERIPHERAL,
119 static struct clk ssc2_clk = {
121 .pmc_mask = 1 << AT91RM9200_ID_SSC2,
122 .type = CLK_TYPE_PERIPHERAL,
124 static struct clk tc0_clk = {
126 .pmc_mask = 1 << AT91RM9200_ID_TC0,
127 .type = CLK_TYPE_PERIPHERAL,
129 static struct clk tc1_clk = {
131 .pmc_mask = 1 << AT91RM9200_ID_TC1,
132 .type = CLK_TYPE_PERIPHERAL,
134 static struct clk tc2_clk = {
136 .pmc_mask = 1 << AT91RM9200_ID_TC2,
137 .type = CLK_TYPE_PERIPHERAL,
139 static struct clk tc3_clk = {
141 .pmc_mask = 1 << AT91RM9200_ID_TC3,
142 .type = CLK_TYPE_PERIPHERAL,
144 static struct clk tc4_clk = {
146 .pmc_mask = 1 << AT91RM9200_ID_TC4,
147 .type = CLK_TYPE_PERIPHERAL,
149 static struct clk tc5_clk = {
151 .pmc_mask = 1 << AT91RM9200_ID_TC5,
152 .type = CLK_TYPE_PERIPHERAL,
155 static struct clk *periph_clocks[] __initdata = {
182 static struct clk_lookup periph_clocks_lookups[] = {
183 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
184 CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
185 CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
186 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tc3_clk),
187 CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.1", &tc4_clk),
188 CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.1", &tc5_clk),
189 CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.0", &ssc0_clk),
190 CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.1", &ssc1_clk),
191 CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.2", &ssc2_clk),
192 CLKDEV_CON_DEV_ID("pclk", "fffd0000.ssc", &ssc0_clk),
193 CLKDEV_CON_DEV_ID("pclk", "fffd4000.ssc", &ssc1_clk),
194 CLKDEV_CON_DEV_ID("pclk", "fffd8000.ssc", &ssc2_clk),
195 CLKDEV_CON_DEV_ID(NULL, "i2c-at91rm9200.0", &twi_clk),
196 /* fake hclk clock */
197 CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
198 CLKDEV_CON_ID("pioA", &pioA_clk),
199 CLKDEV_CON_ID("pioB", &pioB_clk),
200 CLKDEV_CON_ID("pioC", &pioC_clk),
201 CLKDEV_CON_ID("pioD", &pioD_clk),
202 /* usart lookup table for DT entries */
203 CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
204 CLKDEV_CON_DEV_ID("usart", "fffc0000.serial", &usart0_clk),
205 CLKDEV_CON_DEV_ID("usart", "fffc4000.serial", &usart1_clk),
206 CLKDEV_CON_DEV_ID("usart", "fffc8000.serial", &usart2_clk),
207 CLKDEV_CON_DEV_ID("usart", "fffcc000.serial", &usart3_clk),
208 /* tc lookup table for DT entries */
209 CLKDEV_CON_DEV_ID("t0_clk", "fffa0000.timer", &tc0_clk),
210 CLKDEV_CON_DEV_ID("t1_clk", "fffa0000.timer", &tc1_clk),
211 CLKDEV_CON_DEV_ID("t2_clk", "fffa0000.timer", &tc2_clk),
212 CLKDEV_CON_DEV_ID("t0_clk", "fffa4000.timer", &tc3_clk),
213 CLKDEV_CON_DEV_ID("t1_clk", "fffa4000.timer", &tc4_clk),
214 CLKDEV_CON_DEV_ID("t2_clk", "fffa4000.timer", &tc5_clk),
215 CLKDEV_CON_DEV_ID("mci_clk", "fffb4000.mmc", &mmc_clk),
216 CLKDEV_CON_DEV_ID("emac_clk", "fffbc000.ethernet", ðer_clk),
217 CLKDEV_CON_DEV_ID(NULL, "fffb8000.i2c", &twi_clk),
218 CLKDEV_CON_DEV_ID("hclk", "300000.ohci", &ohci_clk),
219 CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioA_clk),
220 CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioB_clk),
221 CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioC_clk),
222 CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioD_clk),
225 static struct clk_lookup usart_clocks_lookups[] = {
226 CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
227 CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
228 CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
229 CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
230 CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
234 * The four programmable clocks.
235 * You must configure pin multiplexing to bring these signals out.
237 static struct clk pck0 = {
239 .pmc_mask = AT91_PMC_PCK0,
240 .type = CLK_TYPE_PROGRAMMABLE,
243 static struct clk pck1 = {
245 .pmc_mask = AT91_PMC_PCK1,
246 .type = CLK_TYPE_PROGRAMMABLE,
249 static struct clk pck2 = {
251 .pmc_mask = AT91_PMC_PCK2,
252 .type = CLK_TYPE_PROGRAMMABLE,
255 static struct clk pck3 = {
257 .pmc_mask = AT91_PMC_PCK3,
258 .type = CLK_TYPE_PROGRAMMABLE,
262 static void __init at91rm9200_register_clocks(void)
266 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
267 clk_register(periph_clocks[i]);
269 clkdev_add_table(periph_clocks_lookups,
270 ARRAY_SIZE(periph_clocks_lookups));
271 clkdev_add_table(usart_clocks_lookups,
272 ARRAY_SIZE(usart_clocks_lookups));
280 /* --------------------------------------------------------------------
282 * -------------------------------------------------------------------- */
284 static struct at91_gpio_bank at91rm9200_gpio[] __initdata = {
286 .id = AT91RM9200_ID_PIOA,
287 .regbase = AT91RM9200_BASE_PIOA,
289 .id = AT91RM9200_ID_PIOB,
290 .regbase = AT91RM9200_BASE_PIOB,
292 .id = AT91RM9200_ID_PIOC,
293 .regbase = AT91RM9200_BASE_PIOC,
295 .id = AT91RM9200_ID_PIOD,
296 .regbase = AT91RM9200_BASE_PIOD,
300 static void at91rm9200_idle(void)
303 * Disable the processor clock. The processor will be automatically
304 * re-enabled by an interrupt or by a reset.
306 at91_pmc_write(AT91_PMC_SCDR, AT91_PMC_PCK);
309 static void at91rm9200_restart(enum reboot_mode reboot_mode, const char *cmd)
312 * Perform a hardware reset with the use of the Watchdog timer.
314 at91_st_write(AT91_ST_WDMR, AT91_ST_RSTEN | AT91_ST_EXTEN | 1);
315 at91_st_write(AT91_ST_CR, AT91_ST_WDRST);
318 /* --------------------------------------------------------------------
319 * AT91RM9200 processor initialization
320 * -------------------------------------------------------------------- */
321 static void __init at91rm9200_map_io(void)
323 /* Map peripherals */
324 at91_init_sram(0, AT91RM9200_SRAM_BASE, AT91RM9200_SRAM_SIZE);
327 static void __init at91rm9200_ioremap_registers(void)
329 at91rm9200_ioremap_st(AT91RM9200_BASE_ST);
330 at91_ioremap_ramc(0, AT91RM9200_BASE_MC, 256);
331 at91_pm_set_standby(at91rm9200_standby);
334 static void __init at91rm9200_initialize(void)
336 arm_pm_idle = at91rm9200_idle;
337 arm_pm_restart = at91rm9200_restart;
339 /* Initialize GPIO subsystem */
340 at91_gpio_init(at91rm9200_gpio,
341 cpu_is_at91rm9200_bga() ? AT91RM9200_BGA : AT91RM9200_PQFP);
345 /* --------------------------------------------------------------------
346 * Interrupt initialization
347 * -------------------------------------------------------------------- */
350 * The default interrupt priority levels (0 = lowest, 7 = highest).
352 static unsigned int at91rm9200_default_irq_priority[NR_AIC_IRQS] __initdata = {
353 7, /* Advanced Interrupt Controller (FIQ) */
354 7, /* System Peripherals */
355 1, /* Parallel IO Controller A */
356 1, /* Parallel IO Controller B */
357 1, /* Parallel IO Controller C */
358 1, /* Parallel IO Controller D */
363 0, /* Multimedia Card Interface */
364 2, /* USB Device Port */
365 6, /* Two-Wire Interface */
366 5, /* Serial Peripheral Interface */
367 4, /* Serial Synchronous Controller 0 */
368 4, /* Serial Synchronous Controller 1 */
369 4, /* Serial Synchronous Controller 2 */
370 0, /* Timer Counter 0 */
371 0, /* Timer Counter 1 */
372 0, /* Timer Counter 2 */
373 0, /* Timer Counter 3 */
374 0, /* Timer Counter 4 */
375 0, /* Timer Counter 5 */
376 2, /* USB Host port */
377 3, /* Ethernet MAC */
378 0, /* Advanced Interrupt Controller (IRQ0) */
379 0, /* Advanced Interrupt Controller (IRQ1) */
380 0, /* Advanced Interrupt Controller (IRQ2) */
381 0, /* Advanced Interrupt Controller (IRQ3) */
382 0, /* Advanced Interrupt Controller (IRQ4) */
383 0, /* Advanced Interrupt Controller (IRQ5) */
384 0 /* Advanced Interrupt Controller (IRQ6) */
387 AT91_SOC_START(at91rm9200)
388 .map_io = at91rm9200_map_io,
389 .default_irq_priority = at91rm9200_default_irq_priority,
390 .extern_irq = (1 << AT91RM9200_ID_IRQ0) | (1 << AT91RM9200_ID_IRQ1)
391 | (1 << AT91RM9200_ID_IRQ2) | (1 << AT91RM9200_ID_IRQ3)
392 | (1 << AT91RM9200_ID_IRQ4) | (1 << AT91RM9200_ID_IRQ5)
393 | (1 << AT91RM9200_ID_IRQ6),
394 .ioremap_registers = at91rm9200_ioremap_registers,
395 .register_clocks = at91rm9200_register_clocks,
396 .init = at91rm9200_initialize,