arch/arm/mach-at91/at91rm9200.c

   1 /*
   2  * arch/arm/mach-at91/at91rm9200.c
   3  *
   4  *  Copyright (C) 2005 SAN People
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  */
  12
  13 #include <linux/module.h>
  14 #include <linux/reboot.h>
  15
  16 #include <asm/irq.h>
  17 #include <asm/mach/arch.h>
  18 #include <asm/mach/map.h>
  19 #include <asm/system_misc.h>
  20 #include <mach/at91rm9200.h>
  21 #include <mach/at91_pmc.h>
  22 #include <mach/at91_st.h>
  23 #include <mach/cpu.h>
  24
  25 #include "at91_aic.h"
  26 #include "soc.h"
  27 #include "generic.h"
  28 #include "clock.h"
  29 #include "sam9_smc.h"
  30
  31 /* --------------------------------------------------------------------
  32  *  Clocks
  33  * -------------------------------------------------------------------- */
  34
  35 /*
  36  * The peripheral clocks.
  37  */
  38 static struct clk udc_clk = {
  39         .name           = "udc_clk",
  40         .pmc_mask       = 1 << AT91RM9200_ID_UDP,
  41         .type           = CLK_TYPE_PERIPHERAL,
  42 };
  43 static struct clk ohci_clk = {
  44         .name           = "ohci_clk",
  45         .pmc_mask       = 1 << AT91RM9200_ID_UHP,
  46         .type           = CLK_TYPE_PERIPHERAL,
  47 };
  48 static struct clk ether_clk = {
  49         .name           = "ether_clk",
  50         .pmc_mask       = 1 << AT91RM9200_ID_EMAC,
  51         .type           = CLK_TYPE_PERIPHERAL,
  52 };
  53 static struct clk mmc_clk = {
  54         .name           = "mci_clk",
  55         .pmc_mask       = 1 << AT91RM9200_ID_MCI,
  56         .type           = CLK_TYPE_PERIPHERAL,
  57 };
  58 static struct clk twi_clk = {
  59         .name           = "twi_clk",
  60         .pmc_mask       = 1 << AT91RM9200_ID_TWI,
  61         .type           = CLK_TYPE_PERIPHERAL,
  62 };
  63 static struct clk usart0_clk = {
  64         .name           = "usart0_clk",
  65         .pmc_mask       = 1 << AT91RM9200_ID_US0,
  66         .type           = CLK_TYPE_PERIPHERAL,
  67 };
  68 static struct clk usart1_clk = {
  69         .name           = "usart1_clk",
  70         .pmc_mask       = 1 << AT91RM9200_ID_US1,
  71         .type           = CLK_TYPE_PERIPHERAL,
  72 };
  73 static struct clk usart2_clk = {
  74         .name           = "usart2_clk",
  75         .pmc_mask       = 1 << AT91RM9200_ID_US2,
  76         .type           = CLK_TYPE_PERIPHERAL,
  77 };
  78 static struct clk usart3_clk = {
  79         .name           = "usart3_clk",
  80         .pmc_mask       = 1 << AT91RM9200_ID_US3,
  81         .type           = CLK_TYPE_PERIPHERAL,
  82 };
  83 static struct clk spi_clk = {
  84         .name           = "spi_clk",
  85         .pmc_mask       = 1 << AT91RM9200_ID_SPI,
  86         .type           = CLK_TYPE_PERIPHERAL,
  87 };
  88 static struct clk pioA_clk = {
  89         .name           = "pioA_clk",
  90         .pmc_mask       = 1 << AT91RM9200_ID_PIOA,
  91         .type           = CLK_TYPE_PERIPHERAL,
  92 };
  93 static struct clk pioB_clk = {
  94         .name           = "pioB_clk",
  95         .pmc_mask       = 1 << AT91RM9200_ID_PIOB,
  96         .type           = CLK_TYPE_PERIPHERAL,
  97 };
  98 static struct clk pioC_clk = {
  99         .name           = "pioC_clk",
 100         .pmc_mask       = 1 << AT91RM9200_ID_PIOC,
 101         .type           = CLK_TYPE_PERIPHERAL,
 102 };
 103 static struct clk pioD_clk = {
 104         .name           = "pioD_clk",
 105         .pmc_mask       = 1 << AT91RM9200_ID_PIOD,
 106         .type           = CLK_TYPE_PERIPHERAL,
 107 };
 108 static struct clk ssc0_clk = {
 109         .name           = "ssc0_clk",
 110         .pmc_mask       = 1 << AT91RM9200_ID_SSC0,
 111         .type           = CLK_TYPE_PERIPHERAL,
 112 };
 113 static struct clk ssc1_clk = {
 114         .name           = "ssc1_clk",
 115         .pmc_mask       = 1 << AT91RM9200_ID_SSC1,
 116         .type           = CLK_TYPE_PERIPHERAL,
 117 };
 118 static struct clk ssc2_clk = {
 119         .name           = "ssc2_clk",
 120         .pmc_mask       = 1 << AT91RM9200_ID_SSC2,
 121         .type           = CLK_TYPE_PERIPHERAL,
 122 };
 123 static struct clk tc0_clk = {
 124         .name           = "tc0_clk",
 125         .pmc_mask       = 1 << AT91RM9200_ID_TC0,
 126         .type           = CLK_TYPE_PERIPHERAL,
 127 };
 128 static struct clk tc1_clk = {
 129         .name           = "tc1_clk",
 130         .pmc_mask       = 1 << AT91RM9200_ID_TC1,
 131         .type           = CLK_TYPE_PERIPHERAL,
 132 };
 133 static struct clk tc2_clk = {
 134         .name           = "tc2_clk",
 135         .pmc_mask       = 1 << AT91RM9200_ID_TC2,
 136         .type           = CLK_TYPE_PERIPHERAL,
 137 };
 138 static struct clk tc3_clk = {
 139         .name           = "tc3_clk",
 140         .pmc_mask       = 1 << AT91RM9200_ID_TC3,
 141         .type           = CLK_TYPE_PERIPHERAL,
 142 };
 143 static struct clk tc4_clk = {
 144         .name           = "tc4_clk",
 145         .pmc_mask       = 1 << AT91RM9200_ID_TC4,
 146         .type           = CLK_TYPE_PERIPHERAL,
 147 };
 148 static struct clk tc5_clk = {
 149         .name           = "tc5_clk",
 150         .pmc_mask       = 1 << AT91RM9200_ID_TC5,
 151         .type           = CLK_TYPE_PERIPHERAL,
 152 };
 153
 154 static struct clk *periph_clocks[] __initdata = {
 155         &pioA_clk,
 156         &pioB_clk,
 157         &pioC_clk,
 158         &pioD_clk,
 159         &usart0_clk,
 160         &usart1_clk,
 161         &usart2_clk,
 162         &usart3_clk,
 163         &mmc_clk,
 164         &udc_clk,
 165         &twi_clk,
 166         &spi_clk,
 167         &ssc0_clk,
 168         &ssc1_clk,
 169         &ssc2_clk,
 170         &tc0_clk,
 171         &tc1_clk,
 172         &tc2_clk,
 173         &tc3_clk,
 174         &tc4_clk,
 175         &tc5_clk,
 176         &ohci_clk,
 177         &ether_clk,
 178         // irq0 .. irq6
 179 };
 180
 181 static struct clk_lookup periph_clocks_lookups[] = {
 182         CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
 183         CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
 184         CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
 185         CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tc3_clk),
 186         CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.1", &tc4_clk),
 187         CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.1", &tc5_clk),
 188         CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.0", &ssc0_clk),
 189         CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.1", &ssc1_clk),
 190         CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.2", &ssc2_clk),
 191         CLKDEV_CON_DEV_ID("pclk", "fffd0000.ssc", &ssc0_clk),
 192         CLKDEV_CON_DEV_ID("pclk", "fffd4000.ssc", &ssc1_clk),
 193         CLKDEV_CON_DEV_ID("pclk", "fffd8000.ssc", &ssc2_clk),
 194         CLKDEV_CON_DEV_ID(NULL, "i2c-at91rm9200.0", &twi_clk),
 195         /* fake hclk clock */
 196         CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
 197         CLKDEV_CON_ID("pioA", &pioA_clk),
 198         CLKDEV_CON_ID("pioB", &pioB_clk),
 199         CLKDEV_CON_ID("pioC", &pioC_clk),
 200         CLKDEV_CON_ID("pioD", &pioD_clk),
 201         /* usart lookup table for DT entries */
 202         CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
 203         CLKDEV_CON_DEV_ID("usart", "fffc0000.serial", &usart0_clk),
 204         CLKDEV_CON_DEV_ID("usart", "fffc4000.serial", &usart1_clk),
 205         CLKDEV_CON_DEV_ID("usart", "fffc8000.serial", &usart2_clk),
 206         CLKDEV_CON_DEV_ID("usart", "fffcc000.serial", &usart3_clk),
 207         /* tc lookup table for DT entries */
 208         CLKDEV_CON_DEV_ID("t0_clk", "fffa0000.timer", &tc0_clk),
 209         CLKDEV_CON_DEV_ID("t1_clk", "fffa0000.timer", &tc1_clk),
 210         CLKDEV_CON_DEV_ID("t2_clk", "fffa0000.timer", &tc2_clk),
 211         CLKDEV_CON_DEV_ID("t0_clk", "fffa4000.timer", &tc3_clk),
 212         CLKDEV_CON_DEV_ID("t1_clk", "fffa4000.timer", &tc4_clk),
 213         CLKDEV_CON_DEV_ID("t2_clk", "fffa4000.timer", &tc5_clk),
 214         CLKDEV_CON_DEV_ID("mci_clk", "fffb4000.mmc", &mmc_clk),
 215         CLKDEV_CON_DEV_ID("emac_clk", "fffbc000.ethernet", &ether_clk),
 216         CLKDEV_CON_DEV_ID(NULL, "fffb8000.i2c", &twi_clk),
 217         CLKDEV_CON_DEV_ID("hclk", "300000.ohci", &ohci_clk),
 218         CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioA_clk),
 219         CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioB_clk),
 220         CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioC_clk),
 221         CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioD_clk),
 222 };
 223
 224 static struct clk_lookup usart_clocks_lookups[] = {
 225         CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
 226         CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
 227         CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
 228         CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
 229         CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
 230 };
 231
 232 /*
 233  * The four programmable clocks.
 234  * You must configure pin multiplexing to bring these signals out.
 235  */
 236 static struct clk pck0 = {
 237         .name           = "pck0",
 238         .pmc_mask       = AT91_PMC_PCK0,
 239         .type           = CLK_TYPE_PROGRAMMABLE,
 240         .id             = 0,
 241 };
 242 static struct clk pck1 = {
 243         .name           = "pck1",
 244         .pmc_mask       = AT91_PMC_PCK1,
 245         .type           = CLK_TYPE_PROGRAMMABLE,
 246         .id             = 1,
 247 };
 248 static struct clk pck2 = {
 249         .name           = "pck2",
 250         .pmc_mask       = AT91_PMC_PCK2,
 251         .type           = CLK_TYPE_PROGRAMMABLE,
 252         .id             = 2,
 253 };
 254 static struct clk pck3 = {
 255         .name           = "pck3",
 256         .pmc_mask       = AT91_PMC_PCK3,
 257         .type           = CLK_TYPE_PROGRAMMABLE,
 258         .id             = 3,
 259 };
 260
 261 static void __init at91rm9200_register_clocks(void)
 262 {
 263         int i;
 264
 265         for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
 266                 clk_register(periph_clocks[i]);
 267
 268         clkdev_add_table(periph_clocks_lookups,
 269                          ARRAY_SIZE(periph_clocks_lookups));
 270         clkdev_add_table(usart_clocks_lookups,
 271                          ARRAY_SIZE(usart_clocks_lookups));
 272
 273         clk_register(&pck0);
 274         clk_register(&pck1);
 275         clk_register(&pck2);
 276         clk_register(&pck3);
 277 }
 278
 279 /* --------------------------------------------------------------------
 280  *  GPIO
 281  * -------------------------------------------------------------------- */
 282
 283 static struct at91_gpio_bank at91rm9200_gpio[] __initdata = {
 284         {
 285                 .id             = AT91RM9200_ID_PIOA,
 286                 .regbase        = AT91RM9200_BASE_PIOA,
 287         }, {
 288                 .id             = AT91RM9200_ID_PIOB,
 289                 .regbase        = AT91RM9200_BASE_PIOB,
 290         }, {
 291                 .id             = AT91RM9200_ID_PIOC,
 292                 .regbase        = AT91RM9200_BASE_PIOC,
 293         }, {
 294                 .id             = AT91RM9200_ID_PIOD,
 295                 .regbase        = AT91RM9200_BASE_PIOD,
 296         }
 297 };
 298
 299 static void at91rm9200_idle(void)
 300 {
 301         /*
 302          * Disable the processor clock.  The processor will be automatically
 303          * re-enabled by an interrupt or by a reset.
 304          */
 305         at91_pmc_write(AT91_PMC_SCDR, AT91_PMC_PCK);
 306 }
 307
 308 static void at91rm9200_restart(enum reboot_mode reboot_mode, const char *cmd)
 309 {
 310         /*
 311          * Perform a hardware reset with the use of the Watchdog timer.
 312          */
 313         at91_st_write(AT91_ST_WDMR, AT91_ST_RSTEN | AT91_ST_EXTEN | 1);
 314         at91_st_write(AT91_ST_CR, AT91_ST_WDRST);
 315 }
 316
 317 /* --------------------------------------------------------------------
 318  *  AT91RM9200 processor initialization
 319  * -------------------------------------------------------------------- */
 320 static void __init at91rm9200_map_io(void)
 321 {
 322         /* Map peripherals */
 323         at91_init_sram(0, AT91RM9200_SRAM_BASE, AT91RM9200_SRAM_SIZE);
 324 }
 325
 326 static void __init at91rm9200_ioremap_registers(void)
 327 {
 328         at91rm9200_ioremap_st(AT91RM9200_BASE_ST);
 329         at91_ioremap_ramc(0, AT91RM9200_BASE_MC, 256);
 330 }
 331
 332 static void __init at91rm9200_initialize(void)
 333 {
 334         arm_pm_idle = at91rm9200_idle;
 335         arm_pm_restart = at91rm9200_restart;
 336
 337         /* Initialize GPIO subsystem */
 338         at91_gpio_init(at91rm9200_gpio,
 339                 cpu_is_at91rm9200_bga() ? AT91RM9200_BGA : AT91RM9200_PQFP);
 340 }
 341
 342
 343 /* --------------------------------------------------------------------
 344  *  Interrupt initialization
 345  * -------------------------------------------------------------------- */
 346
 347 /*
 348  * The default interrupt priority levels (0 = lowest, 7 = highest).
 349  */
 350 static unsigned int at91rm9200_default_irq_priority[NR_AIC_IRQS] __initdata = {
 351         7,      /* Advanced Interrupt Controller (FIQ) */
 352         7,      /* System Peripherals */
 353         1,      /* Parallel IO Controller A */
 354         1,      /* Parallel IO Controller B */
 355         1,      /* Parallel IO Controller C */
 356         1,      /* Parallel IO Controller D */
 357         5,      /* USART 0 */
 358         5,      /* USART 1 */
 359         5,      /* USART 2 */
 360         5,      /* USART 3 */
 361         0,      /* Multimedia Card Interface */
 362         2,      /* USB Device Port */
 363         6,      /* Two-Wire Interface */
 364         5,      /* Serial Peripheral Interface */
 365         4,      /* Serial Synchronous Controller 0 */
 366         4,      /* Serial Synchronous Controller 1 */
 367         4,      /* Serial Synchronous Controller 2 */
 368         0,      /* Timer Counter 0 */
 369         0,      /* Timer Counter 1 */
 370         0,      /* Timer Counter 2 */
 371         0,      /* Timer Counter 3 */
 372         0,      /* Timer Counter 4 */
 373         0,      /* Timer Counter 5 */
 374         2,      /* USB Host port */
 375         3,      /* Ethernet MAC */
 376         0,      /* Advanced Interrupt Controller (IRQ0) */
 377         0,      /* Advanced Interrupt Controller (IRQ1) */
 378         0,      /* Advanced Interrupt Controller (IRQ2) */
 379         0,      /* Advanced Interrupt Controller (IRQ3) */
 380         0,      /* Advanced Interrupt Controller (IRQ4) */
 381         0,      /* Advanced Interrupt Controller (IRQ5) */
 382         0       /* Advanced Interrupt Controller (IRQ6) */
 383 };
 384
 385 AT91_SOC_START(at91rm9200)
 386         .map_io = at91rm9200_map_io,
 387         .default_irq_priority = at91rm9200_default_irq_priority,
 388         .extern_irq = (1 << AT91RM9200_ID_IRQ0) | (1 << AT91RM9200_ID_IRQ1)
 389                     | (1 << AT91RM9200_ID_IRQ2) | (1 << AT91RM9200_ID_IRQ3)
 390                     | (1 << AT91RM9200_ID_IRQ4) | (1 << AT91RM9200_ID_IRQ5)
 391                     | (1 << AT91RM9200_ID_IRQ6),
 392         .ioremap_registers = at91rm9200_ioremap_registers,
 393         .register_clocks = at91rm9200_register_clocks,
 394         .init = at91rm9200_initialize,
 395 AT91_SOC_END