2 * arch/arm/mach-at91/at91rm9200_devices.c
4 * Copyright (C) 2005 Thibaut VARENE <varenet@parisc-linux.org>
5 * Copyright (C) 2005 David Brownell
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
13 #include <asm/mach/arch.h>
14 #include <asm/mach/map.h>
16 #include <linux/platform_device.h>
18 #include <asm/arch/board.h>
19 #include <asm/arch/gpio.h>
20 #include <asm/arch/at91rm9200.h>
21 #include <asm/arch/at91rm9200_mc.h>
25 #define SZ_512 0x00000200
26 #define SZ_256 0x00000100
27 #define SZ_16 0x00000010
29 /* --------------------------------------------------------------------
31 * -------------------------------------------------------------------- */
33 #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
34 static u64 ohci_dmamask = 0xffffffffUL;
35 static struct at91_usbh_data usbh_data;
37 static struct resource usbh_resources[] = {
39 .start = AT91RM9200_UHP_BASE,
40 .end = AT91RM9200_UHP_BASE + SZ_1M - 1,
41 .flags = IORESOURCE_MEM,
44 .start = AT91RM9200_ID_UHP,
45 .end = AT91RM9200_ID_UHP,
46 .flags = IORESOURCE_IRQ,
50 static struct platform_device at91rm9200_usbh_device = {
54 .dma_mask = &ohci_dmamask,
55 .coherent_dma_mask = 0xffffffff,
56 .platform_data = &usbh_data,
58 .resource = usbh_resources,
59 .num_resources = ARRAY_SIZE(usbh_resources),
62 void __init at91_add_device_usbh(struct at91_usbh_data *data)
68 platform_device_register(&at91rm9200_usbh_device);
71 void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
75 /* --------------------------------------------------------------------
77 * -------------------------------------------------------------------- */
79 #ifdef CONFIG_USB_GADGET_AT91
80 static struct at91_udc_data udc_data;
82 static struct resource udc_resources[] = {
84 .start = AT91RM9200_BASE_UDP,
85 .end = AT91RM9200_BASE_UDP + SZ_16K - 1,
86 .flags = IORESOURCE_MEM,
89 .start = AT91RM9200_ID_UDP,
90 .end = AT91RM9200_ID_UDP,
91 .flags = IORESOURCE_IRQ,
95 static struct platform_device at91rm9200_udc_device = {
99 .platform_data = &udc_data,
101 .resource = udc_resources,
102 .num_resources = ARRAY_SIZE(udc_resources),
105 void __init at91_add_device_udc(struct at91_udc_data *data)
110 if (data->vbus_pin) {
111 at91_set_gpio_input(data->vbus_pin, 0);
112 at91_set_deglitch(data->vbus_pin, 1);
114 if (data->pullup_pin)
115 at91_set_gpio_output(data->pullup_pin, 0);
118 platform_device_register(&at91rm9200_udc_device);
121 void __init at91_add_device_udc(struct at91_udc_data *data) {}
125 /* --------------------------------------------------------------------
127 * -------------------------------------------------------------------- */
129 #if defined(CONFIG_ARM_AT91_ETHER) || defined(CONFIG_ARM_AT91_ETHER_MODULE)
130 static u64 eth_dmamask = 0xffffffffUL;
131 static struct at91_eth_data eth_data;
133 static struct resource eth_resources[] = {
135 .start = AT91_VA_BASE_EMAC,
136 .end = AT91_VA_BASE_EMAC + SZ_16K - 1,
137 .flags = IORESOURCE_MEM,
140 .start = AT91RM9200_ID_EMAC,
141 .end = AT91RM9200_ID_EMAC,
142 .flags = IORESOURCE_IRQ,
146 static struct platform_device at91rm9200_eth_device = {
147 .name = "at91_ether",
150 .dma_mask = ð_dmamask,
151 .coherent_dma_mask = 0xffffffff,
152 .platform_data = ð_data,
154 .resource = eth_resources,
155 .num_resources = ARRAY_SIZE(eth_resources),
158 void __init at91_add_device_eth(struct at91_eth_data *data)
163 if (data->phy_irq_pin) {
164 at91_set_gpio_input(data->phy_irq_pin, 0);
165 at91_set_deglitch(data->phy_irq_pin, 1);
168 /* Pins used for MII and RMII */
169 at91_set_A_periph(AT91_PIN_PA16, 0); /* EMDIO */
170 at91_set_A_periph(AT91_PIN_PA15, 0); /* EMDC */
171 at91_set_A_periph(AT91_PIN_PA14, 0); /* ERXER */
172 at91_set_A_periph(AT91_PIN_PA13, 0); /* ERX1 */
173 at91_set_A_periph(AT91_PIN_PA12, 0); /* ERX0 */
174 at91_set_A_periph(AT91_PIN_PA11, 0); /* ECRS_ECRSDV */
175 at91_set_A_periph(AT91_PIN_PA10, 0); /* ETX1 */
176 at91_set_A_periph(AT91_PIN_PA9, 0); /* ETX0 */
177 at91_set_A_periph(AT91_PIN_PA8, 0); /* ETXEN */
178 at91_set_A_periph(AT91_PIN_PA7, 0); /* ETXCK_EREFCK */
180 if (!data->is_rmii) {
181 at91_set_B_periph(AT91_PIN_PB19, 0); /* ERXCK */
182 at91_set_B_periph(AT91_PIN_PB18, 0); /* ECOL */
183 at91_set_B_periph(AT91_PIN_PB17, 0); /* ERXDV */
184 at91_set_B_periph(AT91_PIN_PB16, 0); /* ERX3 */
185 at91_set_B_periph(AT91_PIN_PB15, 0); /* ERX2 */
186 at91_set_B_periph(AT91_PIN_PB14, 0); /* ETXER */
187 at91_set_B_periph(AT91_PIN_PB13, 0); /* ETX3 */
188 at91_set_B_periph(AT91_PIN_PB12, 0); /* ETX2 */
192 platform_device_register(&at91rm9200_eth_device);
195 void __init at91_add_device_eth(struct at91_eth_data *data) {}
199 /* --------------------------------------------------------------------
200 * Compact Flash / PCMCIA
201 * -------------------------------------------------------------------- */
203 #if defined(CONFIG_AT91_CF) || defined(CONFIG_AT91_CF_MODULE)
204 static struct at91_cf_data cf_data;
206 #define CF_BASE AT91_CHIPSELECT_4
208 static struct resource cf_resources[] = {
211 /* ties up CS4, CS5 and CS6 */
212 .end = CF_BASE + (0x30000000 - 1),
213 .flags = IORESOURCE_MEM | IORESOURCE_MEM_8AND16BIT,
217 static struct platform_device at91rm9200_cf_device = {
221 .platform_data = &cf_data,
223 .resource = cf_resources,
224 .num_resources = ARRAY_SIZE(cf_resources),
227 void __init at91_add_device_cf(struct at91_cf_data *data)
234 data->chipselect = 4; /* can only use EBI ChipSelect 4 */
236 /* CF takes over CS4, CS5, CS6 */
237 csa = at91_sys_read(AT91_EBI_CSA);
238 at91_sys_write(AT91_EBI_CSA, csa | AT91_EBI_CS4A_SMC_COMPACTFLASH);
241 * Static memory controller timing adjustments.
242 * REVISIT: these timings are in terms of MCK cycles, so
243 * when MCK changes (cpufreq etc) so must these values...
245 at91_sys_write(AT91_SMC_CSR(4),
250 | AT91_SMC_NWS_(32) /* wait states */
251 | AT91_SMC_RWSETUP_(6) /* setup time */
252 | AT91_SMC_RWHOLD_(4) /* hold time */
257 at91_set_gpio_input(data->irq_pin, 1);
258 at91_set_deglitch(data->irq_pin, 1);
260 at91_set_gpio_input(data->det_pin, 1);
261 at91_set_deglitch(data->det_pin, 1);
263 /* outputs, initially off */
265 at91_set_gpio_output(data->vcc_pin, 0);
266 at91_set_gpio_output(data->rst_pin, 0);
268 /* force poweron defaults for these pins ... */
269 at91_set_A_periph(AT91_PIN_PC9, 0); /* A25/CFRNW */
270 at91_set_A_periph(AT91_PIN_PC10, 0); /* NCS4/CFCS */
271 at91_set_A_periph(AT91_PIN_PC11, 0); /* NCS5/CFCE1 */
272 at91_set_A_periph(AT91_PIN_PC12, 0); /* NCS6/CFCE2 */
274 /* nWAIT is _not_ a default setting */
275 at91_set_A_periph(AT91_PIN_PC6, 1); /* nWAIT */
278 platform_device_register(&at91rm9200_cf_device);
281 void __init at91_add_device_cf(struct at91_cf_data *data) {}
285 /* --------------------------------------------------------------------
287 * -------------------------------------------------------------------- */
289 #if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE)
290 static u64 mmc_dmamask = 0xffffffffUL;
291 static struct at91_mmc_data mmc_data;
293 static struct resource mmc_resources[] = {
295 .start = AT91RM9200_BASE_MCI,
296 .end = AT91RM9200_BASE_MCI + SZ_16K - 1,
297 .flags = IORESOURCE_MEM,
300 .start = AT91RM9200_ID_MCI,
301 .end = AT91RM9200_ID_MCI,
302 .flags = IORESOURCE_IRQ,
306 static struct platform_device at91rm9200_mmc_device = {
310 .dma_mask = &mmc_dmamask,
311 .coherent_dma_mask = 0xffffffff,
312 .platform_data = &mmc_data,
314 .resource = mmc_resources,
315 .num_resources = ARRAY_SIZE(mmc_resources),
318 void __init at91_add_device_mmc(struct at91_mmc_data *data)
325 at91_set_gpio_input(data->det_pin, 1);
326 at91_set_deglitch(data->det_pin, 1);
329 at91_set_gpio_input(data->wp_pin, 1);
331 at91_set_gpio_output(data->vcc_pin, 0);
334 at91_set_A_periph(AT91_PIN_PA27, 0);
338 at91_set_B_periph(AT91_PIN_PA8, 1);
340 /* DAT0, maybe DAT1..DAT3 */
341 at91_set_B_periph(AT91_PIN_PA9, 1);
343 at91_set_B_periph(AT91_PIN_PA10, 1);
344 at91_set_B_periph(AT91_PIN_PA11, 1);
345 at91_set_B_periph(AT91_PIN_PA12, 1);
349 at91_set_A_periph(AT91_PIN_PA28, 1);
351 /* DAT0, maybe DAT1..DAT3 */
352 at91_set_A_periph(AT91_PIN_PA29, 1);
354 at91_set_B_periph(AT91_PIN_PB3, 1);
355 at91_set_B_periph(AT91_PIN_PB4, 1);
356 at91_set_B_periph(AT91_PIN_PB5, 1);
361 platform_device_register(&at91rm9200_mmc_device);
364 void __init at91_add_device_mmc(struct at91_mmc_data *data) {}
368 /* --------------------------------------------------------------------
370 * -------------------------------------------------------------------- */
372 #if defined(CONFIG_MTD_NAND_AT91) || defined(CONFIG_MTD_NAND_AT91_MODULE)
373 static struct at91_nand_data nand_data;
375 #define NAND_BASE AT91_CHIPSELECT_3
377 static struct resource nand_resources[] = {
380 .end = NAND_BASE + SZ_8M - 1,
381 .flags = IORESOURCE_MEM,
385 static struct platform_device at91rm9200_nand_device = {
389 .platform_data = &nand_data,
391 .resource = nand_resources,
392 .num_resources = ARRAY_SIZE(nand_resources),
395 void __init at91_add_device_nand(struct at91_nand_data *data)
402 /* enable the address range of CS3 */
403 csa = at91_sys_read(AT91_EBI_CSA);
404 at91_sys_write(AT91_EBI_CSA, csa | AT91_EBI_CS3A_SMC_SMARTMEDIA);
406 /* set the bus interface characteristics */
407 at91_sys_write(AT91_SMC_CSR(3), AT91_SMC_ACSS_STD | AT91_SMC_DBW_8 | AT91_SMC_WSEN
410 | AT91_SMC_RWSETUP_(0) /* tDS Data Set up Time 30 - ns */
411 | AT91_SMC_RWHOLD_(1) /* tDH Data Hold Time 20 - ns */
415 if (data->enable_pin)
416 at91_set_gpio_output(data->enable_pin, 1);
420 at91_set_gpio_input(data->rdy_pin, 1);
422 /* card detect pin */
424 at91_set_gpio_input(data->det_pin, 1);
426 at91_set_A_periph(AT91_PIN_PC1, 0); /* SMOE */
427 at91_set_A_periph(AT91_PIN_PC3, 0); /* SMWE */
430 platform_device_register(&at91rm9200_nand_device);
433 void __init at91_add_device_nand(struct at91_nand_data *data) {}
437 /* --------------------------------------------------------------------
439 * -------------------------------------------------------------------- */
441 #if defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
443 static struct resource twi_resources[] = {
445 .start = AT91RM9200_BASE_TWI,
446 .end = AT91RM9200_BASE_TWI + SZ_16K - 1,
447 .flags = IORESOURCE_MEM,
450 .start = AT91RM9200_ID_TWI,
451 .end = AT91RM9200_ID_TWI,
452 .flags = IORESOURCE_IRQ,
456 static struct platform_device at91rm9200_twi_device = {
459 .resource = twi_resources,
460 .num_resources = ARRAY_SIZE(twi_resources),
463 void __init at91_add_device_i2c(void)
465 /* pins used for TWI interface */
466 at91_set_A_periph(AT91_PIN_PA25, 0); /* TWD */
467 at91_set_multi_drive(AT91_PIN_PA25, 1);
469 at91_set_A_periph(AT91_PIN_PA26, 0); /* TWCK */
470 at91_set_multi_drive(AT91_PIN_PA26, 1);
472 platform_device_register(&at91rm9200_twi_device);
475 void __init at91_add_device_i2c(void) {}
479 /* --------------------------------------------------------------------
481 * -------------------------------------------------------------------- */
483 #if defined(CONFIG_SPI_AT91) || defined(CONFIG_SPI_AT91_MODULE) || defined(CONFIG_AT91_SPI) || defined(CONFIG_AT91_SPI_MODULE)
484 static u64 spi_dmamask = 0xffffffffUL;
486 static struct resource spi_resources[] = {
488 .start = AT91RM9200_BASE_SPI,
489 .end = AT91RM9200_BASE_SPI + SZ_16K - 1,
490 .flags = IORESOURCE_MEM,
493 .start = AT91RM9200_ID_SPI,
494 .end = AT91RM9200_ID_SPI,
495 .flags = IORESOURCE_IRQ,
499 static struct platform_device at91rm9200_spi_device = {
503 .dma_mask = &spi_dmamask,
504 .coherent_dma_mask = 0xffffffff,
506 .resource = spi_resources,
507 .num_resources = ARRAY_SIZE(spi_resources),
510 static const unsigned spi_standard_cs[4] = { AT91_PIN_PA3, AT91_PIN_PA4, AT91_PIN_PA5, AT91_PIN_PA6 };
512 void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
515 unsigned long cs_pin;
517 at91_set_A_periph(AT91_PIN_PA0, 0); /* MISO */
518 at91_set_A_periph(AT91_PIN_PA1, 0); /* MOSI */
519 at91_set_A_periph(AT91_PIN_PA2, 0); /* SPCK */
521 /* Enable SPI chip-selects */
522 for (i = 0; i < nr_devices; i++) {
523 if (devices[i].controller_data)
524 cs_pin = (unsigned long) devices[i].controller_data;
526 cs_pin = spi_standard_cs[devices[i].chip_select];
528 #ifdef CONFIG_SPI_AT91_MANUAL_CS
529 at91_set_gpio_output(cs_pin, 1);
531 at91_set_A_periph(cs_pin, 0);
534 /* pass chip-select pin to driver */
535 devices[i].controller_data = (void *) cs_pin;
538 spi_register_board_info(devices, nr_devices);
539 at91_clock_associate("spi_clk", &at91rm9200_spi_device.dev, "spi");
540 platform_device_register(&at91rm9200_spi_device);
543 void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
547 /* --------------------------------------------------------------------
549 * -------------------------------------------------------------------- */
551 #if defined(CONFIG_RTC_DRV_AT91RM9200) || defined(CONFIG_RTC_DRV_AT91RM9200_MODULE)
552 static struct platform_device at91rm9200_rtc_device = {
558 static void __init at91_add_device_rtc(void)
560 platform_device_register(&at91rm9200_rtc_device);
563 static void __init at91_add_device_rtc(void) {}
567 /* --------------------------------------------------------------------
569 * -------------------------------------------------------------------- */
571 #if defined(CONFIG_AT91RM9200_WATCHDOG) || defined(CONFIG_AT91RM9200_WATCHDOG_MODULE)
572 static struct platform_device at91rm9200_wdt_device = {
578 static void __init at91_add_device_watchdog(void)
580 platform_device_register(&at91rm9200_wdt_device);
583 static void __init at91_add_device_watchdog(void) {}
587 /* --------------------------------------------------------------------
589 * -------------------------------------------------------------------- */
591 #if defined(CONFIG_LEDS)
595 void __init at91_init_leds(u8 cpu_led, u8 timer_led)
597 at91_leds_cpu = cpu_led;
598 at91_leds_timer = timer_led;
601 void __init at91_init_leds(u8 cpu_led, u8 timer_led) {}
605 /* --------------------------------------------------------------------
607 * -------------------------------------------------------------------- */
609 #if defined(CONFIG_SERIAL_ATMEL)
610 static struct resource dbgu_resources[] = {
612 .start = AT91_VA_BASE_SYS + AT91_DBGU,
613 .end = AT91_VA_BASE_SYS + AT91_DBGU + SZ_512 - 1,
614 .flags = IORESOURCE_MEM,
617 .start = AT91_ID_SYS,
619 .flags = IORESOURCE_IRQ,
623 static struct atmel_uart_data dbgu_data = {
625 .use_dma_rx = 0, /* DBGU not capable of receive DMA */
626 .regs = (void __iomem *)(AT91_VA_BASE_SYS + AT91_DBGU),
629 static struct platform_device at91rm9200_dbgu_device = {
630 .name = "atmel_usart",
633 .platform_data = &dbgu_data,
634 .coherent_dma_mask = 0xffffffff,
636 .resource = dbgu_resources,
637 .num_resources = ARRAY_SIZE(dbgu_resources),
640 static inline void configure_dbgu_pins(void)
642 at91_set_A_periph(AT91_PIN_PA30, 0); /* DRXD */
643 at91_set_A_periph(AT91_PIN_PA31, 1); /* DTXD */
646 static struct resource uart0_resources[] = {
648 .start = AT91RM9200_BASE_US0,
649 .end = AT91RM9200_BASE_US0 + SZ_16K - 1,
650 .flags = IORESOURCE_MEM,
653 .start = AT91RM9200_ID_US0,
654 .end = AT91RM9200_ID_US0,
655 .flags = IORESOURCE_IRQ,
659 static struct atmel_uart_data uart0_data = {
664 static struct platform_device at91rm9200_uart0_device = {
665 .name = "atmel_usart",
668 .platform_data = &uart0_data,
669 .coherent_dma_mask = 0xffffffff,
671 .resource = uart0_resources,
672 .num_resources = ARRAY_SIZE(uart0_resources),
675 static inline void configure_usart0_pins(void)
677 at91_set_A_periph(AT91_PIN_PA17, 1); /* TXD0 */
678 at91_set_A_periph(AT91_PIN_PA18, 0); /* RXD0 */
679 at91_set_A_periph(AT91_PIN_PA20, 0); /* CTS0 */
682 * AT91RM9200 Errata #39 - RTS0 is not internally connected to PA21.
683 * We need to drive the pin manually. Default is off (RTS is active low).
685 at91_set_gpio_output(AT91_PIN_PA21, 1);
688 static struct resource uart1_resources[] = {
690 .start = AT91RM9200_BASE_US1,
691 .end = AT91RM9200_BASE_US1 + SZ_16K - 1,
692 .flags = IORESOURCE_MEM,
695 .start = AT91RM9200_ID_US1,
696 .end = AT91RM9200_ID_US1,
697 .flags = IORESOURCE_IRQ,
701 static struct atmel_uart_data uart1_data = {
706 static struct platform_device at91rm9200_uart1_device = {
707 .name = "atmel_usart",
710 .platform_data = &uart1_data,
711 .coherent_dma_mask = 0xffffffff,
713 .resource = uart1_resources,
714 .num_resources = ARRAY_SIZE(uart1_resources),
717 static inline void configure_usart1_pins(void)
719 at91_set_A_periph(AT91_PIN_PB18, 0); /* RI1 */
720 at91_set_A_periph(AT91_PIN_PB19, 0); /* DTR1 */
721 at91_set_A_periph(AT91_PIN_PB20, 1); /* TXD1 */
722 at91_set_A_periph(AT91_PIN_PB21, 0); /* RXD1 */
723 at91_set_A_periph(AT91_PIN_PB23, 0); /* DCD1 */
724 at91_set_A_periph(AT91_PIN_PB24, 0); /* CTS1 */
725 at91_set_A_periph(AT91_PIN_PB25, 0); /* DSR1 */
726 at91_set_A_periph(AT91_PIN_PB26, 0); /* RTS1 */
729 static struct resource uart2_resources[] = {
731 .start = AT91RM9200_BASE_US2,
732 .end = AT91RM9200_BASE_US2 + SZ_16K - 1,
733 .flags = IORESOURCE_MEM,
736 .start = AT91RM9200_ID_US2,
737 .end = AT91RM9200_ID_US2,
738 .flags = IORESOURCE_IRQ,
742 static struct atmel_uart_data uart2_data = {
747 static struct platform_device at91rm9200_uart2_device = {
748 .name = "atmel_usart",
751 .platform_data = &uart2_data,
752 .coherent_dma_mask = 0xffffffff,
754 .resource = uart2_resources,
755 .num_resources = ARRAY_SIZE(uart2_resources),
758 static inline void configure_usart2_pins(void)
760 at91_set_A_periph(AT91_PIN_PA22, 0); /* RXD2 */
761 at91_set_A_periph(AT91_PIN_PA23, 1); /* TXD2 */
764 static struct resource uart3_resources[] = {
766 .start = AT91RM9200_BASE_US3,
767 .end = AT91RM9200_BASE_US3 + SZ_16K - 1,
768 .flags = IORESOURCE_MEM,
771 .start = AT91RM9200_ID_US3,
772 .end = AT91RM9200_ID_US3,
773 .flags = IORESOURCE_IRQ,
777 static struct atmel_uart_data uart3_data = {
782 static struct platform_device at91rm9200_uart3_device = {
783 .name = "atmel_usart",
786 .platform_data = &uart3_data,
787 .coherent_dma_mask = 0xffffffff,
789 .resource = uart3_resources,
790 .num_resources = ARRAY_SIZE(uart3_resources),
793 static inline void configure_usart3_pins(void)
795 at91_set_B_periph(AT91_PIN_PA5, 1); /* TXD3 */
796 at91_set_B_periph(AT91_PIN_PA6, 0); /* RXD3 */
799 struct platform_device *at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
800 struct platform_device *atmel_default_console_device; /* the serial console device */
802 void __init at91_init_serial(struct at91_uart_config *config)
806 /* Fill in list of supported UARTs */
807 for (i = 0; i < config->nr_tty; i++) {
808 switch (config->tty_map[i]) {
810 configure_usart0_pins();
811 at91_uarts[i] = &at91rm9200_uart0_device;
812 at91_clock_associate("usart0_clk", &at91rm9200_uart0_device.dev, "usart");
815 configure_usart1_pins();
816 at91_uarts[i] = &at91rm9200_uart1_device;
817 at91_clock_associate("usart1_clk", &at91rm9200_uart1_device.dev, "usart");
820 configure_usart2_pins();
821 at91_uarts[i] = &at91rm9200_uart2_device;
822 at91_clock_associate("usart2_clk", &at91rm9200_uart2_device.dev, "usart");
825 configure_usart3_pins();
826 at91_uarts[i] = &at91rm9200_uart3_device;
827 at91_clock_associate("usart3_clk", &at91rm9200_uart3_device.dev, "usart");
830 configure_dbgu_pins();
831 at91_uarts[i] = &at91rm9200_dbgu_device;
832 at91_clock_associate("mck", &at91rm9200_dbgu_device.dev, "usart");
837 at91_uarts[i]->id = i; /* update ID number to mapped ID */
840 /* Set serial console device */
841 if (config->console_tty < ATMEL_MAX_UART)
842 atmel_default_console_device = at91_uarts[config->console_tty];
843 if (!atmel_default_console_device)
844 printk(KERN_INFO "AT91: No default serial console defined.\n");
847 void __init at91_add_device_serial(void)
851 for (i = 0; i < ATMEL_MAX_UART; i++) {
853 platform_device_register(at91_uarts[i]);
857 void __init at91_init_serial(struct at91_uart_config *config) {}
858 void __init at91_add_device_serial(void) {}
862 /* -------------------------------------------------------------------- */
865 * These devices are always present and don't need any board-specific
868 static int __init at91_add_standard_devices(void)
870 at91_add_device_rtc();
871 at91_add_device_watchdog();
875 arch_initcall(at91_add_standard_devices);