2 * arch/arm/mach-at91/at91sam9260.c
4 * Copyright (C) 2006 SAN People
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
13 #include <linux/module.h>
14 #include <linux/clk/at91_pmc.h>
16 #include <asm/proc-fns.h>
18 #include <asm/mach/arch.h>
19 #include <asm/mach/map.h>
20 #include <asm/system_misc.h>
22 #include <mach/at91_dbgu.h>
23 #include <mach/at91sam9260.h>
24 #include <mach/hardware.h>
27 #include "at91_rstc.h"
33 #if defined(CONFIG_OLD_CLK_AT91)
35 /* --------------------------------------------------------------------
37 * -------------------------------------------------------------------- */
40 * The peripheral clocks.
42 static struct clk pioA_clk = {
44 .pmc_mask = 1 << AT91SAM9260_ID_PIOA,
45 .type = CLK_TYPE_PERIPHERAL,
47 static struct clk pioB_clk = {
49 .pmc_mask = 1 << AT91SAM9260_ID_PIOB,
50 .type = CLK_TYPE_PERIPHERAL,
52 static struct clk pioC_clk = {
54 .pmc_mask = 1 << AT91SAM9260_ID_PIOC,
55 .type = CLK_TYPE_PERIPHERAL,
57 static struct clk adc_clk = {
59 .pmc_mask = 1 << AT91SAM9260_ID_ADC,
60 .type = CLK_TYPE_PERIPHERAL,
63 static struct clk adc_op_clk = {
65 .type = CLK_TYPE_PERIPHERAL,
69 static struct clk usart0_clk = {
71 .pmc_mask = 1 << AT91SAM9260_ID_US0,
72 .type = CLK_TYPE_PERIPHERAL,
74 static struct clk usart1_clk = {
76 .pmc_mask = 1 << AT91SAM9260_ID_US1,
77 .type = CLK_TYPE_PERIPHERAL,
79 static struct clk usart2_clk = {
81 .pmc_mask = 1 << AT91SAM9260_ID_US2,
82 .type = CLK_TYPE_PERIPHERAL,
84 static struct clk mmc_clk = {
86 .pmc_mask = 1 << AT91SAM9260_ID_MCI,
87 .type = CLK_TYPE_PERIPHERAL,
89 static struct clk udc_clk = {
91 .pmc_mask = 1 << AT91SAM9260_ID_UDP,
92 .type = CLK_TYPE_PERIPHERAL,
94 static struct clk twi_clk = {
96 .pmc_mask = 1 << AT91SAM9260_ID_TWI,
97 .type = CLK_TYPE_PERIPHERAL,
99 static struct clk spi0_clk = {
101 .pmc_mask = 1 << AT91SAM9260_ID_SPI0,
102 .type = CLK_TYPE_PERIPHERAL,
104 static struct clk spi1_clk = {
106 .pmc_mask = 1 << AT91SAM9260_ID_SPI1,
107 .type = CLK_TYPE_PERIPHERAL,
109 static struct clk ssc_clk = {
111 .pmc_mask = 1 << AT91SAM9260_ID_SSC,
112 .type = CLK_TYPE_PERIPHERAL,
114 static struct clk tc0_clk = {
116 .pmc_mask = 1 << AT91SAM9260_ID_TC0,
117 .type = CLK_TYPE_PERIPHERAL,
119 static struct clk tc1_clk = {
121 .pmc_mask = 1 << AT91SAM9260_ID_TC1,
122 .type = CLK_TYPE_PERIPHERAL,
124 static struct clk tc2_clk = {
126 .pmc_mask = 1 << AT91SAM9260_ID_TC2,
127 .type = CLK_TYPE_PERIPHERAL,
129 static struct clk ohci_clk = {
131 .pmc_mask = 1 << AT91SAM9260_ID_UHP,
132 .type = CLK_TYPE_PERIPHERAL,
134 static struct clk macb_clk = {
136 .pmc_mask = 1 << AT91SAM9260_ID_EMAC,
137 .type = CLK_TYPE_PERIPHERAL,
139 static struct clk isi_clk = {
141 .pmc_mask = 1 << AT91SAM9260_ID_ISI,
142 .type = CLK_TYPE_PERIPHERAL,
144 static struct clk usart3_clk = {
145 .name = "usart3_clk",
146 .pmc_mask = 1 << AT91SAM9260_ID_US3,
147 .type = CLK_TYPE_PERIPHERAL,
149 static struct clk usart4_clk = {
150 .name = "usart4_clk",
151 .pmc_mask = 1 << AT91SAM9260_ID_US4,
152 .type = CLK_TYPE_PERIPHERAL,
154 static struct clk usart5_clk = {
155 .name = "usart5_clk",
156 .pmc_mask = 1 << AT91SAM9260_ID_US5,
157 .type = CLK_TYPE_PERIPHERAL,
159 static struct clk tc3_clk = {
161 .pmc_mask = 1 << AT91SAM9260_ID_TC3,
162 .type = CLK_TYPE_PERIPHERAL,
164 static struct clk tc4_clk = {
166 .pmc_mask = 1 << AT91SAM9260_ID_TC4,
167 .type = CLK_TYPE_PERIPHERAL,
169 static struct clk tc5_clk = {
171 .pmc_mask = 1 << AT91SAM9260_ID_TC5,
172 .type = CLK_TYPE_PERIPHERAL,
175 static struct clk *periph_clocks[] __initdata = {
205 static struct clk_lookup periph_clocks_lookups[] = {
206 /* One additional fake clock for macb_hclk */
207 CLKDEV_CON_ID("hclk", &macb_clk),
208 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
209 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
210 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
211 CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
212 CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
213 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tc3_clk),
214 CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.1", &tc4_clk),
215 CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.1", &tc5_clk),
216 CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.0", &ssc_clk),
217 CLKDEV_CON_DEV_ID("pclk", "fffbc000.ssc", &ssc_clk),
218 CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9260.0", &twi_clk),
219 CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g20.0", &twi_clk),
220 /* more usart lookup table for DT entries */
221 CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
222 CLKDEV_CON_DEV_ID("usart", "fffb0000.serial", &usart0_clk),
223 CLKDEV_CON_DEV_ID("usart", "fffb4000.serial", &usart1_clk),
224 CLKDEV_CON_DEV_ID("usart", "fffb8000.serial", &usart2_clk),
225 CLKDEV_CON_DEV_ID("usart", "fffd0000.serial", &usart3_clk),
226 CLKDEV_CON_DEV_ID("usart", "fffd4000.serial", &usart4_clk),
227 CLKDEV_CON_DEV_ID("usart", "fffd8000.serial", &usart5_clk),
228 CLKDEV_CON_DEV_ID(NULL, "fffac000.i2c", &twi_clk),
229 /* more tc lookup table for DT entries */
230 CLKDEV_CON_DEV_ID("t0_clk", "fffa0000.timer", &tc0_clk),
231 CLKDEV_CON_DEV_ID("t1_clk", "fffa0000.timer", &tc1_clk),
232 CLKDEV_CON_DEV_ID("t2_clk", "fffa0000.timer", &tc2_clk),
233 CLKDEV_CON_DEV_ID("t0_clk", "fffdc000.timer", &tc3_clk),
234 CLKDEV_CON_DEV_ID("t1_clk", "fffdc000.timer", &tc4_clk),
235 CLKDEV_CON_DEV_ID("t2_clk", "fffdc000.timer", &tc5_clk),
236 CLKDEV_CON_DEV_ID("hclk", "500000.ohci", &ohci_clk),
237 CLKDEV_CON_DEV_ID("mci_clk", "fffa8000.mmc", &mmc_clk),
238 CLKDEV_CON_DEV_ID("spi_clk", "fffc8000.spi", &spi0_clk),
239 CLKDEV_CON_DEV_ID("spi_clk", "fffcc000.spi", &spi1_clk),
240 /* fake hclk clock */
241 CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
242 CLKDEV_CON_ID("pioA", &pioA_clk),
243 CLKDEV_CON_ID("pioB", &pioB_clk),
244 CLKDEV_CON_ID("pioC", &pioC_clk),
245 CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioA_clk),
246 CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioB_clk),
247 CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioC_clk),
250 static struct clk_lookup usart_clocks_lookups[] = {
251 CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
252 CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
253 CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
254 CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
255 CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
256 CLKDEV_CON_DEV_ID("usart", "atmel_usart.5", &usart4_clk),
257 CLKDEV_CON_DEV_ID("usart", "atmel_usart.6", &usart5_clk),
261 * The two programmable clocks.
262 * You must configure pin multiplexing to bring these signals out.
264 static struct clk pck0 = {
266 .pmc_mask = AT91_PMC_PCK0,
267 .type = CLK_TYPE_PROGRAMMABLE,
270 static struct clk pck1 = {
272 .pmc_mask = AT91_PMC_PCK1,
273 .type = CLK_TYPE_PROGRAMMABLE,
277 static void __init at91sam9260_register_clocks(void)
281 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
282 clk_register(periph_clocks[i]);
284 clkdev_add_table(periph_clocks_lookups,
285 ARRAY_SIZE(periph_clocks_lookups));
286 clkdev_add_table(usart_clocks_lookups,
287 ARRAY_SIZE(usart_clocks_lookups));
293 #define at91sam9260_register_clocks NULL
296 /* --------------------------------------------------------------------
298 * -------------------------------------------------------------------- */
300 static struct at91_gpio_bank at91sam9260_gpio[] __initdata = {
302 .id = AT91SAM9260_ID_PIOA,
303 .regbase = AT91SAM9260_BASE_PIOA,
305 .id = AT91SAM9260_ID_PIOB,
306 .regbase = AT91SAM9260_BASE_PIOB,
308 .id = AT91SAM9260_ID_PIOC,
309 .regbase = AT91SAM9260_BASE_PIOC,
313 /* --------------------------------------------------------------------
314 * AT91SAM9260 processor initialization
315 * -------------------------------------------------------------------- */
317 static void __init at91sam9xe_map_io(void)
319 unsigned long sram_size;
321 switch (at91_soc_initdata.cidr & AT91_CIDR_SRAMSIZ) {
322 case AT91_CIDR_SRAMSIZ_32K:
323 sram_size = 2 * SZ_16K;
325 case AT91_CIDR_SRAMSIZ_16K:
330 at91_init_sram(0, AT91SAM9XE_SRAM_BASE, sram_size);
333 static void __init at91sam9260_map_io(void)
335 if (cpu_is_at91sam9xe())
337 else if (cpu_is_at91sam9g20())
338 at91_init_sram(0, AT91SAM9G20_SRAM_BASE, AT91SAM9G20_SRAM_SIZE);
340 at91_init_sram(0, AT91SAM9260_SRAM_BASE, AT91SAM9260_SRAM_SIZE);
343 static void __init at91sam9260_ioremap_registers(void)
345 at91_ioremap_shdwc(AT91SAM9260_BASE_SHDWC);
346 at91_ioremap_rstc(AT91SAM9260_BASE_RSTC);
347 at91_ioremap_ramc(0, AT91SAM9260_BASE_SDRAMC, 512);
348 at91sam926x_ioremap_pit(AT91SAM9260_BASE_PIT);
349 at91sam9_ioremap_smc(0, AT91SAM9260_BASE_SMC);
350 at91_ioremap_matrix(AT91SAM9260_BASE_MATRIX);
351 at91_pm_set_standby(at91sam9_sdram_standby);
354 static void __init at91sam9260_initialize(void)
356 arm_pm_idle = at91sam9_idle;
357 arm_pm_restart = at91sam9_alt_restart;
359 at91_sysirq_mask_rtt(AT91SAM9260_BASE_RTT);
361 /* Register GPIO subsystem */
362 at91_gpio_init(at91sam9260_gpio, 3);
365 /* --------------------------------------------------------------------
366 * Interrupt initialization
367 * -------------------------------------------------------------------- */
370 * The default interrupt priority levels (0 = lowest, 7 = highest).
372 static unsigned int at91sam9260_default_irq_priority[NR_AIC_IRQS] __initdata = {
373 7, /* Advanced Interrupt Controller */
374 7, /* System Peripherals */
375 1, /* Parallel IO Controller A */
376 1, /* Parallel IO Controller B */
377 1, /* Parallel IO Controller C */
378 0, /* Analog-to-Digital Converter */
382 0, /* Multimedia Card Interface */
383 2, /* USB Device Port */
384 6, /* Two-Wire Interface */
385 5, /* Serial Peripheral Interface 0 */
386 5, /* Serial Peripheral Interface 1 */
387 5, /* Serial Synchronous Controller */
390 0, /* Timer Counter 0 */
391 0, /* Timer Counter 1 */
392 0, /* Timer Counter 2 */
393 2, /* USB Host port */
395 0, /* Image Sensor Interface */
399 0, /* Timer Counter 3 */
400 0, /* Timer Counter 4 */
401 0, /* Timer Counter 5 */
402 0, /* Advanced Interrupt Controller */
403 0, /* Advanced Interrupt Controller */
404 0, /* Advanced Interrupt Controller */
407 AT91_SOC_START(at91sam9260)
408 .map_io = at91sam9260_map_io,
409 .default_irq_priority = at91sam9260_default_irq_priority,
410 .extern_irq = (1 << AT91SAM9260_ID_IRQ0) | (1 << AT91SAM9260_ID_IRQ1)
411 | (1 << AT91SAM9260_ID_IRQ2),
412 .ioremap_registers = at91sam9260_ioremap_registers,
413 .register_clocks = at91sam9260_register_clocks,
414 .init = at91sam9260_initialize,