2 * arch/arm/mach-at91/at91sam9260.c
4 * Copyright (C) 2006 SAN People
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
13 #include <linux/module.h>
17 #include <asm/mach/arch.h>
18 #include <asm/mach/map.h>
20 #include <mach/at91sam9260.h>
21 #include <mach/at91_pmc.h>
22 #include <mach/at91_rstc.h>
23 #include <mach/at91_shdwc.h>
28 static struct map_desc at91sam9260_io_desc[] __initdata = {
30 .virtual = AT91_VA_BASE_SYS,
31 .pfn = __phys_to_pfn(AT91_BASE_SYS),
37 static struct map_desc at91sam9260_sram_desc[] __initdata = {
39 .virtual = AT91_IO_VIRT_BASE - AT91SAM9260_SRAM0_SIZE,
40 .pfn = __phys_to_pfn(AT91SAM9260_SRAM0_BASE),
41 .length = AT91SAM9260_SRAM0_SIZE,
44 .virtual = AT91_IO_VIRT_BASE - AT91SAM9260_SRAM0_SIZE - AT91SAM9260_SRAM1_SIZE,
45 .pfn = __phys_to_pfn(AT91SAM9260_SRAM1_BASE),
46 .length = AT91SAM9260_SRAM1_SIZE,
51 static struct map_desc at91sam9g20_sram_desc[] __initdata = {
53 .virtual = AT91_IO_VIRT_BASE - AT91SAM9G20_SRAM0_SIZE,
54 .pfn = __phys_to_pfn(AT91SAM9G20_SRAM0_BASE),
55 .length = AT91SAM9G20_SRAM0_SIZE,
58 .virtual = AT91_IO_VIRT_BASE - AT91SAM9G20_SRAM0_SIZE - AT91SAM9G20_SRAM1_SIZE,
59 .pfn = __phys_to_pfn(AT91SAM9G20_SRAM1_BASE),
60 .length = AT91SAM9G20_SRAM1_SIZE,
65 static struct map_desc at91sam9xe_sram_desc[] __initdata = {
67 .pfn = __phys_to_pfn(AT91SAM9XE_SRAM_BASE),
72 /* --------------------------------------------------------------------
74 * -------------------------------------------------------------------- */
77 * The peripheral clocks.
79 static struct clk pioA_clk = {
81 .pmc_mask = 1 << AT91SAM9260_ID_PIOA,
82 .type = CLK_TYPE_PERIPHERAL,
84 static struct clk pioB_clk = {
86 .pmc_mask = 1 << AT91SAM9260_ID_PIOB,
87 .type = CLK_TYPE_PERIPHERAL,
89 static struct clk pioC_clk = {
91 .pmc_mask = 1 << AT91SAM9260_ID_PIOC,
92 .type = CLK_TYPE_PERIPHERAL,
94 static struct clk adc_clk = {
96 .pmc_mask = 1 << AT91SAM9260_ID_ADC,
97 .type = CLK_TYPE_PERIPHERAL,
99 static struct clk usart0_clk = {
100 .name = "usart0_clk",
101 .pmc_mask = 1 << AT91SAM9260_ID_US0,
102 .type = CLK_TYPE_PERIPHERAL,
104 static struct clk usart1_clk = {
105 .name = "usart1_clk",
106 .pmc_mask = 1 << AT91SAM9260_ID_US1,
107 .type = CLK_TYPE_PERIPHERAL,
109 static struct clk usart2_clk = {
110 .name = "usart2_clk",
111 .pmc_mask = 1 << AT91SAM9260_ID_US2,
112 .type = CLK_TYPE_PERIPHERAL,
114 static struct clk mmc_clk = {
116 .pmc_mask = 1 << AT91SAM9260_ID_MCI,
117 .type = CLK_TYPE_PERIPHERAL,
119 static struct clk udc_clk = {
121 .pmc_mask = 1 << AT91SAM9260_ID_UDP,
122 .type = CLK_TYPE_PERIPHERAL,
124 static struct clk twi_clk = {
126 .pmc_mask = 1 << AT91SAM9260_ID_TWI,
127 .type = CLK_TYPE_PERIPHERAL,
129 static struct clk spi0_clk = {
131 .pmc_mask = 1 << AT91SAM9260_ID_SPI0,
132 .type = CLK_TYPE_PERIPHERAL,
134 static struct clk spi1_clk = {
136 .pmc_mask = 1 << AT91SAM9260_ID_SPI1,
137 .type = CLK_TYPE_PERIPHERAL,
139 static struct clk ssc_clk = {
141 .pmc_mask = 1 << AT91SAM9260_ID_SSC,
142 .type = CLK_TYPE_PERIPHERAL,
144 static struct clk tc0_clk = {
146 .pmc_mask = 1 << AT91SAM9260_ID_TC0,
147 .type = CLK_TYPE_PERIPHERAL,
149 static struct clk tc1_clk = {
151 .pmc_mask = 1 << AT91SAM9260_ID_TC1,
152 .type = CLK_TYPE_PERIPHERAL,
154 static struct clk tc2_clk = {
156 .pmc_mask = 1 << AT91SAM9260_ID_TC2,
157 .type = CLK_TYPE_PERIPHERAL,
159 static struct clk ohci_clk = {
161 .pmc_mask = 1 << AT91SAM9260_ID_UHP,
162 .type = CLK_TYPE_PERIPHERAL,
164 static struct clk macb_clk = {
166 .pmc_mask = 1 << AT91SAM9260_ID_EMAC,
167 .type = CLK_TYPE_PERIPHERAL,
169 static struct clk isi_clk = {
171 .pmc_mask = 1 << AT91SAM9260_ID_ISI,
172 .type = CLK_TYPE_PERIPHERAL,
174 static struct clk usart3_clk = {
175 .name = "usart3_clk",
176 .pmc_mask = 1 << AT91SAM9260_ID_US3,
177 .type = CLK_TYPE_PERIPHERAL,
179 static struct clk usart4_clk = {
180 .name = "usart4_clk",
181 .pmc_mask = 1 << AT91SAM9260_ID_US4,
182 .type = CLK_TYPE_PERIPHERAL,
184 static struct clk usart5_clk = {
185 .name = "usart5_clk",
186 .pmc_mask = 1 << AT91SAM9260_ID_US5,
187 .type = CLK_TYPE_PERIPHERAL,
189 static struct clk tc3_clk = {
191 .pmc_mask = 1 << AT91SAM9260_ID_TC3,
192 .type = CLK_TYPE_PERIPHERAL,
194 static struct clk tc4_clk = {
196 .pmc_mask = 1 << AT91SAM9260_ID_TC4,
197 .type = CLK_TYPE_PERIPHERAL,
199 static struct clk tc5_clk = {
201 .pmc_mask = 1 << AT91SAM9260_ID_TC5,
202 .type = CLK_TYPE_PERIPHERAL,
205 static struct clk *periph_clocks[] __initdata = {
234 static struct clk_lookup periph_clocks_lookups[] = {
235 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
236 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
237 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
238 CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
239 CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
240 CLKDEV_CON_DEV_ID("t3_clk", "atmel_tcb.1", &tc3_clk),
241 CLKDEV_CON_DEV_ID("t4_clk", "atmel_tcb.1", &tc4_clk),
242 CLKDEV_CON_DEV_ID("t5_clk", "atmel_tcb.1", &tc5_clk),
243 CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc_clk),
246 static struct clk_lookup usart_clocks_lookups[] = {
247 CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
248 CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
249 CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
250 CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
251 CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
252 CLKDEV_CON_DEV_ID("usart", "atmel_usart.5", &usart4_clk),
253 CLKDEV_CON_DEV_ID("usart", "atmel_usart.6", &usart5_clk),
257 * The two programmable clocks.
258 * You must configure pin multiplexing to bring these signals out.
260 static struct clk pck0 = {
262 .pmc_mask = AT91_PMC_PCK0,
263 .type = CLK_TYPE_PROGRAMMABLE,
266 static struct clk pck1 = {
268 .pmc_mask = AT91_PMC_PCK1,
269 .type = CLK_TYPE_PROGRAMMABLE,
273 static void __init at91sam9260_register_clocks(void)
277 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
278 clk_register(periph_clocks[i]);
280 clkdev_add_table(periph_clocks_lookups,
281 ARRAY_SIZE(periph_clocks_lookups));
282 clkdev_add_table(usart_clocks_lookups,
283 ARRAY_SIZE(usart_clocks_lookups));
289 static struct clk_lookup console_clock_lookup;
291 void __init at91sam9260_set_console_clock(int id)
293 if (id >= ARRAY_SIZE(usart_clocks_lookups))
296 console_clock_lookup.con_id = "usart";
297 console_clock_lookup.clk = usart_clocks_lookups[id].clk;
298 clkdev_add(&console_clock_lookup);
301 /* --------------------------------------------------------------------
303 * -------------------------------------------------------------------- */
305 static struct at91_gpio_bank at91sam9260_gpio[] = {
307 .id = AT91SAM9260_ID_PIOA,
311 .id = AT91SAM9260_ID_PIOB,
315 .id = AT91SAM9260_ID_PIOC,
321 static void at91sam9260_poweroff(void)
323 at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
327 /* --------------------------------------------------------------------
328 * AT91SAM9260 processor initialization
329 * -------------------------------------------------------------------- */
331 static void __init at91sam9xe_map_io(void)
333 unsigned long cidr, sram_size;
335 cidr = at91_sys_read(AT91_DBGU_CIDR);
337 switch (cidr & AT91_CIDR_SRAMSIZ) {
338 case AT91_CIDR_SRAMSIZ_32K:
339 sram_size = 2 * SZ_16K;
341 case AT91_CIDR_SRAMSIZ_16K:
346 at91sam9xe_sram_desc->virtual = AT91_IO_VIRT_BASE - sram_size;
347 at91sam9xe_sram_desc->length = sram_size;
349 iotable_init(at91sam9xe_sram_desc, ARRAY_SIZE(at91sam9xe_sram_desc));
352 void __init at91sam9260_map_io(void)
354 /* Map peripherals */
355 iotable_init(at91sam9260_io_desc, ARRAY_SIZE(at91sam9260_io_desc));
357 if (cpu_is_at91sam9xe())
359 else if (cpu_is_at91sam9g20())
360 iotable_init(at91sam9g20_sram_desc, ARRAY_SIZE(at91sam9g20_sram_desc));
362 iotable_init(at91sam9260_sram_desc, ARRAY_SIZE(at91sam9260_sram_desc));
365 void __init at91sam9260_initialize(unsigned long main_clock)
367 at91_arch_reset = at91sam9_alt_reset;
368 pm_power_off = at91sam9260_poweroff;
369 at91_extern_irq = (1 << AT91SAM9260_ID_IRQ0) | (1 << AT91SAM9260_ID_IRQ1)
370 | (1 << AT91SAM9260_ID_IRQ2);
372 /* Init clock subsystem */
373 at91_clock_init(main_clock);
375 /* Register the processor-specific clocks */
376 at91sam9260_register_clocks();
378 /* Register GPIO subsystem */
379 at91_gpio_init(at91sam9260_gpio, 3);
382 /* --------------------------------------------------------------------
383 * Interrupt initialization
384 * -------------------------------------------------------------------- */
387 * The default interrupt priority levels (0 = lowest, 7 = highest).
389 static unsigned int at91sam9260_default_irq_priority[NR_AIC_IRQS] __initdata = {
390 7, /* Advanced Interrupt Controller */
391 7, /* System Peripherals */
392 1, /* Parallel IO Controller A */
393 1, /* Parallel IO Controller B */
394 1, /* Parallel IO Controller C */
395 0, /* Analog-to-Digital Converter */
399 0, /* Multimedia Card Interface */
400 2, /* USB Device Port */
401 6, /* Two-Wire Interface */
402 5, /* Serial Peripheral Interface 0 */
403 5, /* Serial Peripheral Interface 1 */
404 5, /* Serial Synchronous Controller */
407 0, /* Timer Counter 0 */
408 0, /* Timer Counter 1 */
409 0, /* Timer Counter 2 */
410 2, /* USB Host port */
412 0, /* Image Sensor Interface */
416 0, /* Timer Counter 3 */
417 0, /* Timer Counter 4 */
418 0, /* Timer Counter 5 */
419 0, /* Advanced Interrupt Controller */
420 0, /* Advanced Interrupt Controller */
421 0, /* Advanced Interrupt Controller */
424 void __init at91sam9260_init_interrupts(unsigned int priority[NR_AIC_IRQS])
427 priority = at91sam9260_default_irq_priority;
429 /* Initialize the AIC interrupt controller */
430 at91_aic_init(priority);
432 /* Enable GPIO interrupts */
433 at91_gpio_irq_setup();