2 * arch/arm/mach-at91/at91sam9260.c
4 * Copyright (C) 2006 SAN People
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
13 #include <linux/module.h>
15 #include <asm/proc-fns.h>
17 #include <asm/mach/arch.h>
18 #include <asm/mach/map.h>
19 #include <asm/system_misc.h>
21 #include <mach/at91_dbgu.h>
22 #include <mach/at91sam9260.h>
23 #include <mach/at91_pmc.h>
24 #include <mach/at91_rstc.h>
31 /* --------------------------------------------------------------------
33 * -------------------------------------------------------------------- */
36 * The peripheral clocks.
38 static struct clk pioA_clk = {
40 .pmc_mask = 1 << AT91SAM9260_ID_PIOA,
41 .type = CLK_TYPE_PERIPHERAL,
43 static struct clk pioB_clk = {
45 .pmc_mask = 1 << AT91SAM9260_ID_PIOB,
46 .type = CLK_TYPE_PERIPHERAL,
48 static struct clk pioC_clk = {
50 .pmc_mask = 1 << AT91SAM9260_ID_PIOC,
51 .type = CLK_TYPE_PERIPHERAL,
53 static struct clk adc_clk = {
55 .pmc_mask = 1 << AT91SAM9260_ID_ADC,
56 .type = CLK_TYPE_PERIPHERAL,
58 static struct clk usart0_clk = {
60 .pmc_mask = 1 << AT91SAM9260_ID_US0,
61 .type = CLK_TYPE_PERIPHERAL,
63 static struct clk usart1_clk = {
65 .pmc_mask = 1 << AT91SAM9260_ID_US1,
66 .type = CLK_TYPE_PERIPHERAL,
68 static struct clk usart2_clk = {
70 .pmc_mask = 1 << AT91SAM9260_ID_US2,
71 .type = CLK_TYPE_PERIPHERAL,
73 static struct clk mmc_clk = {
75 .pmc_mask = 1 << AT91SAM9260_ID_MCI,
76 .type = CLK_TYPE_PERIPHERAL,
78 static struct clk udc_clk = {
80 .pmc_mask = 1 << AT91SAM9260_ID_UDP,
81 .type = CLK_TYPE_PERIPHERAL,
83 static struct clk twi_clk = {
85 .pmc_mask = 1 << AT91SAM9260_ID_TWI,
86 .type = CLK_TYPE_PERIPHERAL,
88 static struct clk spi0_clk = {
90 .pmc_mask = 1 << AT91SAM9260_ID_SPI0,
91 .type = CLK_TYPE_PERIPHERAL,
93 static struct clk spi1_clk = {
95 .pmc_mask = 1 << AT91SAM9260_ID_SPI1,
96 .type = CLK_TYPE_PERIPHERAL,
98 static struct clk ssc_clk = {
100 .pmc_mask = 1 << AT91SAM9260_ID_SSC,
101 .type = CLK_TYPE_PERIPHERAL,
103 static struct clk tc0_clk = {
105 .pmc_mask = 1 << AT91SAM9260_ID_TC0,
106 .type = CLK_TYPE_PERIPHERAL,
108 static struct clk tc1_clk = {
110 .pmc_mask = 1 << AT91SAM9260_ID_TC1,
111 .type = CLK_TYPE_PERIPHERAL,
113 static struct clk tc2_clk = {
115 .pmc_mask = 1 << AT91SAM9260_ID_TC2,
116 .type = CLK_TYPE_PERIPHERAL,
118 static struct clk ohci_clk = {
120 .pmc_mask = 1 << AT91SAM9260_ID_UHP,
121 .type = CLK_TYPE_PERIPHERAL,
123 static struct clk macb_clk = {
125 .pmc_mask = 1 << AT91SAM9260_ID_EMAC,
126 .type = CLK_TYPE_PERIPHERAL,
128 static struct clk isi_clk = {
130 .pmc_mask = 1 << AT91SAM9260_ID_ISI,
131 .type = CLK_TYPE_PERIPHERAL,
133 static struct clk usart3_clk = {
134 .name = "usart3_clk",
135 .pmc_mask = 1 << AT91SAM9260_ID_US3,
136 .type = CLK_TYPE_PERIPHERAL,
138 static struct clk usart4_clk = {
139 .name = "usart4_clk",
140 .pmc_mask = 1 << AT91SAM9260_ID_US4,
141 .type = CLK_TYPE_PERIPHERAL,
143 static struct clk usart5_clk = {
144 .name = "usart5_clk",
145 .pmc_mask = 1 << AT91SAM9260_ID_US5,
146 .type = CLK_TYPE_PERIPHERAL,
148 static struct clk tc3_clk = {
150 .pmc_mask = 1 << AT91SAM9260_ID_TC3,
151 .type = CLK_TYPE_PERIPHERAL,
153 static struct clk tc4_clk = {
155 .pmc_mask = 1 << AT91SAM9260_ID_TC4,
156 .type = CLK_TYPE_PERIPHERAL,
158 static struct clk tc5_clk = {
160 .pmc_mask = 1 << AT91SAM9260_ID_TC5,
161 .type = CLK_TYPE_PERIPHERAL,
164 static struct clk *periph_clocks[] __initdata = {
193 static struct clk_lookup periph_clocks_lookups[] = {
194 /* One additional fake clock for macb_hclk */
195 CLKDEV_CON_ID("hclk", &macb_clk),
196 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
197 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
198 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
199 CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
200 CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
201 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tc3_clk),
202 CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.1", &tc4_clk),
203 CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.1", &tc5_clk),
204 CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc_clk),
205 /* more usart lookup table for DT entries */
206 CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
207 CLKDEV_CON_DEV_ID("usart", "fffb0000.serial", &usart0_clk),
208 CLKDEV_CON_DEV_ID("usart", "fffb4000.serial", &usart1_clk),
209 CLKDEV_CON_DEV_ID("usart", "fffb8000.serial", &usart2_clk),
210 CLKDEV_CON_DEV_ID("usart", "fffd0000.serial", &usart3_clk),
211 CLKDEV_CON_DEV_ID("usart", "fffd4000.serial", &usart4_clk),
212 CLKDEV_CON_DEV_ID("usart", "fffd8000.serial", &usart5_clk),
213 /* more tc lookup table for DT entries */
214 CLKDEV_CON_DEV_ID("t0_clk", "fffa0000.timer", &tc0_clk),
215 CLKDEV_CON_DEV_ID("t1_clk", "fffa0000.timer", &tc1_clk),
216 CLKDEV_CON_DEV_ID("t2_clk", "fffa0000.timer", &tc2_clk),
217 CLKDEV_CON_DEV_ID("t0_clk", "fffdc000.timer", &tc3_clk),
218 CLKDEV_CON_DEV_ID("t1_clk", "fffdc000.timer", &tc4_clk),
219 CLKDEV_CON_DEV_ID("t2_clk", "fffdc000.timer", &tc5_clk),
220 CLKDEV_CON_DEV_ID("hclk", "500000.ohci", &ohci_clk),
221 /* fake hclk clock */
222 CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
223 CLKDEV_CON_ID("pioA", &pioA_clk),
224 CLKDEV_CON_ID("pioB", &pioB_clk),
225 CLKDEV_CON_ID("pioC", &pioC_clk),
228 static struct clk_lookup usart_clocks_lookups[] = {
229 CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
230 CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
231 CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
232 CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
233 CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
234 CLKDEV_CON_DEV_ID("usart", "atmel_usart.5", &usart4_clk),
235 CLKDEV_CON_DEV_ID("usart", "atmel_usart.6", &usart5_clk),
239 * The two programmable clocks.
240 * You must configure pin multiplexing to bring these signals out.
242 static struct clk pck0 = {
244 .pmc_mask = AT91_PMC_PCK0,
245 .type = CLK_TYPE_PROGRAMMABLE,
248 static struct clk pck1 = {
250 .pmc_mask = AT91_PMC_PCK1,
251 .type = CLK_TYPE_PROGRAMMABLE,
255 static void __init at91sam9260_register_clocks(void)
259 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
260 clk_register(periph_clocks[i]);
262 clkdev_add_table(periph_clocks_lookups,
263 ARRAY_SIZE(periph_clocks_lookups));
264 clkdev_add_table(usart_clocks_lookups,
265 ARRAY_SIZE(usart_clocks_lookups));
271 /* --------------------------------------------------------------------
273 * -------------------------------------------------------------------- */
275 static struct at91_gpio_bank at91sam9260_gpio[] __initdata = {
277 .id = AT91SAM9260_ID_PIOA,
278 .regbase = AT91SAM9260_BASE_PIOA,
280 .id = AT91SAM9260_ID_PIOB,
281 .regbase = AT91SAM9260_BASE_PIOB,
283 .id = AT91SAM9260_ID_PIOC,
284 .regbase = AT91SAM9260_BASE_PIOC,
288 /* --------------------------------------------------------------------
289 * AT91SAM9260 processor initialization
290 * -------------------------------------------------------------------- */
292 static void __init at91sam9xe_map_io(void)
294 unsigned long sram_size;
296 switch (at91_soc_initdata.cidr & AT91_CIDR_SRAMSIZ) {
297 case AT91_CIDR_SRAMSIZ_32K:
298 sram_size = 2 * SZ_16K;
300 case AT91_CIDR_SRAMSIZ_16K:
305 at91_init_sram(0, AT91SAM9XE_SRAM_BASE, sram_size);
308 static void __init at91sam9260_map_io(void)
310 if (cpu_is_at91sam9xe())
312 else if (cpu_is_at91sam9g20())
313 at91_init_sram(0, AT91SAM9G20_SRAM_BASE, AT91SAM9G20_SRAM_SIZE);
315 at91_init_sram(0, AT91SAM9260_SRAM_BASE, AT91SAM9260_SRAM_SIZE);
318 static void __init at91sam9260_ioremap_registers(void)
320 at91_ioremap_shdwc(AT91SAM9260_BASE_SHDWC);
321 at91_ioremap_rstc(AT91SAM9260_BASE_RSTC);
322 at91_ioremap_ramc(0, AT91SAM9260_BASE_SDRAMC, 512);
323 at91sam926x_ioremap_pit(AT91SAM9260_BASE_PIT);
324 at91sam9_ioremap_smc(0, AT91SAM9260_BASE_SMC);
325 at91_ioremap_matrix(AT91SAM9260_BASE_MATRIX);
328 static void __init at91sam9260_initialize(void)
330 arm_pm_idle = at91sam9_idle;
331 arm_pm_restart = at91sam9_alt_restart;
332 at91_extern_irq = (1 << AT91SAM9260_ID_IRQ0) | (1 << AT91SAM9260_ID_IRQ1)
333 | (1 << AT91SAM9260_ID_IRQ2);
335 /* Register GPIO subsystem */
336 at91_gpio_init(at91sam9260_gpio, 3);
339 /* --------------------------------------------------------------------
340 * Interrupt initialization
341 * -------------------------------------------------------------------- */
344 * The default interrupt priority levels (0 = lowest, 7 = highest).
346 static unsigned int at91sam9260_default_irq_priority[NR_AIC_IRQS] __initdata = {
347 7, /* Advanced Interrupt Controller */
348 7, /* System Peripherals */
349 1, /* Parallel IO Controller A */
350 1, /* Parallel IO Controller B */
351 1, /* Parallel IO Controller C */
352 0, /* Analog-to-Digital Converter */
356 0, /* Multimedia Card Interface */
357 2, /* USB Device Port */
358 6, /* Two-Wire Interface */
359 5, /* Serial Peripheral Interface 0 */
360 5, /* Serial Peripheral Interface 1 */
361 5, /* Serial Synchronous Controller */
364 0, /* Timer Counter 0 */
365 0, /* Timer Counter 1 */
366 0, /* Timer Counter 2 */
367 2, /* USB Host port */
369 0, /* Image Sensor Interface */
373 0, /* Timer Counter 3 */
374 0, /* Timer Counter 4 */
375 0, /* Timer Counter 5 */
376 0, /* Advanced Interrupt Controller */
377 0, /* Advanced Interrupt Controller */
378 0, /* Advanced Interrupt Controller */
381 struct at91_init_soc __initdata at91sam9260_soc = {
382 .map_io = at91sam9260_map_io,
383 .default_irq_priority = at91sam9260_default_irq_priority,
384 .ioremap_registers = at91sam9260_ioremap_registers,
385 .register_clocks = at91sam9260_register_clocks,
386 .init = at91sam9260_initialize,