2 * arch/arm/mach-at91/at91sam9261.c
4 * Copyright (C) 2005 SAN People
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
13 #include <linux/module.h>
16 #include <asm/mach/arch.h>
17 #include <asm/mach/map.h>
19 #include <mach/at91sam9261.h>
20 #include <mach/at91_pmc.h>
21 #include <mach/at91_rstc.h>
28 /* --------------------------------------------------------------------
30 * -------------------------------------------------------------------- */
33 * The peripheral clocks.
35 static struct clk pioA_clk = {
37 .pmc_mask = 1 << AT91SAM9261_ID_PIOA,
38 .type = CLK_TYPE_PERIPHERAL,
40 static struct clk pioB_clk = {
42 .pmc_mask = 1 << AT91SAM9261_ID_PIOB,
43 .type = CLK_TYPE_PERIPHERAL,
45 static struct clk pioC_clk = {
47 .pmc_mask = 1 << AT91SAM9261_ID_PIOC,
48 .type = CLK_TYPE_PERIPHERAL,
50 static struct clk usart0_clk = {
52 .pmc_mask = 1 << AT91SAM9261_ID_US0,
53 .type = CLK_TYPE_PERIPHERAL,
55 static struct clk usart1_clk = {
57 .pmc_mask = 1 << AT91SAM9261_ID_US1,
58 .type = CLK_TYPE_PERIPHERAL,
60 static struct clk usart2_clk = {
62 .pmc_mask = 1 << AT91SAM9261_ID_US2,
63 .type = CLK_TYPE_PERIPHERAL,
65 static struct clk mmc_clk = {
67 .pmc_mask = 1 << AT91SAM9261_ID_MCI,
68 .type = CLK_TYPE_PERIPHERAL,
70 static struct clk udc_clk = {
72 .pmc_mask = 1 << AT91SAM9261_ID_UDP,
73 .type = CLK_TYPE_PERIPHERAL,
75 static struct clk twi_clk = {
77 .pmc_mask = 1 << AT91SAM9261_ID_TWI,
78 .type = CLK_TYPE_PERIPHERAL,
80 static struct clk spi0_clk = {
82 .pmc_mask = 1 << AT91SAM9261_ID_SPI0,
83 .type = CLK_TYPE_PERIPHERAL,
85 static struct clk spi1_clk = {
87 .pmc_mask = 1 << AT91SAM9261_ID_SPI1,
88 .type = CLK_TYPE_PERIPHERAL,
90 static struct clk ssc0_clk = {
92 .pmc_mask = 1 << AT91SAM9261_ID_SSC0,
93 .type = CLK_TYPE_PERIPHERAL,
95 static struct clk ssc1_clk = {
97 .pmc_mask = 1 << AT91SAM9261_ID_SSC1,
98 .type = CLK_TYPE_PERIPHERAL,
100 static struct clk ssc2_clk = {
102 .pmc_mask = 1 << AT91SAM9261_ID_SSC2,
103 .type = CLK_TYPE_PERIPHERAL,
105 static struct clk tc0_clk = {
107 .pmc_mask = 1 << AT91SAM9261_ID_TC0,
108 .type = CLK_TYPE_PERIPHERAL,
110 static struct clk tc1_clk = {
112 .pmc_mask = 1 << AT91SAM9261_ID_TC1,
113 .type = CLK_TYPE_PERIPHERAL,
115 static struct clk tc2_clk = {
117 .pmc_mask = 1 << AT91SAM9261_ID_TC2,
118 .type = CLK_TYPE_PERIPHERAL,
120 static struct clk ohci_clk = {
122 .pmc_mask = 1 << AT91SAM9261_ID_UHP,
123 .type = CLK_TYPE_PERIPHERAL,
125 static struct clk lcdc_clk = {
127 .pmc_mask = 1 << AT91SAM9261_ID_LCDC,
128 .type = CLK_TYPE_PERIPHERAL,
132 static struct clk hck0 = {
134 .pmc_mask = AT91_PMC_HCK0,
135 .type = CLK_TYPE_SYSTEM,
138 static struct clk hck1 = {
140 .pmc_mask = AT91_PMC_HCK1,
141 .type = CLK_TYPE_SYSTEM,
145 static struct clk *periph_clocks[] __initdata = {
168 static struct clk_lookup periph_clocks_lookups[] = {
169 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
170 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
171 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
172 CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
173 CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
174 CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
175 CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
176 CLKDEV_CON_DEV_ID("pclk", "ssc.2", &ssc2_clk),
177 CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &hck0),
178 CLKDEV_CON_ID("pioA", &pioA_clk),
179 CLKDEV_CON_ID("pioB", &pioB_clk),
180 CLKDEV_CON_ID("pioC", &pioC_clk),
183 static struct clk_lookup usart_clocks_lookups[] = {
184 CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
185 CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
186 CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
187 CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
191 * The four programmable clocks.
192 * You must configure pin multiplexing to bring these signals out.
194 static struct clk pck0 = {
196 .pmc_mask = AT91_PMC_PCK0,
197 .type = CLK_TYPE_PROGRAMMABLE,
200 static struct clk pck1 = {
202 .pmc_mask = AT91_PMC_PCK1,
203 .type = CLK_TYPE_PROGRAMMABLE,
206 static struct clk pck2 = {
208 .pmc_mask = AT91_PMC_PCK2,
209 .type = CLK_TYPE_PROGRAMMABLE,
212 static struct clk pck3 = {
214 .pmc_mask = AT91_PMC_PCK3,
215 .type = CLK_TYPE_PROGRAMMABLE,
219 static void __init at91sam9261_register_clocks(void)
223 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
224 clk_register(periph_clocks[i]);
226 clkdev_add_table(periph_clocks_lookups,
227 ARRAY_SIZE(periph_clocks_lookups));
228 clkdev_add_table(usart_clocks_lookups,
229 ARRAY_SIZE(usart_clocks_lookups));
240 static struct clk_lookup console_clock_lookup;
242 void __init at91sam9261_set_console_clock(int id)
244 if (id >= ARRAY_SIZE(usart_clocks_lookups))
247 console_clock_lookup.con_id = "usart";
248 console_clock_lookup.clk = usart_clocks_lookups[id].clk;
249 clkdev_add(&console_clock_lookup);
252 /* --------------------------------------------------------------------
254 * -------------------------------------------------------------------- */
256 static struct at91_gpio_bank at91sam9261_gpio[] __initdata = {
258 .id = AT91SAM9261_ID_PIOA,
259 .regbase = AT91SAM9261_BASE_PIOA,
261 .id = AT91SAM9261_ID_PIOB,
262 .regbase = AT91SAM9261_BASE_PIOB,
264 .id = AT91SAM9261_ID_PIOC,
265 .regbase = AT91SAM9261_BASE_PIOC,
269 /* --------------------------------------------------------------------
270 * AT91SAM9261 processor initialization
271 * -------------------------------------------------------------------- */
273 static void __init at91sam9261_map_io(void)
275 if (cpu_is_at91sam9g10())
276 at91_init_sram(0, AT91SAM9G10_SRAM_BASE, AT91SAM9G10_SRAM_SIZE);
278 at91_init_sram(0, AT91SAM9261_SRAM_BASE, AT91SAM9261_SRAM_SIZE);
281 static void __init at91sam9261_ioremap_registers(void)
283 at91_ioremap_shdwc(AT91SAM9261_BASE_SHDWC);
284 at91_ioremap_rstc(AT91SAM9261_BASE_RSTC);
285 at91sam926x_ioremap_pit(AT91SAM9261_BASE_PIT);
286 at91sam9_ioremap_smc(0, AT91SAM9261_BASE_SMC);
289 static void __init at91sam9261_initialize(void)
291 arm_pm_restart = at91sam9_alt_restart;
292 at91_extern_irq = (1 << AT91SAM9261_ID_IRQ0) | (1 << AT91SAM9261_ID_IRQ1)
293 | (1 << AT91SAM9261_ID_IRQ2);
295 /* Register GPIO subsystem */
296 at91_gpio_init(at91sam9261_gpio, 3);
299 /* --------------------------------------------------------------------
300 * Interrupt initialization
301 * -------------------------------------------------------------------- */
304 * The default interrupt priority levels (0 = lowest, 7 = highest).
306 static unsigned int at91sam9261_default_irq_priority[NR_AIC_IRQS] __initdata = {
307 7, /* Advanced Interrupt Controller */
308 7, /* System Peripherals */
309 1, /* Parallel IO Controller A */
310 1, /* Parallel IO Controller B */
311 1, /* Parallel IO Controller C */
316 0, /* Multimedia Card Interface */
317 2, /* USB Device Port */
318 6, /* Two-Wire Interface */
319 5, /* Serial Peripheral Interface 0 */
320 5, /* Serial Peripheral Interface 1 */
321 4, /* Serial Synchronous Controller 0 */
322 4, /* Serial Synchronous Controller 1 */
323 4, /* Serial Synchronous Controller 2 */
324 0, /* Timer Counter 0 */
325 0, /* Timer Counter 1 */
326 0, /* Timer Counter 2 */
327 2, /* USB Host port */
328 3, /* LCD Controller */
336 0, /* Advanced Interrupt Controller */
337 0, /* Advanced Interrupt Controller */
338 0, /* Advanced Interrupt Controller */
341 struct at91_init_soc __initdata at91sam9261_soc = {
342 .map_io = at91sam9261_map_io,
343 .default_irq_priority = at91sam9261_default_irq_priority,
344 .ioremap_registers = at91sam9261_ioremap_registers,
345 .register_clocks = at91sam9261_register_clocks,
346 .init = at91sam9261_initialize,