arch/arm/mach-at91/at91sam9261.c

   1 /*
   2  * arch/arm/mach-at91/at91sam9261.c
   3  *
   4  *  Copyright (C) 2005 SAN People
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  */
  12
  13 #include <linux/module.h>
  14
  15 #include <asm/proc-fns.h>
  16 #include <asm/irq.h>
  17 #include <asm/mach/arch.h>
  18 #include <asm/mach/map.h>
  19 #include <asm/system_misc.h>
  20 #include <mach/cpu.h>
  21 #include <mach/at91sam9261.h>
  22 #include <mach/at91_pmc.h>
  23 #include <mach/at91_rstc.h>
  24
  25 #include "soc.h"
  26 #include "generic.h"
  27 #include "clock.h"
  28 #include "sam9_smc.h"
  29
  30 /* --------------------------------------------------------------------
  31  *  Clocks
  32  * -------------------------------------------------------------------- */
  33
  34 /*
  35  * The peripheral clocks.
  36  */
  37 static struct clk pioA_clk = {
  38         .name           = "pioA_clk",
  39         .pmc_mask       = 1 << AT91SAM9261_ID_PIOA,
  40         .type           = CLK_TYPE_PERIPHERAL,
  41 };
  42 static struct clk pioB_clk = {
  43         .name           = "pioB_clk",
  44         .pmc_mask       = 1 << AT91SAM9261_ID_PIOB,
  45         .type           = CLK_TYPE_PERIPHERAL,
  46 };
  47 static struct clk pioC_clk = {
  48         .name           = "pioC_clk",
  49         .pmc_mask       = 1 << AT91SAM9261_ID_PIOC,
  50         .type           = CLK_TYPE_PERIPHERAL,
  51 };
  52 static struct clk usart0_clk = {
  53         .name           = "usart0_clk",
  54         .pmc_mask       = 1 << AT91SAM9261_ID_US0,
  55         .type           = CLK_TYPE_PERIPHERAL,
  56 };
  57 static struct clk usart1_clk = {
  58         .name           = "usart1_clk",
  59         .pmc_mask       = 1 << AT91SAM9261_ID_US1,
  60         .type           = CLK_TYPE_PERIPHERAL,
  61 };
  62 static struct clk usart2_clk = {
  63         .name           = "usart2_clk",
  64         .pmc_mask       = 1 << AT91SAM9261_ID_US2,
  65         .type           = CLK_TYPE_PERIPHERAL,
  66 };
  67 static struct clk mmc_clk = {
  68         .name           = "mci_clk",
  69         .pmc_mask       = 1 << AT91SAM9261_ID_MCI,
  70         .type           = CLK_TYPE_PERIPHERAL,
  71 };
  72 static struct clk udc_clk = {
  73         .name           = "udc_clk",
  74         .pmc_mask       = 1 << AT91SAM9261_ID_UDP,
  75         .type           = CLK_TYPE_PERIPHERAL,
  76 };
  77 static struct clk twi_clk = {
  78         .name           = "twi_clk",
  79         .pmc_mask       = 1 << AT91SAM9261_ID_TWI,
  80         .type           = CLK_TYPE_PERIPHERAL,
  81 };
  82 static struct clk spi0_clk = {
  83         .name           = "spi0_clk",
  84         .pmc_mask       = 1 << AT91SAM9261_ID_SPI0,
  85         .type           = CLK_TYPE_PERIPHERAL,
  86 };
  87 static struct clk spi1_clk = {
  88         .name           = "spi1_clk",
  89         .pmc_mask       = 1 << AT91SAM9261_ID_SPI1,
  90         .type           = CLK_TYPE_PERIPHERAL,
  91 };
  92 static struct clk ssc0_clk = {
  93         .name           = "ssc0_clk",
  94         .pmc_mask       = 1 << AT91SAM9261_ID_SSC0,
  95         .type           = CLK_TYPE_PERIPHERAL,
  96 };
  97 static struct clk ssc1_clk = {
  98         .name           = "ssc1_clk",
  99         .pmc_mask       = 1 << AT91SAM9261_ID_SSC1,
 100         .type           = CLK_TYPE_PERIPHERAL,
 101 };
 102 static struct clk ssc2_clk = {
 103         .name           = "ssc2_clk",
 104         .pmc_mask       = 1 << AT91SAM9261_ID_SSC2,
 105         .type           = CLK_TYPE_PERIPHERAL,
 106 };
 107 static struct clk tc0_clk = {
 108         .name           = "tc0_clk",
 109         .pmc_mask       = 1 << AT91SAM9261_ID_TC0,
 110         .type           = CLK_TYPE_PERIPHERAL,
 111 };
 112 static struct clk tc1_clk = {
 113         .name           = "tc1_clk",
 114         .pmc_mask       = 1 << AT91SAM9261_ID_TC1,
 115         .type           = CLK_TYPE_PERIPHERAL,
 116 };
 117 static struct clk tc2_clk = {
 118         .name           = "tc2_clk",
 119         .pmc_mask       = 1 << AT91SAM9261_ID_TC2,
 120         .type           = CLK_TYPE_PERIPHERAL,
 121 };
 122 static struct clk ohci_clk = {
 123         .name           = "ohci_clk",
 124         .pmc_mask       = 1 << AT91SAM9261_ID_UHP,
 125         .type           = CLK_TYPE_PERIPHERAL,
 126 };
 127 static struct clk lcdc_clk = {
 128         .name           = "lcdc_clk",
 129         .pmc_mask       = 1 << AT91SAM9261_ID_LCDC,
 130         .type           = CLK_TYPE_PERIPHERAL,
 131 };
 132
 133 /* HClocks */
 134 static struct clk hck0 = {
 135         .name           = "hck0",
 136         .pmc_mask       = AT91_PMC_HCK0,
 137         .type           = CLK_TYPE_SYSTEM,
 138         .id             = 0,
 139 };
 140 static struct clk hck1 = {
 141         .name           = "hck1",
 142         .pmc_mask       = AT91_PMC_HCK1,
 143         .type           = CLK_TYPE_SYSTEM,
 144         .id             = 1,
 145 };
 146
 147 static struct clk *periph_clocks[] __initdata = {
 148         &pioA_clk,
 149         &pioB_clk,
 150         &pioC_clk,
 151         &usart0_clk,
 152         &usart1_clk,
 153         &usart2_clk,
 154         &mmc_clk,
 155         &udc_clk,
 156         &twi_clk,
 157         &spi0_clk,
 158         &spi1_clk,
 159         &ssc0_clk,
 160         &ssc1_clk,
 161         &ssc2_clk,
 162         &tc0_clk,
 163         &tc1_clk,
 164         &tc2_clk,
 165         &ohci_clk,
 166         &lcdc_clk,
 167         // irq0 .. irq2
 168 };
 169
 170 static struct clk_lookup periph_clocks_lookups[] = {
 171         CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
 172         CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
 173         CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
 174         CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
 175         CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
 176         CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
 177         CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
 178         CLKDEV_CON_DEV_ID("pclk", "ssc.2", &ssc2_clk),
 179         CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &hck0),
 180         CLKDEV_CON_ID("pioA", &pioA_clk),
 181         CLKDEV_CON_ID("pioB", &pioB_clk),
 182         CLKDEV_CON_ID("pioC", &pioC_clk),
 183 };
 184
 185 static struct clk_lookup usart_clocks_lookups[] = {
 186         CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
 187         CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
 188         CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
 189         CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
 190 };
 191
 192 /*
 193  * The four programmable clocks.
 194  * You must configure pin multiplexing to bring these signals out.
 195  */
 196 static struct clk pck0 = {
 197         .name           = "pck0",
 198         .pmc_mask       = AT91_PMC_PCK0,
 199         .type           = CLK_TYPE_PROGRAMMABLE,
 200         .id             = 0,
 201 };
 202 static struct clk pck1 = {
 203         .name           = "pck1",
 204         .pmc_mask       = AT91_PMC_PCK1,
 205         .type           = CLK_TYPE_PROGRAMMABLE,
 206         .id             = 1,
 207 };
 208 static struct clk pck2 = {
 209         .name           = "pck2",
 210         .pmc_mask       = AT91_PMC_PCK2,
 211         .type           = CLK_TYPE_PROGRAMMABLE,
 212         .id             = 2,
 213 };
 214 static struct clk pck3 = {
 215         .name           = "pck3",
 216         .pmc_mask       = AT91_PMC_PCK3,
 217         .type           = CLK_TYPE_PROGRAMMABLE,
 218         .id             = 3,
 219 };
 220
 221 static void __init at91sam9261_register_clocks(void)
 222 {
 223         int i;
 224
 225         for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
 226                 clk_register(periph_clocks[i]);
 227
 228         clkdev_add_table(periph_clocks_lookups,
 229                          ARRAY_SIZE(periph_clocks_lookups));
 230         clkdev_add_table(usart_clocks_lookups,
 231                          ARRAY_SIZE(usart_clocks_lookups));
 232
 233         clk_register(&pck0);
 234         clk_register(&pck1);
 235         clk_register(&pck2);
 236         clk_register(&pck3);
 237
 238         clk_register(&hck0);
 239         clk_register(&hck1);
 240 }
 241
 242 /* --------------------------------------------------------------------
 243  *  GPIO
 244  * -------------------------------------------------------------------- */
 245
 246 static struct at91_gpio_bank at91sam9261_gpio[] __initdata = {
 247         {
 248                 .id             = AT91SAM9261_ID_PIOA,
 249                 .regbase        = AT91SAM9261_BASE_PIOA,
 250         }, {
 251                 .id             = AT91SAM9261_ID_PIOB,
 252                 .regbase        = AT91SAM9261_BASE_PIOB,
 253         }, {
 254                 .id             = AT91SAM9261_ID_PIOC,
 255                 .regbase        = AT91SAM9261_BASE_PIOC,
 256         }
 257 };
 258
 259 /* --------------------------------------------------------------------
 260  *  AT91SAM9261 processor initialization
 261  * -------------------------------------------------------------------- */
 262
 263 static void __init at91sam9261_map_io(void)
 264 {
 265         if (cpu_is_at91sam9g10())
 266                 at91_init_sram(0, AT91SAM9G10_SRAM_BASE, AT91SAM9G10_SRAM_SIZE);
 267         else
 268                 at91_init_sram(0, AT91SAM9261_SRAM_BASE, AT91SAM9261_SRAM_SIZE);
 269 }
 270
 271 static void __init at91sam9261_ioremap_registers(void)
 272 {
 273         at91_ioremap_shdwc(AT91SAM9261_BASE_SHDWC);
 274         at91_ioremap_rstc(AT91SAM9261_BASE_RSTC);
 275         at91_ioremap_ramc(0, AT91SAM9261_BASE_SDRAMC, 512);
 276         at91sam926x_ioremap_pit(AT91SAM9261_BASE_PIT);
 277         at91sam9_ioremap_smc(0, AT91SAM9261_BASE_SMC);
 278         at91_ioremap_matrix(AT91SAM9261_BASE_MATRIX);
 279 }
 280
 281 static void __init at91sam9261_initialize(void)
 282 {
 283         arm_pm_idle = at91sam9_idle;
 284         arm_pm_restart = at91sam9_alt_restart;
 285         at91_extern_irq = (1 << AT91SAM9261_ID_IRQ0) | (1 << AT91SAM9261_ID_IRQ1)
 286                         | (1 << AT91SAM9261_ID_IRQ2);
 287
 288         /* Register GPIO subsystem */
 289         at91_gpio_init(at91sam9261_gpio, 3);
 290 }
 291
 292 /* --------------------------------------------------------------------
 293  *  Interrupt initialization
 294  * -------------------------------------------------------------------- */
 295
 296 /*
 297  * The default interrupt priority levels (0 = lowest, 7 = highest).
 298  */
 299 static unsigned int at91sam9261_default_irq_priority[NR_AIC_IRQS] __initdata = {
 300         7,      /* Advanced Interrupt Controller */
 301         7,      /* System Peripherals */
 302         1,      /* Parallel IO Controller A */
 303         1,      /* Parallel IO Controller B */
 304         1,      /* Parallel IO Controller C */
 305         0,
 306         5,      /* USART 0 */
 307         5,      /* USART 1 */
 308         5,      /* USART 2 */
 309         0,      /* Multimedia Card Interface */
 310         2,      /* USB Device Port */
 311         6,      /* Two-Wire Interface */
 312         5,      /* Serial Peripheral Interface 0 */
 313         5,      /* Serial Peripheral Interface 1 */
 314         4,      /* Serial Synchronous Controller 0 */
 315         4,      /* Serial Synchronous Controller 1 */
 316         4,      /* Serial Synchronous Controller 2 */
 317         0,      /* Timer Counter 0 */
 318         0,      /* Timer Counter 1 */
 319         0,      /* Timer Counter 2 */
 320         2,      /* USB Host port */
 321         3,      /* LCD Controller */
 322         0,
 323         0,
 324         0,
 325         0,
 326         0,
 327         0,
 328         0,
 329         0,      /* Advanced Interrupt Controller */
 330         0,      /* Advanced Interrupt Controller */
 331         0,      /* Advanced Interrupt Controller */
 332 };
 333
 334 struct at91_init_soc __initdata at91sam9261_soc = {
 335         .map_io = at91sam9261_map_io,
 336         .default_irq_priority = at91sam9261_default_irq_priority,
 337         .ioremap_registers = at91sam9261_ioremap_registers,
 338         .register_clocks = at91sam9261_register_clocks,
 339         .init = at91sam9261_initialize,
 340 };