2 * arch/arm/mach-at91/at91sam9263.c
4 * Copyright (C) 2007 Atmel Corporation.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
13 #include <linux/module.h>
14 #include <linux/clk/at91_pmc.h>
16 #include <asm/proc-fns.h>
18 #include <asm/mach/arch.h>
19 #include <asm/mach/map.h>
20 #include <asm/system_misc.h>
21 #include <mach/at91sam9263.h>
22 #include <mach/hardware.h>
25 #include "at91_rstc.h"
32 /* --------------------------------------------------------------------
34 * -------------------------------------------------------------------- */
37 * The peripheral clocks.
39 static struct clk pioA_clk = {
41 .pmc_mask = 1 << AT91SAM9263_ID_PIOA,
42 .type = CLK_TYPE_PERIPHERAL,
44 static struct clk pioB_clk = {
46 .pmc_mask = 1 << AT91SAM9263_ID_PIOB,
47 .type = CLK_TYPE_PERIPHERAL,
49 static struct clk pioCDE_clk = {
51 .pmc_mask = 1 << AT91SAM9263_ID_PIOCDE,
52 .type = CLK_TYPE_PERIPHERAL,
54 static struct clk usart0_clk = {
56 .pmc_mask = 1 << AT91SAM9263_ID_US0,
57 .type = CLK_TYPE_PERIPHERAL,
59 static struct clk usart1_clk = {
61 .pmc_mask = 1 << AT91SAM9263_ID_US1,
62 .type = CLK_TYPE_PERIPHERAL,
64 static struct clk usart2_clk = {
66 .pmc_mask = 1 << AT91SAM9263_ID_US2,
67 .type = CLK_TYPE_PERIPHERAL,
69 static struct clk mmc0_clk = {
71 .pmc_mask = 1 << AT91SAM9263_ID_MCI0,
72 .type = CLK_TYPE_PERIPHERAL,
74 static struct clk mmc1_clk = {
76 .pmc_mask = 1 << AT91SAM9263_ID_MCI1,
77 .type = CLK_TYPE_PERIPHERAL,
79 static struct clk can_clk = {
81 .pmc_mask = 1 << AT91SAM9263_ID_CAN,
82 .type = CLK_TYPE_PERIPHERAL,
84 static struct clk twi_clk = {
86 .pmc_mask = 1 << AT91SAM9263_ID_TWI,
87 .type = CLK_TYPE_PERIPHERAL,
89 static struct clk spi0_clk = {
91 .pmc_mask = 1 << AT91SAM9263_ID_SPI0,
92 .type = CLK_TYPE_PERIPHERAL,
94 static struct clk spi1_clk = {
96 .pmc_mask = 1 << AT91SAM9263_ID_SPI1,
97 .type = CLK_TYPE_PERIPHERAL,
99 static struct clk ssc0_clk = {
101 .pmc_mask = 1 << AT91SAM9263_ID_SSC0,
102 .type = CLK_TYPE_PERIPHERAL,
104 static struct clk ssc1_clk = {
106 .pmc_mask = 1 << AT91SAM9263_ID_SSC1,
107 .type = CLK_TYPE_PERIPHERAL,
109 static struct clk ac97_clk = {
111 .pmc_mask = 1 << AT91SAM9263_ID_AC97C,
112 .type = CLK_TYPE_PERIPHERAL,
114 static struct clk tcb_clk = {
116 .pmc_mask = 1 << AT91SAM9263_ID_TCB,
117 .type = CLK_TYPE_PERIPHERAL,
119 static struct clk pwm_clk = {
121 .pmc_mask = 1 << AT91SAM9263_ID_PWMC,
122 .type = CLK_TYPE_PERIPHERAL,
124 static struct clk macb_clk = {
126 .pmc_mask = 1 << AT91SAM9263_ID_EMAC,
127 .type = CLK_TYPE_PERIPHERAL,
129 static struct clk dma_clk = {
131 .pmc_mask = 1 << AT91SAM9263_ID_DMA,
132 .type = CLK_TYPE_PERIPHERAL,
134 static struct clk twodge_clk = {
136 .pmc_mask = 1 << AT91SAM9263_ID_2DGE,
137 .type = CLK_TYPE_PERIPHERAL,
139 static struct clk udc_clk = {
141 .pmc_mask = 1 << AT91SAM9263_ID_UDP,
142 .type = CLK_TYPE_PERIPHERAL,
144 static struct clk isi_clk = {
146 .pmc_mask = 1 << AT91SAM9263_ID_ISI,
147 .type = CLK_TYPE_PERIPHERAL,
149 static struct clk lcdc_clk = {
151 .pmc_mask = 1 << AT91SAM9263_ID_LCDC,
152 .type = CLK_TYPE_PERIPHERAL,
154 static struct clk ohci_clk = {
156 .pmc_mask = 1 << AT91SAM9263_ID_UHP,
157 .type = CLK_TYPE_PERIPHERAL,
160 static struct clk *periph_clocks[] __initdata = {
188 static struct clk_lookup periph_clocks_lookups[] = {
189 /* One additional fake clock for macb_hclk */
190 CLKDEV_CON_ID("hclk", &macb_clk),
191 CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.0", &ssc0_clk),
192 CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.1", &ssc1_clk),
193 CLKDEV_CON_DEV_ID("pclk", "fff98000.ssc", &ssc0_clk),
194 CLKDEV_CON_DEV_ID("pclk", "fff9c000.ssc", &ssc1_clk),
195 CLKDEV_CON_DEV_ID("hclk", "at91sam9263-lcdfb.0", &lcdc_clk),
196 CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.0", &mmc0_clk),
197 CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.1", &mmc1_clk),
198 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
199 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
200 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb_clk),
201 CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9260.0", &twi_clk),
202 /* fake hclk clock */
203 CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
204 CLKDEV_CON_ID("pioA", &pioA_clk),
205 CLKDEV_CON_ID("pioB", &pioB_clk),
206 CLKDEV_CON_ID("pioC", &pioCDE_clk),
207 CLKDEV_CON_ID("pioD", &pioCDE_clk),
208 CLKDEV_CON_ID("pioE", &pioCDE_clk),
209 /* more usart lookup table for DT entries */
210 CLKDEV_CON_DEV_ID("usart", "ffffee00.serial", &mck),
211 CLKDEV_CON_DEV_ID("usart", "fff8c000.serial", &usart0_clk),
212 CLKDEV_CON_DEV_ID("usart", "fff90000.serial", &usart1_clk),
213 CLKDEV_CON_DEV_ID("usart", "fff94000.serial", &usart2_clk),
214 /* more tc lookup table for DT entries */
215 CLKDEV_CON_DEV_ID("t0_clk", "fff7c000.timer", &tcb_clk),
216 CLKDEV_CON_DEV_ID("hclk", "a00000.ohci", &ohci_clk),
217 CLKDEV_CON_DEV_ID("spi_clk", "fffa4000.spi", &spi0_clk),
218 CLKDEV_CON_DEV_ID("spi_clk", "fffa8000.spi", &spi1_clk),
219 CLKDEV_CON_DEV_ID("mci_clk", "fff80000.mmc", &mmc0_clk),
220 CLKDEV_CON_DEV_ID("mci_clk", "fff84000.mmc", &mmc1_clk),
221 CLKDEV_CON_DEV_ID(NULL, "fff88000.i2c", &twi_clk),
222 CLKDEV_CON_DEV_ID(NULL, "fffff200.gpio", &pioA_clk),
223 CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioB_clk),
224 CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioCDE_clk),
225 CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioCDE_clk),
226 CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioCDE_clk),
227 CLKDEV_CON_DEV_ID(NULL, "fffb8000.pwm", &pwm_clk),
230 static struct clk_lookup usart_clocks_lookups[] = {
231 CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
232 CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
233 CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
234 CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
238 * The four programmable clocks.
239 * You must configure pin multiplexing to bring these signals out.
241 static struct clk pck0 = {
243 .pmc_mask = AT91_PMC_PCK0,
244 .type = CLK_TYPE_PROGRAMMABLE,
247 static struct clk pck1 = {
249 .pmc_mask = AT91_PMC_PCK1,
250 .type = CLK_TYPE_PROGRAMMABLE,
253 static struct clk pck2 = {
255 .pmc_mask = AT91_PMC_PCK2,
256 .type = CLK_TYPE_PROGRAMMABLE,
259 static struct clk pck3 = {
261 .pmc_mask = AT91_PMC_PCK3,
262 .type = CLK_TYPE_PROGRAMMABLE,
266 static void __init at91sam9263_register_clocks(void)
270 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
271 clk_register(periph_clocks[i]);
273 clkdev_add_table(periph_clocks_lookups,
274 ARRAY_SIZE(periph_clocks_lookups));
275 clkdev_add_table(usart_clocks_lookups,
276 ARRAY_SIZE(usart_clocks_lookups));
284 /* --------------------------------------------------------------------
286 * -------------------------------------------------------------------- */
288 static struct at91_gpio_bank at91sam9263_gpio[] __initdata = {
290 .id = AT91SAM9263_ID_PIOA,
291 .regbase = AT91SAM9263_BASE_PIOA,
293 .id = AT91SAM9263_ID_PIOB,
294 .regbase = AT91SAM9263_BASE_PIOB,
296 .id = AT91SAM9263_ID_PIOCDE,
297 .regbase = AT91SAM9263_BASE_PIOC,
299 .id = AT91SAM9263_ID_PIOCDE,
300 .regbase = AT91SAM9263_BASE_PIOD,
302 .id = AT91SAM9263_ID_PIOCDE,
303 .regbase = AT91SAM9263_BASE_PIOE,
307 /* --------------------------------------------------------------------
308 * AT91SAM9263 processor initialization
309 * -------------------------------------------------------------------- */
311 static void __init at91sam9263_map_io(void)
313 at91_init_sram(0, AT91SAM9263_SRAM0_BASE, AT91SAM9263_SRAM0_SIZE);
314 at91_init_sram(1, AT91SAM9263_SRAM1_BASE, AT91SAM9263_SRAM1_SIZE);
317 static void __init at91sam9263_ioremap_registers(void)
319 at91_ioremap_shdwc(AT91SAM9263_BASE_SHDWC);
320 at91_ioremap_rstc(AT91SAM9263_BASE_RSTC);
321 at91_ioremap_ramc(0, AT91SAM9263_BASE_SDRAMC0, 512);
322 at91_ioremap_ramc(1, AT91SAM9263_BASE_SDRAMC1, 512);
323 at91sam926x_ioremap_pit(AT91SAM9263_BASE_PIT);
324 at91sam9_ioremap_smc(0, AT91SAM9263_BASE_SMC0);
325 at91sam9_ioremap_smc(1, AT91SAM9263_BASE_SMC1);
326 at91_ioremap_matrix(AT91SAM9263_BASE_MATRIX);
327 at91_pm_set_standby(at91sam9_sdram_standby);
330 static void __init at91sam9263_initialize(void)
332 arm_pm_idle = at91sam9_idle;
333 arm_pm_restart = at91sam9_alt_restart;
335 at91_sysirq_mask_rtt(AT91SAM9263_BASE_RTT0);
336 at91_sysirq_mask_rtt(AT91SAM9263_BASE_RTT1);
338 /* Register GPIO subsystem */
339 at91_gpio_init(at91sam9263_gpio, 5);
342 /* --------------------------------------------------------------------
343 * Interrupt initialization
344 * -------------------------------------------------------------------- */
347 * The default interrupt priority levels (0 = lowest, 7 = highest).
349 static unsigned int at91sam9263_default_irq_priority[NR_AIC_IRQS] __initdata = {
350 7, /* Advanced Interrupt Controller (FIQ) */
351 7, /* System Peripherals */
352 1, /* Parallel IO Controller A */
353 1, /* Parallel IO Controller B */
354 1, /* Parallel IO Controller C, D and E */
360 0, /* Multimedia Card Interface 0 */
361 0, /* Multimedia Card Interface 1 */
363 6, /* Two-Wire Interface */
364 5, /* Serial Peripheral Interface 0 */
365 5, /* Serial Peripheral Interface 1 */
366 4, /* Serial Synchronous Controller 0 */
367 4, /* Serial Synchronous Controller 1 */
368 5, /* AC97 Controller */
369 0, /* Timer Counter 0, 1 and 2 */
370 0, /* Pulse Width Modulation Controller */
373 0, /* 2D Graphic Engine */
374 2, /* USB Device Port */
375 0, /* Image Sensor Interface */
376 3, /* LDC Controller */
377 0, /* DMA Controller */
379 2, /* USB Host port */
380 0, /* Advanced Interrupt Controller (IRQ0) */
381 0, /* Advanced Interrupt Controller (IRQ1) */
384 AT91_SOC_START(at91sam9263)
385 .map_io = at91sam9263_map_io,
386 .default_irq_priority = at91sam9263_default_irq_priority,
387 .extern_irq = (1 << AT91SAM9263_ID_IRQ0) | (1 << AT91SAM9263_ID_IRQ1),
388 .ioremap_registers = at91sam9263_ioremap_registers,
389 .register_clocks = at91sam9263_register_clocks,
390 .init = at91sam9263_initialize,