arch/arm/mach-at91/at91sam9263.c

   1 /*
   2  * arch/arm/mach-at91/at91sam9263.c
   3  *
   4  *  Copyright (C) 2007 Atmel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  */
  12
  13 #include <linux/module.h>
  14 #include <linux/pm.h>
  15
  16 #include <asm/irq.h>
  17 #include <asm/mach/arch.h>
  18 #include <asm/mach/map.h>
  19 #include <mach/at91sam9263.h>
  20 #include <mach/at91_pmc.h>
  21 #include <mach/at91_rstc.h>
  22 #include <mach/at91_shdwc.h>
  23
  24 #include "soc.h"
  25 #include "generic.h"
  26 #include "clock.h"
  27
  28 /* --------------------------------------------------------------------
  29  *  Clocks
  30  * -------------------------------------------------------------------- */
  31
  32 /*
  33  * The peripheral clocks.
  34  */
  35 static struct clk pioA_clk = {
  36         .name           = "pioA_clk",
  37         .pmc_mask       = 1 << AT91SAM9263_ID_PIOA,
  38         .type           = CLK_TYPE_PERIPHERAL,
  39 };
  40 static struct clk pioB_clk = {
  41         .name           = "pioB_clk",
  42         .pmc_mask       = 1 << AT91SAM9263_ID_PIOB,
  43         .type           = CLK_TYPE_PERIPHERAL,
  44 };
  45 static struct clk pioCDE_clk = {
  46         .name           = "pioCDE_clk",
  47         .pmc_mask       = 1 << AT91SAM9263_ID_PIOCDE,
  48         .type           = CLK_TYPE_PERIPHERAL,
  49 };
  50 static struct clk usart0_clk = {
  51         .name           = "usart0_clk",
  52         .pmc_mask       = 1 << AT91SAM9263_ID_US0,
  53         .type           = CLK_TYPE_PERIPHERAL,
  54 };
  55 static struct clk usart1_clk = {
  56         .name           = "usart1_clk",
  57         .pmc_mask       = 1 << AT91SAM9263_ID_US1,
  58         .type           = CLK_TYPE_PERIPHERAL,
  59 };
  60 static struct clk usart2_clk = {
  61         .name           = "usart2_clk",
  62         .pmc_mask       = 1 << AT91SAM9263_ID_US2,
  63         .type           = CLK_TYPE_PERIPHERAL,
  64 };
  65 static struct clk mmc0_clk = {
  66         .name           = "mci0_clk",
  67         .pmc_mask       = 1 << AT91SAM9263_ID_MCI0,
  68         .type           = CLK_TYPE_PERIPHERAL,
  69 };
  70 static struct clk mmc1_clk = {
  71         .name           = "mci1_clk",
  72         .pmc_mask       = 1 << AT91SAM9263_ID_MCI1,
  73         .type           = CLK_TYPE_PERIPHERAL,
  74 };
  75 static struct clk can_clk = {
  76         .name           = "can_clk",
  77         .pmc_mask       = 1 << AT91SAM9263_ID_CAN,
  78         .type           = CLK_TYPE_PERIPHERAL,
  79 };
  80 static struct clk twi_clk = {
  81         .name           = "twi_clk",
  82         .pmc_mask       = 1 << AT91SAM9263_ID_TWI,
  83         .type           = CLK_TYPE_PERIPHERAL,
  84 };
  85 static struct clk spi0_clk = {
  86         .name           = "spi0_clk",
  87         .pmc_mask       = 1 << AT91SAM9263_ID_SPI0,
  88         .type           = CLK_TYPE_PERIPHERAL,
  89 };
  90 static struct clk spi1_clk = {
  91         .name           = "spi1_clk",
  92         .pmc_mask       = 1 << AT91SAM9263_ID_SPI1,
  93         .type           = CLK_TYPE_PERIPHERAL,
  94 };
  95 static struct clk ssc0_clk = {
  96         .name           = "ssc0_clk",
  97         .pmc_mask       = 1 << AT91SAM9263_ID_SSC0,
  98         .type           = CLK_TYPE_PERIPHERAL,
  99 };
 100 static struct clk ssc1_clk = {
 101         .name           = "ssc1_clk",
 102         .pmc_mask       = 1 << AT91SAM9263_ID_SSC1,
 103         .type           = CLK_TYPE_PERIPHERAL,
 104 };
 105 static struct clk ac97_clk = {
 106         .name           = "ac97_clk",
 107         .pmc_mask       = 1 << AT91SAM9263_ID_AC97C,
 108         .type           = CLK_TYPE_PERIPHERAL,
 109 };
 110 static struct clk tcb_clk = {
 111         .name           = "tcb_clk",
 112         .pmc_mask       = 1 << AT91SAM9263_ID_TCB,
 113         .type           = CLK_TYPE_PERIPHERAL,
 114 };
 115 static struct clk pwm_clk = {
 116         .name           = "pwm_clk",
 117         .pmc_mask       = 1 << AT91SAM9263_ID_PWMC,
 118         .type           = CLK_TYPE_PERIPHERAL,
 119 };
 120 static struct clk macb_clk = {
 121         .name           = "pclk",
 122         .pmc_mask       = 1 << AT91SAM9263_ID_EMAC,
 123         .type           = CLK_TYPE_PERIPHERAL,
 124 };
 125 static struct clk dma_clk = {
 126         .name           = "dma_clk",
 127         .pmc_mask       = 1 << AT91SAM9263_ID_DMA,
 128         .type           = CLK_TYPE_PERIPHERAL,
 129 };
 130 static struct clk twodge_clk = {
 131         .name           = "2dge_clk",
 132         .pmc_mask       = 1 << AT91SAM9263_ID_2DGE,
 133         .type           = CLK_TYPE_PERIPHERAL,
 134 };
 135 static struct clk udc_clk = {
 136         .name           = "udc_clk",
 137         .pmc_mask       = 1 << AT91SAM9263_ID_UDP,
 138         .type           = CLK_TYPE_PERIPHERAL,
 139 };
 140 static struct clk isi_clk = {
 141         .name           = "isi_clk",
 142         .pmc_mask       = 1 << AT91SAM9263_ID_ISI,
 143         .type           = CLK_TYPE_PERIPHERAL,
 144 };
 145 static struct clk lcdc_clk = {
 146         .name           = "lcdc_clk",
 147         .pmc_mask       = 1 << AT91SAM9263_ID_LCDC,
 148         .type           = CLK_TYPE_PERIPHERAL,
 149 };
 150 static struct clk ohci_clk = {
 151         .name           = "ohci_clk",
 152         .pmc_mask       = 1 << AT91SAM9263_ID_UHP,
 153         .type           = CLK_TYPE_PERIPHERAL,
 154 };
 155
 156 static struct clk *periph_clocks[] __initdata = {
 157         &pioA_clk,
 158         &pioB_clk,
 159         &pioCDE_clk,
 160         &usart0_clk,
 161         &usart1_clk,
 162         &usart2_clk,
 163         &mmc0_clk,
 164         &mmc1_clk,
 165         &can_clk,
 166         &twi_clk,
 167         &spi0_clk,
 168         &spi1_clk,
 169         &ssc0_clk,
 170         &ssc1_clk,
 171         &ac97_clk,
 172         &tcb_clk,
 173         &pwm_clk,
 174         &macb_clk,
 175         &twodge_clk,
 176         &udc_clk,
 177         &isi_clk,
 178         &lcdc_clk,
 179         &dma_clk,
 180         &ohci_clk,
 181         // irq0 .. irq1
 182 };
 183
 184 static struct clk_lookup periph_clocks_lookups[] = {
 185         /* One additional fake clock for macb_hclk */
 186         CLKDEV_CON_ID("hclk", &macb_clk),
 187         CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
 188         CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
 189         CLKDEV_CON_DEV_ID("mci_clk", "at91_mci.0", &mmc0_clk),
 190         CLKDEV_CON_DEV_ID("mci_clk", "at91_mci.1", &mmc1_clk),
 191         CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
 192         CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
 193         CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb_clk),
 194         /* fake hclk clock */
 195         CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
 196 };
 197
 198 static struct clk_lookup usart_clocks_lookups[] = {
 199         CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
 200         CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
 201         CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
 202         CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
 203 };
 204
 205 /*
 206  * The four programmable clocks.
 207  * You must configure pin multiplexing to bring these signals out.
 208  */
 209 static struct clk pck0 = {
 210         .name           = "pck0",
 211         .pmc_mask       = AT91_PMC_PCK0,
 212         .type           = CLK_TYPE_PROGRAMMABLE,
 213         .id             = 0,
 214 };
 215 static struct clk pck1 = {
 216         .name           = "pck1",
 217         .pmc_mask       = AT91_PMC_PCK1,
 218         .type           = CLK_TYPE_PROGRAMMABLE,
 219         .id             = 1,
 220 };
 221 static struct clk pck2 = {
 222         .name           = "pck2",
 223         .pmc_mask       = AT91_PMC_PCK2,
 224         .type           = CLK_TYPE_PROGRAMMABLE,
 225         .id             = 2,
 226 };
 227 static struct clk pck3 = {
 228         .name           = "pck3",
 229         .pmc_mask       = AT91_PMC_PCK3,
 230         .type           = CLK_TYPE_PROGRAMMABLE,
 231         .id             = 3,
 232 };
 233
 234 static void __init at91sam9263_register_clocks(void)
 235 {
 236         int i;
 237
 238         for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
 239                 clk_register(periph_clocks[i]);
 240
 241         clkdev_add_table(periph_clocks_lookups,
 242                          ARRAY_SIZE(periph_clocks_lookups));
 243         clkdev_add_table(usart_clocks_lookups,
 244                          ARRAY_SIZE(usart_clocks_lookups));
 245
 246         clk_register(&pck0);
 247         clk_register(&pck1);
 248         clk_register(&pck2);
 249         clk_register(&pck3);
 250 }
 251
 252 static struct clk_lookup console_clock_lookup;
 253
 254 void __init at91sam9263_set_console_clock(int id)
 255 {
 256         if (id >= ARRAY_SIZE(usart_clocks_lookups))
 257                 return;
 258
 259         console_clock_lookup.con_id = "usart";
 260         console_clock_lookup.clk = usart_clocks_lookups[id].clk;
 261         clkdev_add(&console_clock_lookup);
 262 }
 263
 264 /* --------------------------------------------------------------------
 265  *  GPIO
 266  * -------------------------------------------------------------------- */
 267
 268 static struct at91_gpio_bank at91sam9263_gpio[] = {
 269         {
 270                 .id             = AT91SAM9263_ID_PIOA,
 271                 .offset         = AT91_PIOA,
 272                 .clock          = &pioA_clk,
 273         }, {
 274                 .id             = AT91SAM9263_ID_PIOB,
 275                 .offset         = AT91_PIOB,
 276                 .clock          = &pioB_clk,
 277         }, {
 278                 .id             = AT91SAM9263_ID_PIOCDE,
 279                 .offset         = AT91_PIOC,
 280                 .clock          = &pioCDE_clk,
 281         }, {
 282                 .id             = AT91SAM9263_ID_PIOCDE,
 283                 .offset         = AT91_PIOD,
 284                 .clock          = &pioCDE_clk,
 285         }, {
 286                 .id             = AT91SAM9263_ID_PIOCDE,
 287                 .offset         = AT91_PIOE,
 288                 .clock          = &pioCDE_clk,
 289         }
 290 };
 291
 292 static void at91sam9263_poweroff(void)
 293 {
 294         at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
 295 }
 296
 297
 298 /* --------------------------------------------------------------------
 299  *  AT91SAM9263 processor initialization
 300  * -------------------------------------------------------------------- */
 301
 302 static void __init at91sam9263_map_io(void)
 303 {
 304         at91_init_sram(0, AT91SAM9263_SRAM0_BASE, AT91SAM9263_SRAM0_SIZE);
 305         at91_init_sram(1, AT91SAM9263_SRAM1_BASE, AT91SAM9263_SRAM1_SIZE);
 306 }
 307
 308 static void __init at91sam9263_initialize(void)
 309 {
 310         at91_arch_reset = at91sam9_alt_reset;
 311         pm_power_off = at91sam9263_poweroff;
 312         at91_extern_irq = (1 << AT91SAM9263_ID_IRQ0) | (1 << AT91SAM9263_ID_IRQ1);
 313
 314         /* Register GPIO subsystem */
 315         at91_gpio_init(at91sam9263_gpio, 5);
 316 }
 317
 318 /* --------------------------------------------------------------------
 319  *  Interrupt initialization
 320  * -------------------------------------------------------------------- */
 321
 322 /*
 323  * The default interrupt priority levels (0 = lowest, 7 = highest).
 324  */
 325 static unsigned int at91sam9263_default_irq_priority[NR_AIC_IRQS] __initdata = {
 326         7,      /* Advanced Interrupt Controller (FIQ) */
 327         7,      /* System Peripherals */
 328         1,      /* Parallel IO Controller A */
 329         1,      /* Parallel IO Controller B */
 330         1,      /* Parallel IO Controller C, D and E */
 331         0,
 332         0,
 333         5,      /* USART 0 */
 334         5,      /* USART 1 */
 335         5,      /* USART 2 */
 336         0,      /* Multimedia Card Interface 0 */
 337         0,      /* Multimedia Card Interface 1 */
 338         3,      /* CAN */
 339         6,      /* Two-Wire Interface */
 340         5,      /* Serial Peripheral Interface 0 */
 341         5,      /* Serial Peripheral Interface 1 */
 342         4,      /* Serial Synchronous Controller 0 */
 343         4,      /* Serial Synchronous Controller 1 */
 344         5,      /* AC97 Controller */
 345         0,      /* Timer Counter 0, 1 and 2 */
 346         0,      /* Pulse Width Modulation Controller */
 347         3,      /* Ethernet */
 348         0,
 349         0,      /* 2D Graphic Engine */
 350         2,      /* USB Device Port */
 351         0,      /* Image Sensor Interface */
 352         3,      /* LDC Controller */
 353         0,      /* DMA Controller */
 354         0,
 355         2,      /* USB Host port */
 356         0,      /* Advanced Interrupt Controller (IRQ0) */
 357         0,      /* Advanced Interrupt Controller (IRQ1) */
 358 };
 359
 360 struct at91_init_soc __initdata at91sam9263_soc = {
 361         .map_io = at91sam9263_map_io,
 362         .default_irq_priority = at91sam9263_default_irq_priority,
 363         .register_clocks = at91sam9263_register_clocks,
 364         .init = at91sam9263_initialize,
 365 };