2 * arch/arm/mach-at91/at91sam9263.c
4 * Copyright (C) 2007 Atmel Corporation.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
13 #include <linux/module.h>
14 #include <linux/clk/at91_pmc.h>
16 #include <asm/proc-fns.h>
18 #include <asm/mach/arch.h>
19 #include <asm/mach/map.h>
20 #include <asm/system_misc.h>
21 #include <mach/at91sam9263.h>
22 #include <mach/hardware.h>
25 #include "at91_rstc.h"
31 #if defined(CONFIG_OLD_CLK_AT91)
33 /* --------------------------------------------------------------------
35 * -------------------------------------------------------------------- */
38 * The peripheral clocks.
40 static struct clk pioA_clk = {
42 .pmc_mask = 1 << AT91SAM9263_ID_PIOA,
43 .type = CLK_TYPE_PERIPHERAL,
45 static struct clk pioB_clk = {
47 .pmc_mask = 1 << AT91SAM9263_ID_PIOB,
48 .type = CLK_TYPE_PERIPHERAL,
50 static struct clk pioCDE_clk = {
52 .pmc_mask = 1 << AT91SAM9263_ID_PIOCDE,
53 .type = CLK_TYPE_PERIPHERAL,
55 static struct clk usart0_clk = {
57 .pmc_mask = 1 << AT91SAM9263_ID_US0,
58 .type = CLK_TYPE_PERIPHERAL,
60 static struct clk usart1_clk = {
62 .pmc_mask = 1 << AT91SAM9263_ID_US1,
63 .type = CLK_TYPE_PERIPHERAL,
65 static struct clk usart2_clk = {
67 .pmc_mask = 1 << AT91SAM9263_ID_US2,
68 .type = CLK_TYPE_PERIPHERAL,
70 static struct clk mmc0_clk = {
72 .pmc_mask = 1 << AT91SAM9263_ID_MCI0,
73 .type = CLK_TYPE_PERIPHERAL,
75 static struct clk mmc1_clk = {
77 .pmc_mask = 1 << AT91SAM9263_ID_MCI1,
78 .type = CLK_TYPE_PERIPHERAL,
80 static struct clk can_clk = {
82 .pmc_mask = 1 << AT91SAM9263_ID_CAN,
83 .type = CLK_TYPE_PERIPHERAL,
85 static struct clk twi_clk = {
87 .pmc_mask = 1 << AT91SAM9263_ID_TWI,
88 .type = CLK_TYPE_PERIPHERAL,
90 static struct clk spi0_clk = {
92 .pmc_mask = 1 << AT91SAM9263_ID_SPI0,
93 .type = CLK_TYPE_PERIPHERAL,
95 static struct clk spi1_clk = {
97 .pmc_mask = 1 << AT91SAM9263_ID_SPI1,
98 .type = CLK_TYPE_PERIPHERAL,
100 static struct clk ssc0_clk = {
102 .pmc_mask = 1 << AT91SAM9263_ID_SSC0,
103 .type = CLK_TYPE_PERIPHERAL,
105 static struct clk ssc1_clk = {
107 .pmc_mask = 1 << AT91SAM9263_ID_SSC1,
108 .type = CLK_TYPE_PERIPHERAL,
110 static struct clk ac97_clk = {
112 .pmc_mask = 1 << AT91SAM9263_ID_AC97C,
113 .type = CLK_TYPE_PERIPHERAL,
115 static struct clk tcb_clk = {
117 .pmc_mask = 1 << AT91SAM9263_ID_TCB,
118 .type = CLK_TYPE_PERIPHERAL,
120 static struct clk pwm_clk = {
122 .pmc_mask = 1 << AT91SAM9263_ID_PWMC,
123 .type = CLK_TYPE_PERIPHERAL,
125 static struct clk macb_clk = {
127 .pmc_mask = 1 << AT91SAM9263_ID_EMAC,
128 .type = CLK_TYPE_PERIPHERAL,
130 static struct clk dma_clk = {
132 .pmc_mask = 1 << AT91SAM9263_ID_DMA,
133 .type = CLK_TYPE_PERIPHERAL,
135 static struct clk twodge_clk = {
137 .pmc_mask = 1 << AT91SAM9263_ID_2DGE,
138 .type = CLK_TYPE_PERIPHERAL,
140 static struct clk udc_clk = {
142 .pmc_mask = 1 << AT91SAM9263_ID_UDP,
143 .type = CLK_TYPE_PERIPHERAL,
145 static struct clk isi_clk = {
147 .pmc_mask = 1 << AT91SAM9263_ID_ISI,
148 .type = CLK_TYPE_PERIPHERAL,
150 static struct clk lcdc_clk = {
152 .pmc_mask = 1 << AT91SAM9263_ID_LCDC,
153 .type = CLK_TYPE_PERIPHERAL,
155 static struct clk ohci_clk = {
157 .pmc_mask = 1 << AT91SAM9263_ID_UHP,
158 .type = CLK_TYPE_PERIPHERAL,
161 static struct clk *periph_clocks[] __initdata = {
189 static struct clk_lookup periph_clocks_lookups[] = {
190 /* One additional fake clock for macb_hclk */
191 CLKDEV_CON_ID("hclk", &macb_clk),
192 CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.0", &ssc0_clk),
193 CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.1", &ssc1_clk),
194 CLKDEV_CON_DEV_ID("pclk", "fff98000.ssc", &ssc0_clk),
195 CLKDEV_CON_DEV_ID("pclk", "fff9c000.ssc", &ssc1_clk),
196 CLKDEV_CON_DEV_ID("hclk", "at91sam9263-lcdfb.0", &lcdc_clk),
197 CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.0", &mmc0_clk),
198 CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.1", &mmc1_clk),
199 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
200 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
201 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb_clk),
202 CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9260.0", &twi_clk),
203 CLKDEV_CON_DEV_ID(NULL, "at91sam9rl-pwm", &pwm_clk),
204 /* fake hclk clock */
205 CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
206 CLKDEV_CON_ID("pioA", &pioA_clk),
207 CLKDEV_CON_ID("pioB", &pioB_clk),
208 CLKDEV_CON_ID("pioC", &pioCDE_clk),
209 CLKDEV_CON_ID("pioD", &pioCDE_clk),
210 CLKDEV_CON_ID("pioE", &pioCDE_clk),
211 /* more usart lookup table for DT entries */
212 CLKDEV_CON_DEV_ID("usart", "ffffee00.serial", &mck),
213 CLKDEV_CON_DEV_ID("usart", "fff8c000.serial", &usart0_clk),
214 CLKDEV_CON_DEV_ID("usart", "fff90000.serial", &usart1_clk),
215 CLKDEV_CON_DEV_ID("usart", "fff94000.serial", &usart2_clk),
216 /* more tc lookup table for DT entries */
217 CLKDEV_CON_DEV_ID("t0_clk", "fff7c000.timer", &tcb_clk),
218 CLKDEV_CON_DEV_ID("hclk", "a00000.ohci", &ohci_clk),
219 CLKDEV_CON_DEV_ID("spi_clk", "fffa4000.spi", &spi0_clk),
220 CLKDEV_CON_DEV_ID("spi_clk", "fffa8000.spi", &spi1_clk),
221 CLKDEV_CON_DEV_ID("mci_clk", "fff80000.mmc", &mmc0_clk),
222 CLKDEV_CON_DEV_ID("mci_clk", "fff84000.mmc", &mmc1_clk),
223 CLKDEV_CON_DEV_ID(NULL, "fff88000.i2c", &twi_clk),
224 CLKDEV_CON_DEV_ID(NULL, "fffff200.gpio", &pioA_clk),
225 CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioB_clk),
226 CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioCDE_clk),
227 CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioCDE_clk),
228 CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioCDE_clk),
229 CLKDEV_CON_DEV_ID(NULL, "fffb8000.pwm", &pwm_clk),
232 static struct clk_lookup usart_clocks_lookups[] = {
233 CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
234 CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
235 CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
236 CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
240 * The four programmable clocks.
241 * You must configure pin multiplexing to bring these signals out.
243 static struct clk pck0 = {
245 .pmc_mask = AT91_PMC_PCK0,
246 .type = CLK_TYPE_PROGRAMMABLE,
249 static struct clk pck1 = {
251 .pmc_mask = AT91_PMC_PCK1,
252 .type = CLK_TYPE_PROGRAMMABLE,
255 static struct clk pck2 = {
257 .pmc_mask = AT91_PMC_PCK2,
258 .type = CLK_TYPE_PROGRAMMABLE,
261 static struct clk pck3 = {
263 .pmc_mask = AT91_PMC_PCK3,
264 .type = CLK_TYPE_PROGRAMMABLE,
268 static void __init at91sam9263_register_clocks(void)
272 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
273 clk_register(periph_clocks[i]);
275 clkdev_add_table(periph_clocks_lookups,
276 ARRAY_SIZE(periph_clocks_lookups));
277 clkdev_add_table(usart_clocks_lookups,
278 ARRAY_SIZE(usart_clocks_lookups));
286 #define at91sam9263_register_clocks NULL
289 /* --------------------------------------------------------------------
291 * -------------------------------------------------------------------- */
293 static struct at91_gpio_bank at91sam9263_gpio[] __initdata = {
295 .id = AT91SAM9263_ID_PIOA,
296 .regbase = AT91SAM9263_BASE_PIOA,
298 .id = AT91SAM9263_ID_PIOB,
299 .regbase = AT91SAM9263_BASE_PIOB,
301 .id = AT91SAM9263_ID_PIOCDE,
302 .regbase = AT91SAM9263_BASE_PIOC,
304 .id = AT91SAM9263_ID_PIOCDE,
305 .regbase = AT91SAM9263_BASE_PIOD,
307 .id = AT91SAM9263_ID_PIOCDE,
308 .regbase = AT91SAM9263_BASE_PIOE,
312 /* --------------------------------------------------------------------
313 * AT91SAM9263 processor initialization
314 * -------------------------------------------------------------------- */
316 static void __init at91sam9263_map_io(void)
318 at91_init_sram(0, AT91SAM9263_SRAM0_BASE, AT91SAM9263_SRAM0_SIZE);
319 at91_init_sram(1, AT91SAM9263_SRAM1_BASE, AT91SAM9263_SRAM1_SIZE);
322 static void __init at91sam9263_ioremap_registers(void)
324 at91_ioremap_shdwc(AT91SAM9263_BASE_SHDWC);
325 at91_ioremap_rstc(AT91SAM9263_BASE_RSTC);
326 at91_ioremap_ramc(0, AT91SAM9263_BASE_SDRAMC0, 512);
327 at91_ioremap_ramc(1, AT91SAM9263_BASE_SDRAMC1, 512);
328 at91sam926x_ioremap_pit(AT91SAM9263_BASE_PIT);
329 at91sam9_ioremap_smc(0, AT91SAM9263_BASE_SMC0);
330 at91sam9_ioremap_smc(1, AT91SAM9263_BASE_SMC1);
331 at91_ioremap_matrix(AT91SAM9263_BASE_MATRIX);
332 at91_pm_set_standby(at91sam9_sdram_standby);
335 static void __init at91sam9263_initialize(void)
337 arm_pm_idle = at91sam9_idle;
338 arm_pm_restart = at91sam9_alt_restart;
340 at91_sysirq_mask_rtt(AT91SAM9263_BASE_RTT0);
341 at91_sysirq_mask_rtt(AT91SAM9263_BASE_RTT1);
343 /* Register GPIO subsystem */
344 at91_gpio_init(at91sam9263_gpio, 5);
347 /* --------------------------------------------------------------------
348 * Interrupt initialization
349 * -------------------------------------------------------------------- */
352 * The default interrupt priority levels (0 = lowest, 7 = highest).
354 static unsigned int at91sam9263_default_irq_priority[NR_AIC_IRQS] __initdata = {
355 7, /* Advanced Interrupt Controller (FIQ) */
356 7, /* System Peripherals */
357 1, /* Parallel IO Controller A */
358 1, /* Parallel IO Controller B */
359 1, /* Parallel IO Controller C, D and E */
365 0, /* Multimedia Card Interface 0 */
366 0, /* Multimedia Card Interface 1 */
368 6, /* Two-Wire Interface */
369 5, /* Serial Peripheral Interface 0 */
370 5, /* Serial Peripheral Interface 1 */
371 4, /* Serial Synchronous Controller 0 */
372 4, /* Serial Synchronous Controller 1 */
373 5, /* AC97 Controller */
374 0, /* Timer Counter 0, 1 and 2 */
375 0, /* Pulse Width Modulation Controller */
378 0, /* 2D Graphic Engine */
379 2, /* USB Device Port */
380 0, /* Image Sensor Interface */
381 3, /* LDC Controller */
382 0, /* DMA Controller */
384 2, /* USB Host port */
385 0, /* Advanced Interrupt Controller (IRQ0) */
386 0, /* Advanced Interrupt Controller (IRQ1) */
389 AT91_SOC_START(at91sam9263)
390 .map_io = at91sam9263_map_io,
391 .default_irq_priority = at91sam9263_default_irq_priority,
392 .extern_irq = (1 << AT91SAM9263_ID_IRQ0) | (1 << AT91SAM9263_ID_IRQ1),
393 .ioremap_registers = at91sam9263_ioremap_registers,
394 .register_clocks = at91sam9263_register_clocks,
395 .init = at91sam9263_initialize,