2 * at91sam926x_time.c - Periodic Interval Timer (PIT) for at91sam926x
4 * Copyright (C) 2005-2006 M. Amine SAYA, ATMEL Rousset, France
5 * Revision 2005 M. Nicolas Diremdjian, ATMEL Rousset, France
6 * Converted to ClockSource/ClockEvents by David Brownell.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 #include <linux/interrupt.h>
13 #include <linux/irq.h>
14 #include <linux/kernel.h>
15 #include <linux/clk.h>
16 #include <linux/clockchips.h>
18 #include <linux/of_address.h>
19 #include <linux/of_irq.h>
21 #include <asm/mach/time.h>
22 #include <mach/hardware.h>
24 #define AT91_PIT_MR 0x00 /* Mode Register */
25 #define AT91_PIT_PITIEN (1 << 25) /* Timer Interrupt Enable */
26 #define AT91_PIT_PITEN (1 << 24) /* Timer Enabled */
27 #define AT91_PIT_PIV (0xfffff) /* Periodic Interval Value */
29 #define AT91_PIT_SR 0x04 /* Status Register */
30 #define AT91_PIT_PITS (1 << 0) /* Timer Status */
32 #define AT91_PIT_PIVR 0x08 /* Periodic Interval Value Register */
33 #define AT91_PIT_PIIR 0x0c /* Periodic Interval Image Register */
34 #define AT91_PIT_PICNT (0xfff << 20) /* Interval Counter */
35 #define AT91_PIT_CPIV (0xfffff) /* Inverval Value */
37 #define PIT_CPIV(x) ((x) & AT91_PIT_CPIV)
38 #define PIT_PICNT(x) (((x) & AT91_PIT_PICNT) >> 20)
40 static u32 pit_cycle; /* write-once */
41 static u32 pit_cnt; /* access only w/system irq blocked */
42 static void __iomem *pit_base_addr __read_mostly;
43 static struct clk *mck;
45 static inline unsigned int pit_read(unsigned int reg_offset)
47 return __raw_readl(pit_base_addr + reg_offset);
50 static inline void pit_write(unsigned int reg_offset, unsigned long value)
52 __raw_writel(value, pit_base_addr + reg_offset);
56 * Clocksource: just a monotonic counter of MCK/16 cycles.
57 * We don't care whether or not PIT irqs are enabled.
59 static cycle_t read_pit_clk(struct clocksource *cs)
65 raw_local_irq_save(flags);
67 t = pit_read(AT91_PIT_PIIR);
68 raw_local_irq_restore(flags);
70 elapsed += PIT_PICNT(t) * pit_cycle;
71 elapsed += PIT_CPIV(t);
75 static struct clocksource pit_clk = {
79 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
84 * Clockevent device: interrupts every 1/HZ (== pit_cycles * MCK/16)
87 pit_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev)
90 case CLOCK_EVT_MODE_PERIODIC:
91 /* update clocksource counter */
92 pit_cnt += pit_cycle * PIT_PICNT(pit_read(AT91_PIT_PIVR));
93 pit_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN
96 case CLOCK_EVT_MODE_ONESHOT:
99 case CLOCK_EVT_MODE_SHUTDOWN:
100 case CLOCK_EVT_MODE_UNUSED:
101 /* disable irq, leaving the clocksource active */
102 pit_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN);
104 case CLOCK_EVT_MODE_RESUME:
109 static void at91sam926x_pit_suspend(struct clock_event_device *cedev)
112 pit_write(AT91_PIT_MR, 0);
115 static void at91sam926x_pit_reset(void)
117 /* Disable timer and irqs */
118 pit_write(AT91_PIT_MR, 0);
120 /* Clear any pending interrupts, wait for PIT to stop counting */
121 while (PIT_CPIV(pit_read(AT91_PIT_PIVR)) != 0)
124 /* Start PIT but don't enable IRQ */
125 pit_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN);
128 static void at91sam926x_pit_resume(struct clock_event_device *cedev)
130 at91sam926x_pit_reset();
133 static struct clock_event_device pit_clkevt = {
135 .features = CLOCK_EVT_FEAT_PERIODIC,
138 .set_mode = pit_clkevt_mode,
139 .suspend = at91sam926x_pit_suspend,
140 .resume = at91sam926x_pit_resume,
145 * IRQ handler for the timer.
147 static irqreturn_t at91sam926x_pit_interrupt(int irq, void *dev_id)
150 * irqs should be disabled here, but as the irq is shared they are only
151 * guaranteed to be off if the timer irq is registered first.
153 WARN_ON_ONCE(!irqs_disabled());
155 /* The PIT interrupt may be disabled, and is shared */
156 if ((pit_clkevt.mode == CLOCK_EVT_MODE_PERIODIC)
157 && (pit_read(AT91_PIT_SR) & AT91_PIT_PITS)) {
160 /* Get number of ticks performed before irq, and ack it */
161 nr_ticks = PIT_PICNT(pit_read(AT91_PIT_PIVR));
163 pit_cnt += pit_cycle;
164 pit_clkevt.event_handler(&pit_clkevt);
174 static struct irqaction at91sam926x_pit_irq = {
176 .flags = IRQF_SHARED | IRQF_TIMER | IRQF_IRQPOLL,
177 .handler = at91sam926x_pit_interrupt,
178 .irq = NR_IRQS_LEGACY + AT91_ID_SYS,
182 static struct of_device_id pit_timer_ids[] = {
183 { .compatible = "atmel,at91sam9260-pit" },
187 static int __init of_at91sam926x_pit_init(void)
189 struct device_node *np;
192 np = of_find_matching_node(NULL, pit_timer_ids);
196 pit_base_addr = of_iomap(np, 0);
200 mck = of_clk_get(np, 0);
202 /* Get the interrupts property */
203 ret = irq_of_parse_and_map(np, 0);
205 pr_crit("AT91: PIT: Unable to get IRQ from DT\n");
210 at91sam926x_pit_irq.irq = ret;
217 iounmap(pit_base_addr);
224 static int __init of_at91sam926x_pit_init(void)
231 * Set up both clocksource and clockevent support.
233 void __init at91sam926x_pit_init(void)
235 unsigned long pit_rate;
239 mck = ERR_PTR(-ENOENT);
241 /* For device tree enabled device: initialize here */
242 of_at91sam926x_pit_init();
245 * Use our actual MCK to figure out how many MCK/16 ticks per
246 * 1/HZ period (instead of a compile-time constant LATCH).
249 mck = clk_get(NULL, "mck");
252 panic("AT91: PIT: Unable to get mck clk\n");
253 pit_rate = clk_get_rate(mck) / 16;
254 pit_cycle = (pit_rate + HZ/2) / HZ;
255 WARN_ON(((pit_cycle - 1) & ~AT91_PIT_PIV) != 0);
257 /* Initialize and enable the timer */
258 at91sam926x_pit_reset();
261 * Register clocksource. The high order bits of PIV are unused,
262 * so this isn't a 32-bit counter unless we get clockevent irqs.
264 bits = 12 /* PICNT */ + ilog2(pit_cycle) /* PIV */;
265 pit_clk.mask = CLOCKSOURCE_MASK(bits);
266 clocksource_register_hz(&pit_clk, pit_rate);
268 /* Set up irq handler */
269 ret = setup_irq(at91sam926x_pit_irq.irq, &at91sam926x_pit_irq);
271 pr_crit("AT91: PIT: Unable to setup IRQ\n");
273 /* Set up and register clockevents */
274 pit_clkevt.mult = div_sc(pit_rate, NSEC_PER_SEC, pit_clkevt.shift);
275 pit_clkevt.cpumask = cpumask_of(0);
276 clockevents_register_device(&pit_clkevt);
279 void __init at91sam926x_ioremap_pit(u32 addr)
281 #if defined(CONFIG_OF)
282 struct device_node *np =
283 of_find_matching_node(NULL, pit_timer_ids);
290 pit_base_addr = ioremap(addr, 16);
293 panic("Impossible to ioremap PIT\n");