2 * Chip-specific setup code for the AT91SAM9G45 family
4 * Copyright (C) 2009 Atmel Corporation.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
13 #include <linux/module.h>
14 #include <linux/dma-mapping.h>
17 #include <asm/mach/arch.h>
18 #include <asm/mach/map.h>
19 #include <asm/system_misc.h>
20 #include <mach/at91sam9g45.h>
21 #include <mach/at91_pmc.h>
31 /* --------------------------------------------------------------------
33 * -------------------------------------------------------------------- */
36 * The peripheral clocks.
38 static struct clk pioA_clk = {
40 .pmc_mask = 1 << AT91SAM9G45_ID_PIOA,
41 .type = CLK_TYPE_PERIPHERAL,
43 static struct clk pioB_clk = {
45 .pmc_mask = 1 << AT91SAM9G45_ID_PIOB,
46 .type = CLK_TYPE_PERIPHERAL,
48 static struct clk pioC_clk = {
50 .pmc_mask = 1 << AT91SAM9G45_ID_PIOC,
51 .type = CLK_TYPE_PERIPHERAL,
53 static struct clk pioDE_clk = {
55 .pmc_mask = 1 << AT91SAM9G45_ID_PIODE,
56 .type = CLK_TYPE_PERIPHERAL,
58 static struct clk trng_clk = {
60 .pmc_mask = 1 << AT91SAM9G45_ID_TRNG,
61 .type = CLK_TYPE_PERIPHERAL,
63 static struct clk usart0_clk = {
65 .pmc_mask = 1 << AT91SAM9G45_ID_US0,
66 .type = CLK_TYPE_PERIPHERAL,
68 static struct clk usart1_clk = {
70 .pmc_mask = 1 << AT91SAM9G45_ID_US1,
71 .type = CLK_TYPE_PERIPHERAL,
73 static struct clk usart2_clk = {
75 .pmc_mask = 1 << AT91SAM9G45_ID_US2,
76 .type = CLK_TYPE_PERIPHERAL,
78 static struct clk usart3_clk = {
80 .pmc_mask = 1 << AT91SAM9G45_ID_US3,
81 .type = CLK_TYPE_PERIPHERAL,
83 static struct clk mmc0_clk = {
85 .pmc_mask = 1 << AT91SAM9G45_ID_MCI0,
86 .type = CLK_TYPE_PERIPHERAL,
88 static struct clk twi0_clk = {
90 .pmc_mask = 1 << AT91SAM9G45_ID_TWI0,
91 .type = CLK_TYPE_PERIPHERAL,
93 static struct clk twi1_clk = {
95 .pmc_mask = 1 << AT91SAM9G45_ID_TWI1,
96 .type = CLK_TYPE_PERIPHERAL,
98 static struct clk spi0_clk = {
100 .pmc_mask = 1 << AT91SAM9G45_ID_SPI0,
101 .type = CLK_TYPE_PERIPHERAL,
103 static struct clk spi1_clk = {
105 .pmc_mask = 1 << AT91SAM9G45_ID_SPI1,
106 .type = CLK_TYPE_PERIPHERAL,
108 static struct clk ssc0_clk = {
110 .pmc_mask = 1 << AT91SAM9G45_ID_SSC0,
111 .type = CLK_TYPE_PERIPHERAL,
113 static struct clk ssc1_clk = {
115 .pmc_mask = 1 << AT91SAM9G45_ID_SSC1,
116 .type = CLK_TYPE_PERIPHERAL,
118 static struct clk tcb0_clk = {
120 .pmc_mask = 1 << AT91SAM9G45_ID_TCB,
121 .type = CLK_TYPE_PERIPHERAL,
123 static struct clk pwm_clk = {
125 .pmc_mask = 1 << AT91SAM9G45_ID_PWMC,
126 .type = CLK_TYPE_PERIPHERAL,
128 static struct clk tsc_clk = {
130 .pmc_mask = 1 << AT91SAM9G45_ID_TSC,
131 .type = CLK_TYPE_PERIPHERAL,
133 static struct clk dma_clk = {
135 .pmc_mask = 1 << AT91SAM9G45_ID_DMA,
136 .type = CLK_TYPE_PERIPHERAL,
138 static struct clk uhphs_clk = {
140 .pmc_mask = 1 << AT91SAM9G45_ID_UHPHS,
141 .type = CLK_TYPE_PERIPHERAL,
143 static struct clk lcdc_clk = {
145 .pmc_mask = 1 << AT91SAM9G45_ID_LCDC,
146 .type = CLK_TYPE_PERIPHERAL,
148 static struct clk ac97_clk = {
150 .pmc_mask = 1 << AT91SAM9G45_ID_AC97C,
151 .type = CLK_TYPE_PERIPHERAL,
153 static struct clk macb_clk = {
155 .pmc_mask = 1 << AT91SAM9G45_ID_EMAC,
156 .type = CLK_TYPE_PERIPHERAL,
158 static struct clk isi_clk = {
160 .pmc_mask = 1 << AT91SAM9G45_ID_ISI,
161 .type = CLK_TYPE_PERIPHERAL,
163 static struct clk udphs_clk = {
165 .pmc_mask = 1 << AT91SAM9G45_ID_UDPHS,
166 .type = CLK_TYPE_PERIPHERAL,
168 static struct clk mmc1_clk = {
170 .pmc_mask = 1 << AT91SAM9G45_ID_MCI1,
171 .type = CLK_TYPE_PERIPHERAL,
174 /* Video decoder clock - Only for sam9m10/sam9m11 */
175 static struct clk vdec_clk = {
177 .pmc_mask = 1 << AT91SAM9G45_ID_VDEC,
178 .type = CLK_TYPE_PERIPHERAL,
181 static struct clk adc_op_clk = {
182 .name = "adc_op_clk",
183 .type = CLK_TYPE_PERIPHERAL,
187 /* AES/TDES/SHA clock - Only for sam9m11/sam9g56 */
188 static struct clk aestdessha_clk = {
189 .name = "aestdessha_clk",
190 .pmc_mask = 1 << AT91SAM9G45_ID_AESTDESSHA,
191 .type = CLK_TYPE_PERIPHERAL,
194 static struct clk *periph_clocks[] __initdata = {
227 static struct clk_lookup periph_clocks_lookups[] = {
228 /* One additional fake clock for macb_hclk */
229 CLKDEV_CON_ID("hclk", &macb_clk),
230 /* One additional fake clock for ohci */
231 CLKDEV_CON_ID("ohci_clk", &uhphs_clk),
232 CLKDEV_CON_DEV_ID("hclk", "at91sam9g45-lcdfb.0", &lcdc_clk),
233 CLKDEV_CON_DEV_ID("hclk", "at91sam9g45es-lcdfb.0", &lcdc_clk),
234 CLKDEV_CON_DEV_ID("ehci_clk", "atmel-ehci", &uhphs_clk),
235 CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
236 CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
237 CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.0", &mmc0_clk),
238 CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.1", &mmc1_clk),
239 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
240 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
241 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb0_clk),
242 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tcb0_clk),
243 CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g10.0", &twi0_clk),
244 CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g10.1", &twi1_clk),
245 CLKDEV_CON_DEV_ID("pclk", "at91sam9g45_ssc.0", &ssc0_clk),
246 CLKDEV_CON_DEV_ID("pclk", "at91sam9g45_ssc.1", &ssc1_clk),
247 CLKDEV_CON_DEV_ID("pclk", "fff9c000.ssc", &ssc0_clk),
248 CLKDEV_CON_DEV_ID("pclk", "fffa0000.ssc", &ssc1_clk),
249 CLKDEV_CON_DEV_ID(NULL, "atmel-trng", &trng_clk),
250 CLKDEV_CON_DEV_ID(NULL, "atmel_sha", &aestdessha_clk),
251 CLKDEV_CON_DEV_ID(NULL, "atmel_tdes", &aestdessha_clk),
252 CLKDEV_CON_DEV_ID(NULL, "atmel_aes", &aestdessha_clk),
253 /* more usart lookup table for DT entries */
254 CLKDEV_CON_DEV_ID("usart", "ffffee00.serial", &mck),
255 CLKDEV_CON_DEV_ID("usart", "fff8c000.serial", &usart0_clk),
256 CLKDEV_CON_DEV_ID("usart", "fff90000.serial", &usart1_clk),
257 CLKDEV_CON_DEV_ID("usart", "fff94000.serial", &usart2_clk),
258 CLKDEV_CON_DEV_ID("usart", "fff98000.serial", &usart3_clk),
259 /* more tc lookup table for DT entries */
260 CLKDEV_CON_DEV_ID("t0_clk", "fff7c000.timer", &tcb0_clk),
261 CLKDEV_CON_DEV_ID("t0_clk", "fffd4000.timer", &tcb0_clk),
262 CLKDEV_CON_DEV_ID("hclk", "700000.ohci", &uhphs_clk),
263 CLKDEV_CON_DEV_ID("ehci_clk", "800000.ehci", &uhphs_clk),
264 CLKDEV_CON_DEV_ID("mci_clk", "fff80000.mmc", &mmc0_clk),
265 CLKDEV_CON_DEV_ID("mci_clk", "fffd0000.mmc", &mmc1_clk),
266 CLKDEV_CON_DEV_ID(NULL, "fff84000.i2c", &twi0_clk),
267 CLKDEV_CON_DEV_ID(NULL, "fff88000.i2c", &twi1_clk),
268 CLKDEV_CON_DEV_ID("spi_clk", "fffa4000.spi", &spi0_clk),
269 CLKDEV_CON_DEV_ID("spi_clk", "fffa8000.spi", &spi1_clk),
270 CLKDEV_CON_DEV_ID("hclk", "600000.gadget", &utmi_clk),
271 CLKDEV_CON_DEV_ID("pclk", "600000.gadget", &udphs_clk),
272 /* fake hclk clock */
273 CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &uhphs_clk),
274 CLKDEV_CON_DEV_ID(NULL, "fffff200.gpio", &pioA_clk),
275 CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioB_clk),
276 CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioC_clk),
277 CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioDE_clk),
278 CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioDE_clk),
280 CLKDEV_CON_ID("pioA", &pioA_clk),
281 CLKDEV_CON_ID("pioB", &pioB_clk),
282 CLKDEV_CON_ID("pioC", &pioC_clk),
283 CLKDEV_CON_ID("pioD", &pioDE_clk),
284 CLKDEV_CON_ID("pioE", &pioDE_clk),
286 CLKDEV_CON_ID("adc_clk", &tsc_clk),
289 static struct clk_lookup usart_clocks_lookups[] = {
290 CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
291 CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
292 CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
293 CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
294 CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
298 * The two programmable clocks.
299 * You must configure pin multiplexing to bring these signals out.
301 static struct clk pck0 = {
303 .pmc_mask = AT91_PMC_PCK0,
304 .type = CLK_TYPE_PROGRAMMABLE,
307 static struct clk pck1 = {
309 .pmc_mask = AT91_PMC_PCK1,
310 .type = CLK_TYPE_PROGRAMMABLE,
314 static void __init at91sam9g45_register_clocks(void)
318 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
319 clk_register(periph_clocks[i]);
321 clkdev_add_table(periph_clocks_lookups,
322 ARRAY_SIZE(periph_clocks_lookups));
323 clkdev_add_table(usart_clocks_lookups,
324 ARRAY_SIZE(usart_clocks_lookups));
326 if (cpu_is_at91sam9m10() || cpu_is_at91sam9m11())
327 clk_register(&vdec_clk);
333 /* --------------------------------------------------------------------
335 * -------------------------------------------------------------------- */
337 static struct at91_gpio_bank at91sam9g45_gpio[] __initdata = {
339 .id = AT91SAM9G45_ID_PIOA,
340 .regbase = AT91SAM9G45_BASE_PIOA,
342 .id = AT91SAM9G45_ID_PIOB,
343 .regbase = AT91SAM9G45_BASE_PIOB,
345 .id = AT91SAM9G45_ID_PIOC,
346 .regbase = AT91SAM9G45_BASE_PIOC,
348 .id = AT91SAM9G45_ID_PIODE,
349 .regbase = AT91SAM9G45_BASE_PIOD,
351 .id = AT91SAM9G45_ID_PIODE,
352 .regbase = AT91SAM9G45_BASE_PIOE,
356 /* --------------------------------------------------------------------
357 * AT91SAM9G45 processor initialization
358 * -------------------------------------------------------------------- */
360 static void __init at91sam9g45_map_io(void)
362 at91_init_sram(0, AT91SAM9G45_SRAM_BASE, AT91SAM9G45_SRAM_SIZE);
365 static void __init at91sam9g45_ioremap_registers(void)
367 at91_ioremap_shdwc(AT91SAM9G45_BASE_SHDWC);
368 at91_ioremap_rstc(AT91SAM9G45_BASE_RSTC);
369 at91_ioremap_ramc(0, AT91SAM9G45_BASE_DDRSDRC1, 512);
370 at91_ioremap_ramc(1, AT91SAM9G45_BASE_DDRSDRC0, 512);
371 at91sam926x_ioremap_pit(AT91SAM9G45_BASE_PIT);
372 at91sam9_ioremap_smc(0, AT91SAM9G45_BASE_SMC);
373 at91_ioremap_matrix(AT91SAM9G45_BASE_MATRIX);
374 at91_pm_set_standby(at91_ddr_standby);
377 static void __init at91sam9g45_initialize(void)
379 arm_pm_idle = at91sam9_idle;
380 arm_pm_restart = at91sam9g45_restart;
382 at91_sysirq_mask_rtc(AT91SAM9G45_BASE_RTC);
383 at91_sysirq_mask_rtt(AT91SAM9G45_BASE_RTT);
385 /* Register GPIO subsystem */
386 at91_gpio_init(at91sam9g45_gpio, 5);
389 /* --------------------------------------------------------------------
390 * Interrupt initialization
391 * -------------------------------------------------------------------- */
394 * The default interrupt priority levels (0 = lowest, 7 = highest).
396 static unsigned int at91sam9g45_default_irq_priority[NR_AIC_IRQS] __initdata = {
397 7, /* Advanced Interrupt Controller (FIQ) */
398 7, /* System Peripherals */
399 1, /* Parallel IO Controller A */
400 1, /* Parallel IO Controller B */
401 1, /* Parallel IO Controller C */
402 1, /* Parallel IO Controller D and E */
408 0, /* Multimedia Card Interface 0 */
409 6, /* Two-Wire Interface 0 */
410 6, /* Two-Wire Interface 1 */
411 5, /* Serial Peripheral Interface 0 */
412 5, /* Serial Peripheral Interface 1 */
413 4, /* Serial Synchronous Controller 0 */
414 4, /* Serial Synchronous Controller 1 */
415 0, /* Timer Counter 0, 1, 2, 3, 4 and 5 */
416 0, /* Pulse Width Modulation Controller */
417 0, /* Touch Screen Controller */
418 0, /* DMA Controller */
419 2, /* USB Host High Speed port */
420 3, /* LDC Controller */
421 5, /* AC97 Controller */
423 0, /* Image Sensor Interface */
424 2, /* USB Device High speed port */
425 0, /* AESTDESSHA Crypto HW Accelerators */
426 0, /* Multimedia Card Interface 1 */
428 0, /* Advanced Interrupt Controller (IRQ0) */
431 AT91_SOC_START(at91sam9g45)
432 .map_io = at91sam9g45_map_io,
433 .default_irq_priority = at91sam9g45_default_irq_priority,
434 .extern_irq = (1 << AT91SAM9G45_ID_IRQ0),
435 .ioremap_registers = at91sam9g45_ioremap_registers,
436 .register_clocks = at91sam9g45_register_clocks,
437 .init = at91sam9g45_initialize,