2 * Chip-specific setup code for the AT91SAM9G45 family
4 * Copyright (C) 2009 Atmel Corporation.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
13 #include <linux/module.h>
17 #include <asm/mach/arch.h>
18 #include <asm/mach/map.h>
19 #include <mach/at91sam9g45.h>
20 #include <mach/at91_pmc.h>
21 #include <mach/at91_rstc.h>
22 #include <mach/at91_shdwc.h>
27 static struct map_desc at91sam9g45_io_desc[] __initdata = {
29 .virtual = AT91_VA_BASE_SYS,
30 .pfn = __phys_to_pfn(AT91_BASE_SYS),
34 .virtual = AT91_IO_VIRT_BASE - AT91SAM9G45_SRAM_SIZE,
35 .pfn = __phys_to_pfn(AT91SAM9G45_SRAM_BASE),
36 .length = AT91SAM9G45_SRAM_SIZE,
41 /* --------------------------------------------------------------------
43 * -------------------------------------------------------------------- */
46 * The peripheral clocks.
48 static struct clk pioA_clk = {
50 .pmc_mask = 1 << AT91SAM9G45_ID_PIOA,
51 .type = CLK_TYPE_PERIPHERAL,
53 static struct clk pioB_clk = {
55 .pmc_mask = 1 << AT91SAM9G45_ID_PIOB,
56 .type = CLK_TYPE_PERIPHERAL,
58 static struct clk pioC_clk = {
60 .pmc_mask = 1 << AT91SAM9G45_ID_PIOC,
61 .type = CLK_TYPE_PERIPHERAL,
63 static struct clk pioDE_clk = {
65 .pmc_mask = 1 << AT91SAM9G45_ID_PIODE,
66 .type = CLK_TYPE_PERIPHERAL,
68 static struct clk usart0_clk = {
70 .pmc_mask = 1 << AT91SAM9G45_ID_US0,
71 .type = CLK_TYPE_PERIPHERAL,
73 static struct clk usart1_clk = {
75 .pmc_mask = 1 << AT91SAM9G45_ID_US1,
76 .type = CLK_TYPE_PERIPHERAL,
78 static struct clk usart2_clk = {
80 .pmc_mask = 1 << AT91SAM9G45_ID_US2,
81 .type = CLK_TYPE_PERIPHERAL,
83 static struct clk usart3_clk = {
85 .pmc_mask = 1 << AT91SAM9G45_ID_US3,
86 .type = CLK_TYPE_PERIPHERAL,
88 static struct clk mmc0_clk = {
90 .pmc_mask = 1 << AT91SAM9G45_ID_MCI0,
91 .type = CLK_TYPE_PERIPHERAL,
93 static struct clk twi0_clk = {
95 .pmc_mask = 1 << AT91SAM9G45_ID_TWI0,
96 .type = CLK_TYPE_PERIPHERAL,
98 static struct clk twi1_clk = {
100 .pmc_mask = 1 << AT91SAM9G45_ID_TWI1,
101 .type = CLK_TYPE_PERIPHERAL,
103 static struct clk spi0_clk = {
105 .pmc_mask = 1 << AT91SAM9G45_ID_SPI0,
106 .type = CLK_TYPE_PERIPHERAL,
108 static struct clk spi1_clk = {
110 .pmc_mask = 1 << AT91SAM9G45_ID_SPI1,
111 .type = CLK_TYPE_PERIPHERAL,
113 static struct clk ssc0_clk = {
115 .pmc_mask = 1 << AT91SAM9G45_ID_SSC0,
116 .type = CLK_TYPE_PERIPHERAL,
118 static struct clk ssc1_clk = {
120 .pmc_mask = 1 << AT91SAM9G45_ID_SSC1,
121 .type = CLK_TYPE_PERIPHERAL,
123 static struct clk tcb_clk = {
125 .pmc_mask = 1 << AT91SAM9G45_ID_TCB,
126 .type = CLK_TYPE_PERIPHERAL,
128 static struct clk pwm_clk = {
130 .pmc_mask = 1 << AT91SAM9G45_ID_PWMC,
131 .type = CLK_TYPE_PERIPHERAL,
133 static struct clk tsc_clk = {
135 .pmc_mask = 1 << AT91SAM9G45_ID_TSC,
136 .type = CLK_TYPE_PERIPHERAL,
138 static struct clk dma_clk = {
140 .pmc_mask = 1 << AT91SAM9G45_ID_DMA,
141 .type = CLK_TYPE_PERIPHERAL,
143 static struct clk uhphs_clk = {
145 .pmc_mask = 1 << AT91SAM9G45_ID_UHPHS,
146 .type = CLK_TYPE_PERIPHERAL,
148 static struct clk lcdc_clk = {
150 .pmc_mask = 1 << AT91SAM9G45_ID_LCDC,
151 .type = CLK_TYPE_PERIPHERAL,
153 static struct clk ac97_clk = {
155 .pmc_mask = 1 << AT91SAM9G45_ID_AC97C,
156 .type = CLK_TYPE_PERIPHERAL,
158 static struct clk macb_clk = {
160 .pmc_mask = 1 << AT91SAM9G45_ID_EMAC,
161 .type = CLK_TYPE_PERIPHERAL,
163 static struct clk isi_clk = {
165 .pmc_mask = 1 << AT91SAM9G45_ID_ISI,
166 .type = CLK_TYPE_PERIPHERAL,
168 static struct clk udphs_clk = {
170 .pmc_mask = 1 << AT91SAM9G45_ID_UDPHS,
171 .type = CLK_TYPE_PERIPHERAL,
173 static struct clk mmc1_clk = {
175 .pmc_mask = 1 << AT91SAM9G45_ID_MCI1,
176 .type = CLK_TYPE_PERIPHERAL,
179 /* One additional fake clock for ohci */
180 static struct clk ohci_clk = {
183 .type = CLK_TYPE_PERIPHERAL,
184 .parent = &uhphs_clk,
187 static struct clk *periph_clocks[] __initdata = {
219 * The two programmable clocks.
220 * You must configure pin multiplexing to bring these signals out.
222 static struct clk pck0 = {
224 .pmc_mask = AT91_PMC_PCK0,
225 .type = CLK_TYPE_PROGRAMMABLE,
228 static struct clk pck1 = {
230 .pmc_mask = AT91_PMC_PCK1,
231 .type = CLK_TYPE_PROGRAMMABLE,
235 static void __init at91sam9g45_register_clocks(void)
239 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
240 clk_register(periph_clocks[i]);
246 /* --------------------------------------------------------------------
248 * -------------------------------------------------------------------- */
250 static struct at91_gpio_bank at91sam9g45_gpio[] = {
252 .id = AT91SAM9G45_ID_PIOA,
256 .id = AT91SAM9G45_ID_PIOB,
260 .id = AT91SAM9G45_ID_PIOC,
264 .id = AT91SAM9G45_ID_PIODE,
268 .id = AT91SAM9G45_ID_PIODE,
274 static void at91sam9g45_reset(void)
276 at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
279 static void at91sam9g45_poweroff(void)
281 at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
285 /* --------------------------------------------------------------------
286 * AT91SAM9G45 processor initialization
287 * -------------------------------------------------------------------- */
289 void __init at91sam9g45_initialize(unsigned long main_clock)
291 /* Map peripherals */
292 iotable_init(at91sam9g45_io_desc, ARRAY_SIZE(at91sam9g45_io_desc));
294 at91_arch_reset = at91sam9g45_reset;
295 pm_power_off = at91sam9g45_poweroff;
296 at91_extern_irq = (1 << AT91SAM9G45_ID_IRQ0);
298 /* Init clock subsystem */
299 at91_clock_init(main_clock);
301 /* Register the processor-specific clocks */
302 at91sam9g45_register_clocks();
304 /* Register GPIO subsystem */
305 at91_gpio_init(at91sam9g45_gpio, 5);
308 /* --------------------------------------------------------------------
309 * Interrupt initialization
310 * -------------------------------------------------------------------- */
313 * The default interrupt priority levels (0 = lowest, 7 = highest).
315 static unsigned int at91sam9g45_default_irq_priority[NR_AIC_IRQS] __initdata = {
316 7, /* Advanced Interrupt Controller (FIQ) */
317 7, /* System Peripherals */
318 1, /* Parallel IO Controller A */
319 1, /* Parallel IO Controller B */
320 1, /* Parallel IO Controller C */
321 1, /* Parallel IO Controller D and E */
327 0, /* Multimedia Card Interface 0 */
328 6, /* Two-Wire Interface 0 */
329 6, /* Two-Wire Interface 1 */
330 5, /* Serial Peripheral Interface 0 */
331 5, /* Serial Peripheral Interface 1 */
332 4, /* Serial Synchronous Controller 0 */
333 4, /* Serial Synchronous Controller 1 */
334 0, /* Timer Counter 0, 1, 2, 3, 4 and 5 */
335 0, /* Pulse Width Modulation Controller */
336 0, /* Touch Screen Controller */
337 0, /* DMA Controller */
338 2, /* USB Host High Speed port */
339 3, /* LDC Controller */
340 5, /* AC97 Controller */
342 0, /* Image Sensor Interface */
343 2, /* USB Device High speed port */
345 0, /* Multimedia Card Interface 1 */
347 0, /* Advanced Interrupt Controller (IRQ0) */
350 void __init at91sam9g45_init_interrupts(unsigned int priority[NR_AIC_IRQS])
353 priority = at91sam9g45_default_irq_priority;
355 /* Initialize the AIC interrupt controller */
356 at91_aic_init(priority);
358 /* Enable GPIO interrupts */
359 at91_gpio_irq_setup();