2 * On-Chip devices setup code for the AT91SAM9G45 family
4 * Copyright (C) 2009 Atmel Corporation.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
12 #include <asm/mach/arch.h>
13 #include <asm/mach/map.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/gpio.h>
17 #include <linux/clk.h>
18 #include <linux/platform_device.h>
19 #include <linux/i2c-gpio.h>
20 #include <linux/atmel-mci.h>
21 #include <linux/platform_data/crypto-atmel.h>
23 #include <linux/platform_data/at91_adc.h>
26 #include <video/atmel_lcdc.h>
28 #include <mach/at91_adc.h>
29 #include <mach/at91sam9g45.h>
30 #include <mach/at91sam9g45_matrix.h>
31 #include <mach/at91_matrix.h>
32 #include <mach/at91sam9_smc.h>
33 #include <linux/platform_data/dma-atmel.h>
34 #include <mach/atmel-mci.h>
35 #include <mach/hardware.h>
37 #include <media/atmel-isi.h>
44 /* --------------------------------------------------------------------
45 * HDMAC - AHB DMA Controller
46 * -------------------------------------------------------------------- */
48 #if defined(CONFIG_AT_HDMAC) || defined(CONFIG_AT_HDMAC_MODULE)
49 static u64 hdmac_dmamask = DMA_BIT_MASK(32);
51 static struct resource hdmac_resources[] = {
53 .start = AT91SAM9G45_BASE_DMA,
54 .end = AT91SAM9G45_BASE_DMA + SZ_512 - 1,
55 .flags = IORESOURCE_MEM,
58 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_DMA,
59 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_DMA,
60 .flags = IORESOURCE_IRQ,
64 static struct platform_device at_hdmac_device = {
65 .name = "at91sam9g45_dma",
68 .dma_mask = &hdmac_dmamask,
69 .coherent_dma_mask = DMA_BIT_MASK(32),
71 .resource = hdmac_resources,
72 .num_resources = ARRAY_SIZE(hdmac_resources),
75 void __init at91_add_device_hdmac(void)
77 platform_device_register(&at_hdmac_device);
80 void __init at91_add_device_hdmac(void) {}
84 /* --------------------------------------------------------------------
86 * -------------------------------------------------------------------- */
88 #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
89 static u64 ohci_dmamask = DMA_BIT_MASK(32);
90 static struct at91_usbh_data usbh_ohci_data;
92 static struct resource usbh_ohci_resources[] = {
94 .start = AT91SAM9G45_OHCI_BASE,
95 .end = AT91SAM9G45_OHCI_BASE + SZ_1M - 1,
96 .flags = IORESOURCE_MEM,
99 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_UHPHS,
100 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_UHPHS,
101 .flags = IORESOURCE_IRQ,
105 static struct platform_device at91_usbh_ohci_device = {
109 .dma_mask = &ohci_dmamask,
110 .coherent_dma_mask = DMA_BIT_MASK(32),
111 .platform_data = &usbh_ohci_data,
113 .resource = usbh_ohci_resources,
114 .num_resources = ARRAY_SIZE(usbh_ohci_resources),
117 void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data)
124 /* Enable VBus control for UHP ports */
125 for (i = 0; i < data->ports; i++) {
126 if (gpio_is_valid(data->vbus_pin[i]))
127 at91_set_gpio_output(data->vbus_pin[i],
128 data->vbus_pin_active_low[i]);
131 /* Enable overcurrent notification */
132 for (i = 0; i < data->ports; i++) {
133 if (gpio_is_valid(data->overcurrent_pin[i]))
134 at91_set_gpio_input(data->overcurrent_pin[i], 1);
137 usbh_ohci_data = *data;
138 platform_device_register(&at91_usbh_ohci_device);
141 void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data) {}
145 /* --------------------------------------------------------------------
147 * Needs an OHCI host for low and full speed management
148 * -------------------------------------------------------------------- */
150 #if defined(CONFIG_USB_EHCI_HCD) || defined(CONFIG_USB_EHCI_HCD_MODULE)
151 static u64 ehci_dmamask = DMA_BIT_MASK(32);
152 static struct at91_usbh_data usbh_ehci_data;
154 static struct resource usbh_ehci_resources[] = {
156 .start = AT91SAM9G45_EHCI_BASE,
157 .end = AT91SAM9G45_EHCI_BASE + SZ_1M - 1,
158 .flags = IORESOURCE_MEM,
161 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_UHPHS,
162 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_UHPHS,
163 .flags = IORESOURCE_IRQ,
167 static struct platform_device at91_usbh_ehci_device = {
168 .name = "atmel-ehci",
171 .dma_mask = &ehci_dmamask,
172 .coherent_dma_mask = DMA_BIT_MASK(32),
173 .platform_data = &usbh_ehci_data,
175 .resource = usbh_ehci_resources,
176 .num_resources = ARRAY_SIZE(usbh_ehci_resources),
179 void __init at91_add_device_usbh_ehci(struct at91_usbh_data *data)
186 /* Enable VBus control for UHP ports */
187 for (i = 0; i < data->ports; i++) {
188 if (gpio_is_valid(data->vbus_pin[i]))
189 at91_set_gpio_output(data->vbus_pin[i],
190 data->vbus_pin_active_low[i]);
193 usbh_ehci_data = *data;
194 platform_device_register(&at91_usbh_ehci_device);
197 void __init at91_add_device_usbh_ehci(struct at91_usbh_data *data) {}
201 /* --------------------------------------------------------------------
202 * USB HS Device (Gadget)
203 * -------------------------------------------------------------------- */
205 #if defined(CONFIG_USB_ATMEL_USBA) || defined(CONFIG_USB_ATMEL_USBA_MODULE)
206 static struct resource usba_udc_resources[] = {
208 .start = AT91SAM9G45_UDPHS_FIFO,
209 .end = AT91SAM9G45_UDPHS_FIFO + SZ_512K - 1,
210 .flags = IORESOURCE_MEM,
213 .start = AT91SAM9G45_BASE_UDPHS,
214 .end = AT91SAM9G45_BASE_UDPHS + SZ_1K - 1,
215 .flags = IORESOURCE_MEM,
218 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_UDPHS,
219 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_UDPHS,
220 .flags = IORESOURCE_IRQ,
224 #define EP(nam, idx, maxpkt, maxbk, dma, isoc) \
228 .fifo_size = maxpkt, \
234 static struct usba_ep_data usba_udc_ep[] __initdata = {
235 EP("ep0", 0, 64, 1, 0, 0),
236 EP("ep1", 1, 1024, 2, 1, 1),
237 EP("ep2", 2, 1024, 2, 1, 1),
238 EP("ep3", 3, 1024, 3, 1, 0),
239 EP("ep4", 4, 1024, 3, 1, 0),
240 EP("ep5", 5, 1024, 3, 1, 1),
241 EP("ep6", 6, 1024, 3, 1, 1),
247 * pdata doesn't have room for any endpoints, so we need to
248 * append room for the ones we need right after it.
251 struct usba_platform_data pdata;
252 struct usba_ep_data ep[7];
255 static struct platform_device at91_usba_udc_device = {
256 .name = "atmel_usba_udc",
259 .platform_data = &usba_udc_data.pdata,
261 .resource = usba_udc_resources,
262 .num_resources = ARRAY_SIZE(usba_udc_resources),
265 void __init at91_add_device_usba(struct usba_platform_data *data)
267 usba_udc_data.pdata.vbus_pin = -EINVAL;
268 usba_udc_data.pdata.num_ep = ARRAY_SIZE(usba_udc_ep);
269 memcpy(usba_udc_data.ep, usba_udc_ep, sizeof(usba_udc_ep));
271 if (data && gpio_is_valid(data->vbus_pin)) {
272 at91_set_gpio_input(data->vbus_pin, 0);
273 at91_set_deglitch(data->vbus_pin, 1);
274 usba_udc_data.pdata.vbus_pin = data->vbus_pin;
277 /* Pullup pin is handled internally by USB device peripheral */
279 platform_device_register(&at91_usba_udc_device);
282 void __init at91_add_device_usba(struct usba_platform_data *data) {}
286 /* --------------------------------------------------------------------
288 * -------------------------------------------------------------------- */
290 #if defined(CONFIG_MACB) || defined(CONFIG_MACB_MODULE)
291 static u64 eth_dmamask = DMA_BIT_MASK(32);
292 static struct macb_platform_data eth_data;
294 static struct resource eth_resources[] = {
296 .start = AT91SAM9G45_BASE_EMAC,
297 .end = AT91SAM9G45_BASE_EMAC + SZ_16K - 1,
298 .flags = IORESOURCE_MEM,
301 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_EMAC,
302 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_EMAC,
303 .flags = IORESOURCE_IRQ,
307 static struct platform_device at91sam9g45_eth_device = {
311 .dma_mask = ð_dmamask,
312 .coherent_dma_mask = DMA_BIT_MASK(32),
313 .platform_data = ð_data,
315 .resource = eth_resources,
316 .num_resources = ARRAY_SIZE(eth_resources),
319 void __init at91_add_device_eth(struct macb_platform_data *data)
324 if (gpio_is_valid(data->phy_irq_pin)) {
325 at91_set_gpio_input(data->phy_irq_pin, 0);
326 at91_set_deglitch(data->phy_irq_pin, 1);
329 /* Pins used for MII and RMII */
330 at91_set_A_periph(AT91_PIN_PA17, 0); /* ETXCK_EREFCK */
331 at91_set_A_periph(AT91_PIN_PA15, 0); /* ERXDV */
332 at91_set_A_periph(AT91_PIN_PA12, 0); /* ERX0 */
333 at91_set_A_periph(AT91_PIN_PA13, 0); /* ERX1 */
334 at91_set_A_periph(AT91_PIN_PA16, 0); /* ERXER */
335 at91_set_A_periph(AT91_PIN_PA14, 0); /* ETXEN */
336 at91_set_A_periph(AT91_PIN_PA10, 0); /* ETX0 */
337 at91_set_A_periph(AT91_PIN_PA11, 0); /* ETX1 */
338 at91_set_A_periph(AT91_PIN_PA19, 0); /* EMDIO */
339 at91_set_A_periph(AT91_PIN_PA18, 0); /* EMDC */
341 if (!data->is_rmii) {
342 at91_set_B_periph(AT91_PIN_PA29, 0); /* ECRS */
343 at91_set_B_periph(AT91_PIN_PA30, 0); /* ECOL */
344 at91_set_B_periph(AT91_PIN_PA8, 0); /* ERX2 */
345 at91_set_B_periph(AT91_PIN_PA9, 0); /* ERX3 */
346 at91_set_B_periph(AT91_PIN_PA28, 0); /* ERXCK */
347 at91_set_B_periph(AT91_PIN_PA6, 0); /* ETX2 */
348 at91_set_B_periph(AT91_PIN_PA7, 0); /* ETX3 */
349 at91_set_B_periph(AT91_PIN_PA27, 0); /* ETXER */
353 platform_device_register(&at91sam9g45_eth_device);
356 void __init at91_add_device_eth(struct macb_platform_data *data) {}
360 /* --------------------------------------------------------------------
362 * -------------------------------------------------------------------- */
364 #if defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_ATMELMCI_MODULE)
365 static u64 mmc_dmamask = DMA_BIT_MASK(32);
366 static struct mci_platform_data mmc0_data, mmc1_data;
368 static struct resource mmc0_resources[] = {
370 .start = AT91SAM9G45_BASE_MCI0,
371 .end = AT91SAM9G45_BASE_MCI0 + SZ_16K - 1,
372 .flags = IORESOURCE_MEM,
375 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_MCI0,
376 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_MCI0,
377 .flags = IORESOURCE_IRQ,
381 static struct platform_device at91sam9g45_mmc0_device = {
385 .dma_mask = &mmc_dmamask,
386 .coherent_dma_mask = DMA_BIT_MASK(32),
387 .platform_data = &mmc0_data,
389 .resource = mmc0_resources,
390 .num_resources = ARRAY_SIZE(mmc0_resources),
393 static struct resource mmc1_resources[] = {
395 .start = AT91SAM9G45_BASE_MCI1,
396 .end = AT91SAM9G45_BASE_MCI1 + SZ_16K - 1,
397 .flags = IORESOURCE_MEM,
400 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_MCI1,
401 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_MCI1,
402 .flags = IORESOURCE_IRQ,
406 static struct platform_device at91sam9g45_mmc1_device = {
410 .dma_mask = &mmc_dmamask,
411 .coherent_dma_mask = DMA_BIT_MASK(32),
412 .platform_data = &mmc1_data,
414 .resource = mmc1_resources,
415 .num_resources = ARRAY_SIZE(mmc1_resources),
418 /* Consider only one slot : slot 0 */
419 void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data)
425 /* Must have at least one usable slot */
426 if (!data->slot[0].bus_width)
429 #if defined(CONFIG_AT_HDMAC) || defined(CONFIG_AT_HDMAC_MODULE)
431 struct at_dma_slave *atslave;
432 struct mci_dma_data *alt_atslave;
434 alt_atslave = kzalloc(sizeof(struct mci_dma_data), GFP_KERNEL);
435 atslave = &alt_atslave->sdata;
437 /* DMA slave channel configuration */
438 atslave->dma_dev = &at_hdmac_device.dev;
439 atslave->cfg = ATC_FIFOCFG_HALFFIFO
440 | ATC_SRC_H2SEL_HW | ATC_DST_H2SEL_HW;
441 if (mmc_id == 0) /* MCI0 */
442 atslave->cfg |= ATC_SRC_PER(AT_DMA_ID_MCI0)
443 | ATC_DST_PER(AT_DMA_ID_MCI0);
446 atslave->cfg |= ATC_SRC_PER(AT_DMA_ID_MCI1)
447 | ATC_DST_PER(AT_DMA_ID_MCI1);
449 data->dma_slave = alt_atslave;
455 if (gpio_is_valid(data->slot[0].detect_pin)) {
456 at91_set_gpio_input(data->slot[0].detect_pin, 1);
457 at91_set_deglitch(data->slot[0].detect_pin, 1);
459 if (gpio_is_valid(data->slot[0].wp_pin))
460 at91_set_gpio_input(data->slot[0].wp_pin, 1);
462 if (mmc_id == 0) { /* MCI0 */
465 at91_set_A_periph(AT91_PIN_PA0, 0);
468 at91_set_A_periph(AT91_PIN_PA1, 1);
470 /* DAT0, maybe DAT1..DAT3 and maybe DAT4..DAT7 */
471 at91_set_A_periph(AT91_PIN_PA2, 1);
472 if (data->slot[0].bus_width == 4) {
473 at91_set_A_periph(AT91_PIN_PA3, 1);
474 at91_set_A_periph(AT91_PIN_PA4, 1);
475 at91_set_A_periph(AT91_PIN_PA5, 1);
476 if (data->slot[0].bus_width == 8) {
477 at91_set_A_periph(AT91_PIN_PA6, 1);
478 at91_set_A_periph(AT91_PIN_PA7, 1);
479 at91_set_A_periph(AT91_PIN_PA8, 1);
480 at91_set_A_periph(AT91_PIN_PA9, 1);
485 platform_device_register(&at91sam9g45_mmc0_device);
490 at91_set_A_periph(AT91_PIN_PA31, 0);
493 at91_set_A_periph(AT91_PIN_PA22, 1);
495 /* DAT0, maybe DAT1..DAT3 and maybe DAT4..DAT7 */
496 at91_set_A_periph(AT91_PIN_PA23, 1);
497 if (data->slot[0].bus_width == 4) {
498 at91_set_A_periph(AT91_PIN_PA24, 1);
499 at91_set_A_periph(AT91_PIN_PA25, 1);
500 at91_set_A_periph(AT91_PIN_PA26, 1);
501 if (data->slot[0].bus_width == 8) {
502 at91_set_A_periph(AT91_PIN_PA27, 1);
503 at91_set_A_periph(AT91_PIN_PA28, 1);
504 at91_set_A_periph(AT91_PIN_PA29, 1);
505 at91_set_A_periph(AT91_PIN_PA30, 1);
510 platform_device_register(&at91sam9g45_mmc1_device);
515 void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data) {}
519 /* --------------------------------------------------------------------
521 * -------------------------------------------------------------------- */
523 #if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE)
524 static struct atmel_nand_data nand_data;
526 #define NAND_BASE AT91_CHIPSELECT_3
528 static struct resource nand_resources[] = {
531 .end = NAND_BASE + SZ_256M - 1,
532 .flags = IORESOURCE_MEM,
535 .start = AT91SAM9G45_BASE_ECC,
536 .end = AT91SAM9G45_BASE_ECC + SZ_512 - 1,
537 .flags = IORESOURCE_MEM,
541 static struct platform_device at91sam9g45_nand_device = {
542 .name = "atmel_nand",
545 .platform_data = &nand_data,
547 .resource = nand_resources,
548 .num_resources = ARRAY_SIZE(nand_resources),
551 void __init at91_add_device_nand(struct atmel_nand_data *data)
558 csa = at91_matrix_read(AT91_MATRIX_EBICSA);
559 at91_matrix_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA);
562 if (gpio_is_valid(data->enable_pin))
563 at91_set_gpio_output(data->enable_pin, 1);
566 if (gpio_is_valid(data->rdy_pin))
567 at91_set_gpio_input(data->rdy_pin, 1);
569 /* card detect pin */
570 if (gpio_is_valid(data->det_pin))
571 at91_set_gpio_input(data->det_pin, 1);
574 platform_device_register(&at91sam9g45_nand_device);
577 void __init at91_add_device_nand(struct atmel_nand_data *data) {}
581 /* --------------------------------------------------------------------
583 * -------------------------------------------------------------------- */
586 * Prefer the GPIO code since the TWI controller isn't robust
587 * (gets overruns and underruns under load) and can only issue
588 * repeated STARTs in one scenario (the driver doesn't yet handle them).
590 #if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
591 static struct i2c_gpio_platform_data pdata_i2c0 = {
592 .sda_pin = AT91_PIN_PA20,
593 .sda_is_open_drain = 1,
594 .scl_pin = AT91_PIN_PA21,
595 .scl_is_open_drain = 1,
596 .udelay = 5, /* ~100 kHz */
599 static struct platform_device at91sam9g45_twi0_device = {
602 .dev.platform_data = &pdata_i2c0,
605 static struct i2c_gpio_platform_data pdata_i2c1 = {
606 .sda_pin = AT91_PIN_PB10,
607 .sda_is_open_drain = 1,
608 .scl_pin = AT91_PIN_PB11,
609 .scl_is_open_drain = 1,
610 .udelay = 5, /* ~100 kHz */
613 static struct platform_device at91sam9g45_twi1_device = {
616 .dev.platform_data = &pdata_i2c1,
619 void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices)
621 i2c_register_board_info(i2c_id, devices, nr_devices);
624 at91_set_GPIO_periph(AT91_PIN_PA20, 1); /* TWD (SDA) */
625 at91_set_multi_drive(AT91_PIN_PA20, 1);
627 at91_set_GPIO_periph(AT91_PIN_PA21, 1); /* TWCK (SCL) */
628 at91_set_multi_drive(AT91_PIN_PA21, 1);
630 platform_device_register(&at91sam9g45_twi0_device);
632 at91_set_GPIO_periph(AT91_PIN_PB10, 1); /* TWD (SDA) */
633 at91_set_multi_drive(AT91_PIN_PB10, 1);
635 at91_set_GPIO_periph(AT91_PIN_PB11, 1); /* TWCK (SCL) */
636 at91_set_multi_drive(AT91_PIN_PB11, 1);
638 platform_device_register(&at91sam9g45_twi1_device);
642 #elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
643 static struct resource twi0_resources[] = {
645 .start = AT91SAM9G45_BASE_TWI0,
646 .end = AT91SAM9G45_BASE_TWI0 + SZ_16K - 1,
647 .flags = IORESOURCE_MEM,
650 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_TWI0,
651 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_TWI0,
652 .flags = IORESOURCE_IRQ,
656 static struct platform_device at91sam9g45_twi0_device = {
657 .name = "i2c-at91sam9g10",
659 .resource = twi0_resources,
660 .num_resources = ARRAY_SIZE(twi0_resources),
663 static struct resource twi1_resources[] = {
665 .start = AT91SAM9G45_BASE_TWI1,
666 .end = AT91SAM9G45_BASE_TWI1 + SZ_16K - 1,
667 .flags = IORESOURCE_MEM,
670 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_TWI1,
671 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_TWI1,
672 .flags = IORESOURCE_IRQ,
676 static struct platform_device at91sam9g45_twi1_device = {
677 .name = "i2c-at91sam9g10",
679 .resource = twi1_resources,
680 .num_resources = ARRAY_SIZE(twi1_resources),
683 void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices)
685 i2c_register_board_info(i2c_id, devices, nr_devices);
687 /* pins used for TWI interface */
689 at91_set_A_periph(AT91_PIN_PA20, 0); /* TWD */
690 at91_set_A_periph(AT91_PIN_PA21, 0); /* TWCK */
692 platform_device_register(&at91sam9g45_twi0_device);
694 at91_set_A_periph(AT91_PIN_PB10, 0); /* TWD */
695 at91_set_A_periph(AT91_PIN_PB11, 0); /* TWCK */
697 platform_device_register(&at91sam9g45_twi1_device);
701 void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices) {}
705 /* --------------------------------------------------------------------
707 * -------------------------------------------------------------------- */
709 #if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
710 static u64 spi_dmamask = DMA_BIT_MASK(32);
712 static struct resource spi0_resources[] = {
714 .start = AT91SAM9G45_BASE_SPI0,
715 .end = AT91SAM9G45_BASE_SPI0 + SZ_16K - 1,
716 .flags = IORESOURCE_MEM,
719 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_SPI0,
720 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_SPI0,
721 .flags = IORESOURCE_IRQ,
725 static struct platform_device at91sam9g45_spi0_device = {
729 .dma_mask = &spi_dmamask,
730 .coherent_dma_mask = DMA_BIT_MASK(32),
732 .resource = spi0_resources,
733 .num_resources = ARRAY_SIZE(spi0_resources),
736 static const unsigned spi0_standard_cs[4] = { AT91_PIN_PB3, AT91_PIN_PB18, AT91_PIN_PB19, AT91_PIN_PD27 };
738 static struct resource spi1_resources[] = {
740 .start = AT91SAM9G45_BASE_SPI1,
741 .end = AT91SAM9G45_BASE_SPI1 + SZ_16K - 1,
742 .flags = IORESOURCE_MEM,
745 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_SPI1,
746 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_SPI1,
747 .flags = IORESOURCE_IRQ,
751 static struct platform_device at91sam9g45_spi1_device = {
755 .dma_mask = &spi_dmamask,
756 .coherent_dma_mask = DMA_BIT_MASK(32),
758 .resource = spi1_resources,
759 .num_resources = ARRAY_SIZE(spi1_resources),
762 static const unsigned spi1_standard_cs[4] = { AT91_PIN_PB17, AT91_PIN_PD28, AT91_PIN_PD18, AT91_PIN_PD19 };
764 void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
767 unsigned long cs_pin;
768 short enable_spi0 = 0;
769 short enable_spi1 = 0;
771 /* Choose SPI chip-selects */
772 for (i = 0; i < nr_devices; i++) {
773 if (devices[i].controller_data)
774 cs_pin = (unsigned long) devices[i].controller_data;
775 else if (devices[i].bus_num == 0)
776 cs_pin = spi0_standard_cs[devices[i].chip_select];
778 cs_pin = spi1_standard_cs[devices[i].chip_select];
780 if (!gpio_is_valid(cs_pin))
783 if (devices[i].bus_num == 0)
788 /* enable chip-select pin */
789 at91_set_gpio_output(cs_pin, 1);
791 /* pass chip-select pin to driver */
792 devices[i].controller_data = (void *) cs_pin;
795 spi_register_board_info(devices, nr_devices);
797 /* Configure SPI bus(es) */
799 at91_set_A_periph(AT91_PIN_PB0, 0); /* SPI0_MISO */
800 at91_set_A_periph(AT91_PIN_PB1, 0); /* SPI0_MOSI */
801 at91_set_A_periph(AT91_PIN_PB2, 0); /* SPI0_SPCK */
803 platform_device_register(&at91sam9g45_spi0_device);
806 at91_set_A_periph(AT91_PIN_PB14, 0); /* SPI1_MISO */
807 at91_set_A_periph(AT91_PIN_PB15, 0); /* SPI1_MOSI */
808 at91_set_A_periph(AT91_PIN_PB16, 0); /* SPI1_SPCK */
810 platform_device_register(&at91sam9g45_spi1_device);
814 void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
818 /* --------------------------------------------------------------------
820 * -------------------------------------------------------------------- */
822 #if defined(CONFIG_SND_ATMEL_AC97C) || defined(CONFIG_SND_ATMEL_AC97C_MODULE)
823 static u64 ac97_dmamask = DMA_BIT_MASK(32);
824 static struct ac97c_platform_data ac97_data;
826 static struct resource ac97_resources[] = {
828 .start = AT91SAM9G45_BASE_AC97C,
829 .end = AT91SAM9G45_BASE_AC97C + SZ_16K - 1,
830 .flags = IORESOURCE_MEM,
833 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_AC97C,
834 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_AC97C,
835 .flags = IORESOURCE_IRQ,
839 static struct platform_device at91sam9g45_ac97_device = {
840 .name = "atmel_ac97c",
843 .dma_mask = &ac97_dmamask,
844 .coherent_dma_mask = DMA_BIT_MASK(32),
845 .platform_data = &ac97_data,
847 .resource = ac97_resources,
848 .num_resources = ARRAY_SIZE(ac97_resources),
851 void __init at91_add_device_ac97(struct ac97c_platform_data *data)
856 at91_set_A_periph(AT91_PIN_PD8, 0); /* AC97FS */
857 at91_set_A_periph(AT91_PIN_PD9, 0); /* AC97CK */
858 at91_set_A_periph(AT91_PIN_PD7, 0); /* AC97TX */
859 at91_set_A_periph(AT91_PIN_PD6, 0); /* AC97RX */
862 if (gpio_is_valid(data->reset_pin))
863 at91_set_gpio_output(data->reset_pin, 0);
866 platform_device_register(&at91sam9g45_ac97_device);
869 void __init at91_add_device_ac97(struct ac97c_platform_data *data) {}
872 /* --------------------------------------------------------------------
873 * Image Sensor Interface
874 * -------------------------------------------------------------------- */
875 #if defined(CONFIG_VIDEO_ATMEL_ISI) || defined(CONFIG_VIDEO_ATMEL_ISI_MODULE)
876 static u64 isi_dmamask = DMA_BIT_MASK(32);
877 static struct isi_platform_data isi_data;
879 struct resource isi_resources[] = {
881 .start = AT91SAM9G45_BASE_ISI,
882 .end = AT91SAM9G45_BASE_ISI + SZ_16K - 1,
883 .flags = IORESOURCE_MEM,
886 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_ISI,
887 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_ISI,
888 .flags = IORESOURCE_IRQ,
892 static struct platform_device at91sam9g45_isi_device = {
896 .dma_mask = &isi_dmamask,
897 .coherent_dma_mask = DMA_BIT_MASK(32),
898 .platform_data = &isi_data,
900 .resource = isi_resources,
901 .num_resources = ARRAY_SIZE(isi_resources),
904 static struct clk_lookup isi_mck_lookups[] = {
905 CLKDEV_CON_DEV_ID("isi_mck", "atmel_isi.0", NULL),
908 void __init at91_add_device_isi(struct isi_platform_data *data,
918 at91_set_A_periph(AT91_PIN_PB20, 0); /* ISI_D0 */
919 at91_set_A_periph(AT91_PIN_PB21, 0); /* ISI_D1 */
920 at91_set_A_periph(AT91_PIN_PB22, 0); /* ISI_D2 */
921 at91_set_A_periph(AT91_PIN_PB23, 0); /* ISI_D3 */
922 at91_set_A_periph(AT91_PIN_PB24, 0); /* ISI_D4 */
923 at91_set_A_periph(AT91_PIN_PB25, 0); /* ISI_D5 */
924 at91_set_A_periph(AT91_PIN_PB26, 0); /* ISI_D6 */
925 at91_set_A_periph(AT91_PIN_PB27, 0); /* ISI_D7 */
926 at91_set_A_periph(AT91_PIN_PB28, 0); /* ISI_PCK */
927 at91_set_A_periph(AT91_PIN_PB30, 0); /* ISI_HSYNC */
928 at91_set_A_periph(AT91_PIN_PB29, 0); /* ISI_VSYNC */
929 at91_set_B_periph(AT91_PIN_PB8, 0); /* ISI_PD8 */
930 at91_set_B_periph(AT91_PIN_PB9, 0); /* ISI_PD9 */
931 at91_set_B_periph(AT91_PIN_PB10, 0); /* ISI_PD10 */
932 at91_set_B_periph(AT91_PIN_PB11, 0); /* ISI_PD11 */
934 platform_device_register(&at91sam9g45_isi_device);
936 if (use_pck_as_mck) {
937 at91_set_B_periph(AT91_PIN_PB31, 0); /* ISI_MCK (PCK1) */
939 pck = clk_get(NULL, "pck1");
940 parent = clk_get(NULL, "plla");
942 BUG_ON(IS_ERR(pck) || IS_ERR(parent));
944 if (clk_set_parent(pck, parent)) {
945 pr_err("Failed to set PCK's parent\n");
947 /* Register PCK as ISI_MCK */
948 isi_mck_lookups[0].clk = pck;
949 clkdev_add_table(isi_mck_lookups,
950 ARRAY_SIZE(isi_mck_lookups));
958 void __init at91_add_device_isi(struct isi_platform_data *data,
959 bool use_pck_as_mck) {}
963 /* --------------------------------------------------------------------
965 * -------------------------------------------------------------------- */
967 #if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
968 static u64 lcdc_dmamask = DMA_BIT_MASK(32);
969 static struct atmel_lcdfb_pdata lcdc_data;
971 static struct resource lcdc_resources[] = {
973 .start = AT91SAM9G45_LCDC_BASE,
974 .end = AT91SAM9G45_LCDC_BASE + SZ_4K - 1,
975 .flags = IORESOURCE_MEM,
978 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_LCDC,
979 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_LCDC,
980 .flags = IORESOURCE_IRQ,
984 static struct platform_device at91_lcdc_device = {
987 .dma_mask = &lcdc_dmamask,
988 .coherent_dma_mask = DMA_BIT_MASK(32),
989 .platform_data = &lcdc_data,
991 .resource = lcdc_resources,
992 .num_resources = ARRAY_SIZE(lcdc_resources),
995 void __init at91_add_device_lcdc(struct atmel_lcdfb_pdata *data)
1000 if (cpu_is_at91sam9g45es())
1001 at91_lcdc_device.name = "at91sam9g45es-lcdfb";
1003 at91_lcdc_device.name = "at91sam9g45-lcdfb";
1005 at91_set_A_periph(AT91_PIN_PE0, 0); /* LCDDPWR */
1007 at91_set_A_periph(AT91_PIN_PE2, 0); /* LCDCC */
1008 at91_set_A_periph(AT91_PIN_PE3, 0); /* LCDVSYNC */
1009 at91_set_A_periph(AT91_PIN_PE4, 0); /* LCDHSYNC */
1010 at91_set_A_periph(AT91_PIN_PE5, 0); /* LCDDOTCK */
1011 at91_set_A_periph(AT91_PIN_PE6, 0); /* LCDDEN */
1012 at91_set_A_periph(AT91_PIN_PE7, 0); /* LCDD0 */
1013 at91_set_A_periph(AT91_PIN_PE8, 0); /* LCDD1 */
1014 at91_set_A_periph(AT91_PIN_PE9, 0); /* LCDD2 */
1015 at91_set_A_periph(AT91_PIN_PE10, 0); /* LCDD3 */
1016 at91_set_A_periph(AT91_PIN_PE11, 0); /* LCDD4 */
1017 at91_set_A_periph(AT91_PIN_PE12, 0); /* LCDD5 */
1018 at91_set_A_periph(AT91_PIN_PE13, 0); /* LCDD6 */
1019 at91_set_A_periph(AT91_PIN_PE14, 0); /* LCDD7 */
1020 at91_set_A_periph(AT91_PIN_PE15, 0); /* LCDD8 */
1021 at91_set_A_periph(AT91_PIN_PE16, 0); /* LCDD9 */
1022 at91_set_A_periph(AT91_PIN_PE17, 0); /* LCDD10 */
1023 at91_set_A_periph(AT91_PIN_PE18, 0); /* LCDD11 */
1024 at91_set_A_periph(AT91_PIN_PE19, 0); /* LCDD12 */
1025 at91_set_A_periph(AT91_PIN_PE20, 0); /* LCDD13 */
1026 at91_set_A_periph(AT91_PIN_PE21, 0); /* LCDD14 */
1027 at91_set_A_periph(AT91_PIN_PE22, 0); /* LCDD15 */
1028 at91_set_A_periph(AT91_PIN_PE23, 0); /* LCDD16 */
1029 at91_set_A_periph(AT91_PIN_PE24, 0); /* LCDD17 */
1030 at91_set_A_periph(AT91_PIN_PE25, 0); /* LCDD18 */
1031 at91_set_A_periph(AT91_PIN_PE26, 0); /* LCDD19 */
1032 at91_set_A_periph(AT91_PIN_PE27, 0); /* LCDD20 */
1033 at91_set_A_periph(AT91_PIN_PE28, 0); /* LCDD21 */
1034 at91_set_A_periph(AT91_PIN_PE29, 0); /* LCDD22 */
1035 at91_set_A_periph(AT91_PIN_PE30, 0); /* LCDD23 */
1038 platform_device_register(&at91_lcdc_device);
1041 void __init at91_add_device_lcdc(struct atmel_lcdfb_pdata *data) {}
1045 /* --------------------------------------------------------------------
1046 * Timer/Counter block
1047 * -------------------------------------------------------------------- */
1049 #ifdef CONFIG_ATMEL_TCLIB
1050 static struct resource tcb0_resources[] = {
1052 .start = AT91SAM9G45_BASE_TCB0,
1053 .end = AT91SAM9G45_BASE_TCB0 + SZ_256 - 1,
1054 .flags = IORESOURCE_MEM,
1057 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_TCB,
1058 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_TCB,
1059 .flags = IORESOURCE_IRQ,
1063 static struct platform_device at91sam9g45_tcb0_device = {
1064 .name = "atmel_tcb",
1066 .resource = tcb0_resources,
1067 .num_resources = ARRAY_SIZE(tcb0_resources),
1070 /* TCB1 begins with TC3 */
1071 static struct resource tcb1_resources[] = {
1073 .start = AT91SAM9G45_BASE_TCB1,
1074 .end = AT91SAM9G45_BASE_TCB1 + SZ_256 - 1,
1075 .flags = IORESOURCE_MEM,
1078 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_TCB,
1079 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_TCB,
1080 .flags = IORESOURCE_IRQ,
1084 static struct platform_device at91sam9g45_tcb1_device = {
1085 .name = "atmel_tcb",
1087 .resource = tcb1_resources,
1088 .num_resources = ARRAY_SIZE(tcb1_resources),
1091 static void __init at91_add_device_tc(void)
1093 platform_device_register(&at91sam9g45_tcb0_device);
1094 platform_device_register(&at91sam9g45_tcb1_device);
1097 static void __init at91_add_device_tc(void) { }
1101 /* --------------------------------------------------------------------
1103 * -------------------------------------------------------------------- */
1105 #if defined(CONFIG_RTC_DRV_AT91RM9200) || defined(CONFIG_RTC_DRV_AT91RM9200_MODULE)
1106 static struct resource rtc_resources[] = {
1108 .start = AT91SAM9G45_BASE_RTC,
1109 .end = AT91SAM9G45_BASE_RTC + SZ_256 - 1,
1110 .flags = IORESOURCE_MEM,
1113 .start = NR_IRQS_LEGACY + AT91_ID_SYS,
1114 .end = NR_IRQS_LEGACY + AT91_ID_SYS,
1115 .flags = IORESOURCE_IRQ,
1119 static struct platform_device at91sam9g45_rtc_device = {
1122 .resource = rtc_resources,
1123 .num_resources = ARRAY_SIZE(rtc_resources),
1126 static void __init at91_add_device_rtc(void)
1128 platform_device_register(&at91sam9g45_rtc_device);
1131 static void __init at91_add_device_rtc(void) {}
1135 /* --------------------------------------------------------------------
1137 * -------------------------------------------------------------------- */
1139 #if defined(CONFIG_TOUCHSCREEN_ATMEL_TSADCC) || defined(CONFIG_TOUCHSCREEN_ATMEL_TSADCC_MODULE)
1140 static u64 tsadcc_dmamask = DMA_BIT_MASK(32);
1141 static struct at91_tsadcc_data tsadcc_data;
1143 static struct resource tsadcc_resources[] = {
1145 .start = AT91SAM9G45_BASE_TSC,
1146 .end = AT91SAM9G45_BASE_TSC + SZ_16K - 1,
1147 .flags = IORESOURCE_MEM,
1150 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_TSC,
1151 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_TSC,
1152 .flags = IORESOURCE_IRQ,
1156 static struct platform_device at91sam9g45_tsadcc_device = {
1157 .name = "atmel_tsadcc",
1160 .dma_mask = &tsadcc_dmamask,
1161 .coherent_dma_mask = DMA_BIT_MASK(32),
1162 .platform_data = &tsadcc_data,
1164 .resource = tsadcc_resources,
1165 .num_resources = ARRAY_SIZE(tsadcc_resources),
1168 void __init at91_add_device_tsadcc(struct at91_tsadcc_data *data)
1173 at91_set_gpio_input(AT91_PIN_PD20, 0); /* AD0_XR */
1174 at91_set_gpio_input(AT91_PIN_PD21, 0); /* AD1_XL */
1175 at91_set_gpio_input(AT91_PIN_PD22, 0); /* AD2_YT */
1176 at91_set_gpio_input(AT91_PIN_PD23, 0); /* AD3_TB */
1178 tsadcc_data = *data;
1179 platform_device_register(&at91sam9g45_tsadcc_device);
1182 void __init at91_add_device_tsadcc(struct at91_tsadcc_data *data) {}
1186 /* --------------------------------------------------------------------
1188 * -------------------------------------------------------------------- */
1190 #if IS_ENABLED(CONFIG_AT91_ADC)
1191 static struct at91_adc_data adc_data;
1193 static struct resource adc_resources[] = {
1195 .start = AT91SAM9G45_BASE_TSC,
1196 .end = AT91SAM9G45_BASE_TSC + SZ_16K - 1,
1197 .flags = IORESOURCE_MEM,
1200 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_TSC,
1201 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_TSC,
1202 .flags = IORESOURCE_IRQ,
1206 static struct platform_device at91_adc_device = {
1207 .name = "at91sam9g45-adc",
1210 .platform_data = &adc_data,
1212 .resource = adc_resources,
1213 .num_resources = ARRAY_SIZE(adc_resources),
1216 static struct at91_adc_trigger at91_adc_triggers[] = {
1218 .name = "external-rising",
1220 .is_external = true,
1223 .name = "external-falling",
1225 .is_external = true,
1228 .name = "external-any",
1230 .is_external = true,
1233 .name = "continuous",
1235 .is_external = false,
1239 static struct at91_adc_reg_desc at91_adc_register_g45 = {
1240 .channel_base = AT91_ADC_CHR(0),
1241 .drdy_mask = AT91_ADC_DRDY,
1242 .status_register = AT91_ADC_SR,
1243 .trigger_register = 0x08,
1246 void __init at91_add_device_adc(struct at91_adc_data *data)
1251 if (test_bit(0, &data->channels_used))
1252 at91_set_gpio_input(AT91_PIN_PD20, 0);
1253 if (test_bit(1, &data->channels_used))
1254 at91_set_gpio_input(AT91_PIN_PD21, 0);
1255 if (test_bit(2, &data->channels_used))
1256 at91_set_gpio_input(AT91_PIN_PD22, 0);
1257 if (test_bit(3, &data->channels_used))
1258 at91_set_gpio_input(AT91_PIN_PD23, 0);
1259 if (test_bit(4, &data->channels_used))
1260 at91_set_gpio_input(AT91_PIN_PD24, 0);
1261 if (test_bit(5, &data->channels_used))
1262 at91_set_gpio_input(AT91_PIN_PD25, 0);
1263 if (test_bit(6, &data->channels_used))
1264 at91_set_gpio_input(AT91_PIN_PD26, 0);
1265 if (test_bit(7, &data->channels_used))
1266 at91_set_gpio_input(AT91_PIN_PD27, 0);
1268 if (data->use_external_triggers)
1269 at91_set_A_periph(AT91_PIN_PD28, 0);
1271 data->num_channels = 8;
1272 data->startup_time = 40;
1273 data->registers = &at91_adc_register_g45;
1274 data->trigger_number = 4;
1275 data->trigger_list = at91_adc_triggers;
1278 platform_device_register(&at91_adc_device);
1281 void __init at91_add_device_adc(struct at91_adc_data *data) {}
1284 /* --------------------------------------------------------------------
1286 * -------------------------------------------------------------------- */
1288 static struct resource rtt_resources[] = {
1290 .start = AT91SAM9G45_BASE_RTT,
1291 .end = AT91SAM9G45_BASE_RTT + SZ_16 - 1,
1292 .flags = IORESOURCE_MEM,
1294 .flags = IORESOURCE_MEM,
1296 .flags = IORESOURCE_IRQ,
1300 static struct platform_device at91sam9g45_rtt_device = {
1303 .resource = rtt_resources,
1306 #if IS_ENABLED(CONFIG_RTC_DRV_AT91SAM9)
1307 static void __init at91_add_device_rtt_rtc(void)
1309 at91sam9g45_rtt_device.name = "rtc-at91sam9";
1311 * The second resource is needed:
1312 * GPBR will serve as the storage for RTC time offset
1314 at91sam9g45_rtt_device.num_resources = 3;
1315 rtt_resources[1].start = AT91SAM9G45_BASE_GPBR +
1316 4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
1317 rtt_resources[1].end = rtt_resources[1].start + 3;
1318 rtt_resources[2].start = NR_IRQS_LEGACY + AT91_ID_SYS;
1319 rtt_resources[2].end = NR_IRQS_LEGACY + AT91_ID_SYS;
1322 static void __init at91_add_device_rtt_rtc(void)
1324 /* Only one resource is needed: RTT not used as RTC */
1325 at91sam9g45_rtt_device.num_resources = 1;
1329 static void __init at91_add_device_rtt(void)
1331 at91_add_device_rtt_rtc();
1332 platform_device_register(&at91sam9g45_rtt_device);
1336 /* --------------------------------------------------------------------
1338 * -------------------------------------------------------------------- */
1340 #if defined(CONFIG_HW_RANDOM_ATMEL) || defined(CONFIG_HW_RANDOM_ATMEL_MODULE)
1341 static struct resource trng_resources[] = {
1343 .start = AT91SAM9G45_BASE_TRNG,
1344 .end = AT91SAM9G45_BASE_TRNG + SZ_16K - 1,
1345 .flags = IORESOURCE_MEM,
1349 static struct platform_device at91sam9g45_trng_device = {
1350 .name = "atmel-trng",
1352 .resource = trng_resources,
1353 .num_resources = ARRAY_SIZE(trng_resources),
1356 static void __init at91_add_device_trng(void)
1358 platform_device_register(&at91sam9g45_trng_device);
1361 static void __init at91_add_device_trng(void) {}
1364 /* --------------------------------------------------------------------
1366 * -------------------------------------------------------------------- */
1368 #if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
1369 static struct resource wdt_resources[] = {
1371 .start = AT91SAM9G45_BASE_WDT,
1372 .end = AT91SAM9G45_BASE_WDT + SZ_16 - 1,
1373 .flags = IORESOURCE_MEM,
1377 static struct platform_device at91sam9g45_wdt_device = {
1380 .resource = wdt_resources,
1381 .num_resources = ARRAY_SIZE(wdt_resources),
1384 static void __init at91_add_device_watchdog(void)
1386 platform_device_register(&at91sam9g45_wdt_device);
1389 static void __init at91_add_device_watchdog(void) {}
1393 /* --------------------------------------------------------------------
1395 * --------------------------------------------------------------------*/
1397 #if defined(CONFIG_ATMEL_PWM) || defined(CONFIG_ATMEL_PWM_MODULE)
1398 static u32 pwm_mask;
1400 static struct resource pwm_resources[] = {
1402 .start = AT91SAM9G45_BASE_PWMC,
1403 .end = AT91SAM9G45_BASE_PWMC + SZ_16K - 1,
1404 .flags = IORESOURCE_MEM,
1407 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_PWMC,
1408 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_PWMC,
1409 .flags = IORESOURCE_IRQ,
1413 static struct platform_device at91sam9g45_pwm0_device = {
1414 .name = "atmel_pwm",
1417 .platform_data = &pwm_mask,
1419 .resource = pwm_resources,
1420 .num_resources = ARRAY_SIZE(pwm_resources),
1423 void __init at91_add_device_pwm(u32 mask)
1425 if (mask & (1 << AT91_PWM0))
1426 at91_set_B_periph(AT91_PIN_PD24, 1); /* enable PWM0 */
1428 if (mask & (1 << AT91_PWM1))
1429 at91_set_B_periph(AT91_PIN_PD31, 1); /* enable PWM1 */
1431 if (mask & (1 << AT91_PWM2))
1432 at91_set_B_periph(AT91_PIN_PD26, 1); /* enable PWM2 */
1434 if (mask & (1 << AT91_PWM3))
1435 at91_set_B_periph(AT91_PIN_PD0, 1); /* enable PWM3 */
1439 platform_device_register(&at91sam9g45_pwm0_device);
1442 void __init at91_add_device_pwm(u32 mask) {}
1446 /* --------------------------------------------------------------------
1447 * SSC -- Synchronous Serial Controller
1448 * -------------------------------------------------------------------- */
1450 #if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE)
1451 static u64 ssc0_dmamask = DMA_BIT_MASK(32);
1453 static struct resource ssc0_resources[] = {
1455 .start = AT91SAM9G45_BASE_SSC0,
1456 .end = AT91SAM9G45_BASE_SSC0 + SZ_16K - 1,
1457 .flags = IORESOURCE_MEM,
1460 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_SSC0,
1461 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_SSC0,
1462 .flags = IORESOURCE_IRQ,
1466 static struct platform_device at91sam9g45_ssc0_device = {
1467 .name = "at91sam9g45_ssc",
1470 .dma_mask = &ssc0_dmamask,
1471 .coherent_dma_mask = DMA_BIT_MASK(32),
1473 .resource = ssc0_resources,
1474 .num_resources = ARRAY_SIZE(ssc0_resources),
1477 static inline void configure_ssc0_pins(unsigned pins)
1479 if (pins & ATMEL_SSC_TF)
1480 at91_set_A_periph(AT91_PIN_PD1, 1);
1481 if (pins & ATMEL_SSC_TK)
1482 at91_set_A_periph(AT91_PIN_PD0, 1);
1483 if (pins & ATMEL_SSC_TD)
1484 at91_set_A_periph(AT91_PIN_PD2, 1);
1485 if (pins & ATMEL_SSC_RD)
1486 at91_set_A_periph(AT91_PIN_PD3, 1);
1487 if (pins & ATMEL_SSC_RK)
1488 at91_set_A_periph(AT91_PIN_PD4, 1);
1489 if (pins & ATMEL_SSC_RF)
1490 at91_set_A_periph(AT91_PIN_PD5, 1);
1493 static u64 ssc1_dmamask = DMA_BIT_MASK(32);
1495 static struct resource ssc1_resources[] = {
1497 .start = AT91SAM9G45_BASE_SSC1,
1498 .end = AT91SAM9G45_BASE_SSC1 + SZ_16K - 1,
1499 .flags = IORESOURCE_MEM,
1502 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_SSC1,
1503 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_SSC1,
1504 .flags = IORESOURCE_IRQ,
1508 static struct platform_device at91sam9g45_ssc1_device = {
1509 .name = "at91sam9g45_ssc",
1512 .dma_mask = &ssc1_dmamask,
1513 .coherent_dma_mask = DMA_BIT_MASK(32),
1515 .resource = ssc1_resources,
1516 .num_resources = ARRAY_SIZE(ssc1_resources),
1519 static inline void configure_ssc1_pins(unsigned pins)
1521 if (pins & ATMEL_SSC_TF)
1522 at91_set_A_periph(AT91_PIN_PD14, 1);
1523 if (pins & ATMEL_SSC_TK)
1524 at91_set_A_periph(AT91_PIN_PD12, 1);
1525 if (pins & ATMEL_SSC_TD)
1526 at91_set_A_periph(AT91_PIN_PD10, 1);
1527 if (pins & ATMEL_SSC_RD)
1528 at91_set_A_periph(AT91_PIN_PD11, 1);
1529 if (pins & ATMEL_SSC_RK)
1530 at91_set_A_periph(AT91_PIN_PD13, 1);
1531 if (pins & ATMEL_SSC_RF)
1532 at91_set_A_periph(AT91_PIN_PD15, 1);
1536 * SSC controllers are accessed through library code, instead of any
1537 * kind of all-singing/all-dancing driver. For example one could be
1538 * used by a particular I2S audio codec's driver, while another one
1539 * on the same system might be used by a custom data capture driver.
1541 void __init at91_add_device_ssc(unsigned id, unsigned pins)
1543 struct platform_device *pdev;
1546 * NOTE: caller is responsible for passing information matching
1547 * "pins" to whatever will be using each particular controller.
1550 case AT91SAM9G45_ID_SSC0:
1551 pdev = &at91sam9g45_ssc0_device;
1552 configure_ssc0_pins(pins);
1554 case AT91SAM9G45_ID_SSC1:
1555 pdev = &at91sam9g45_ssc1_device;
1556 configure_ssc1_pins(pins);
1562 platform_device_register(pdev);
1566 void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
1570 /* --------------------------------------------------------------------
1572 * -------------------------------------------------------------------- */
1574 #if defined(CONFIG_SERIAL_ATMEL)
1575 static struct resource dbgu_resources[] = {
1577 .start = AT91SAM9G45_BASE_DBGU,
1578 .end = AT91SAM9G45_BASE_DBGU + SZ_512 - 1,
1579 .flags = IORESOURCE_MEM,
1582 .start = NR_IRQS_LEGACY + AT91_ID_SYS,
1583 .end = NR_IRQS_LEGACY + AT91_ID_SYS,
1584 .flags = IORESOURCE_IRQ,
1588 static struct atmel_uart_data dbgu_data = {
1591 .rts_gpio = -EINVAL,
1594 static u64 dbgu_dmamask = DMA_BIT_MASK(32);
1596 static struct platform_device at91sam9g45_dbgu_device = {
1597 .name = "atmel_usart",
1600 .dma_mask = &dbgu_dmamask,
1601 .coherent_dma_mask = DMA_BIT_MASK(32),
1602 .platform_data = &dbgu_data,
1604 .resource = dbgu_resources,
1605 .num_resources = ARRAY_SIZE(dbgu_resources),
1608 static inline void configure_dbgu_pins(void)
1610 at91_set_A_periph(AT91_PIN_PB12, 0); /* DRXD */
1611 at91_set_A_periph(AT91_PIN_PB13, 1); /* DTXD */
1614 static struct resource uart0_resources[] = {
1616 .start = AT91SAM9G45_BASE_US0,
1617 .end = AT91SAM9G45_BASE_US0 + SZ_16K - 1,
1618 .flags = IORESOURCE_MEM,
1621 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_US0,
1622 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_US0,
1623 .flags = IORESOURCE_IRQ,
1627 static struct atmel_uart_data uart0_data = {
1630 .rts_gpio = -EINVAL,
1633 static u64 uart0_dmamask = DMA_BIT_MASK(32);
1635 static struct platform_device at91sam9g45_uart0_device = {
1636 .name = "atmel_usart",
1639 .dma_mask = &uart0_dmamask,
1640 .coherent_dma_mask = DMA_BIT_MASK(32),
1641 .platform_data = &uart0_data,
1643 .resource = uart0_resources,
1644 .num_resources = ARRAY_SIZE(uart0_resources),
1647 static inline void configure_usart0_pins(unsigned pins)
1649 at91_set_A_periph(AT91_PIN_PB19, 1); /* TXD0 */
1650 at91_set_A_periph(AT91_PIN_PB18, 0); /* RXD0 */
1652 if (pins & ATMEL_UART_RTS)
1653 at91_set_B_periph(AT91_PIN_PB17, 0); /* RTS0 */
1654 if (pins & ATMEL_UART_CTS)
1655 at91_set_B_periph(AT91_PIN_PB15, 0); /* CTS0 */
1658 static struct resource uart1_resources[] = {
1660 .start = AT91SAM9G45_BASE_US1,
1661 .end = AT91SAM9G45_BASE_US1 + SZ_16K - 1,
1662 .flags = IORESOURCE_MEM,
1665 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_US1,
1666 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_US1,
1667 .flags = IORESOURCE_IRQ,
1671 static struct atmel_uart_data uart1_data = {
1674 .rts_gpio = -EINVAL,
1677 static u64 uart1_dmamask = DMA_BIT_MASK(32);
1679 static struct platform_device at91sam9g45_uart1_device = {
1680 .name = "atmel_usart",
1683 .dma_mask = &uart1_dmamask,
1684 .coherent_dma_mask = DMA_BIT_MASK(32),
1685 .platform_data = &uart1_data,
1687 .resource = uart1_resources,
1688 .num_resources = ARRAY_SIZE(uart1_resources),
1691 static inline void configure_usart1_pins(unsigned pins)
1693 at91_set_A_periph(AT91_PIN_PB4, 1); /* TXD1 */
1694 at91_set_A_periph(AT91_PIN_PB5, 0); /* RXD1 */
1696 if (pins & ATMEL_UART_RTS)
1697 at91_set_A_periph(AT91_PIN_PD16, 0); /* RTS1 */
1698 if (pins & ATMEL_UART_CTS)
1699 at91_set_A_periph(AT91_PIN_PD17, 0); /* CTS1 */
1702 static struct resource uart2_resources[] = {
1704 .start = AT91SAM9G45_BASE_US2,
1705 .end = AT91SAM9G45_BASE_US2 + SZ_16K - 1,
1706 .flags = IORESOURCE_MEM,
1709 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_US2,
1710 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_US2,
1711 .flags = IORESOURCE_IRQ,
1715 static struct atmel_uart_data uart2_data = {
1718 .rts_gpio = -EINVAL,
1721 static u64 uart2_dmamask = DMA_BIT_MASK(32);
1723 static struct platform_device at91sam9g45_uart2_device = {
1724 .name = "atmel_usart",
1727 .dma_mask = &uart2_dmamask,
1728 .coherent_dma_mask = DMA_BIT_MASK(32),
1729 .platform_data = &uart2_data,
1731 .resource = uart2_resources,
1732 .num_resources = ARRAY_SIZE(uart2_resources),
1735 static inline void configure_usart2_pins(unsigned pins)
1737 at91_set_A_periph(AT91_PIN_PB6, 1); /* TXD2 */
1738 at91_set_A_periph(AT91_PIN_PB7, 0); /* RXD2 */
1740 if (pins & ATMEL_UART_RTS)
1741 at91_set_B_periph(AT91_PIN_PC9, 0); /* RTS2 */
1742 if (pins & ATMEL_UART_CTS)
1743 at91_set_B_periph(AT91_PIN_PC11, 0); /* CTS2 */
1746 static struct resource uart3_resources[] = {
1748 .start = AT91SAM9G45_BASE_US3,
1749 .end = AT91SAM9G45_BASE_US3 + SZ_16K - 1,
1750 .flags = IORESOURCE_MEM,
1753 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_US3,
1754 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_US3,
1755 .flags = IORESOURCE_IRQ,
1759 static struct atmel_uart_data uart3_data = {
1762 .rts_gpio = -EINVAL,
1765 static u64 uart3_dmamask = DMA_BIT_MASK(32);
1767 static struct platform_device at91sam9g45_uart3_device = {
1768 .name = "atmel_usart",
1771 .dma_mask = &uart3_dmamask,
1772 .coherent_dma_mask = DMA_BIT_MASK(32),
1773 .platform_data = &uart3_data,
1775 .resource = uart3_resources,
1776 .num_resources = ARRAY_SIZE(uart3_resources),
1779 static inline void configure_usart3_pins(unsigned pins)
1781 at91_set_A_periph(AT91_PIN_PB8, 1); /* TXD3 */
1782 at91_set_A_periph(AT91_PIN_PB9, 0); /* RXD3 */
1784 if (pins & ATMEL_UART_RTS)
1785 at91_set_B_periph(AT91_PIN_PA23, 0); /* RTS3 */
1786 if (pins & ATMEL_UART_CTS)
1787 at91_set_B_periph(AT91_PIN_PA24, 0); /* CTS3 */
1790 static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
1792 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
1794 struct platform_device *pdev;
1795 struct atmel_uart_data *pdata;
1799 pdev = &at91sam9g45_dbgu_device;
1800 configure_dbgu_pins();
1802 case AT91SAM9G45_ID_US0:
1803 pdev = &at91sam9g45_uart0_device;
1804 configure_usart0_pins(pins);
1806 case AT91SAM9G45_ID_US1:
1807 pdev = &at91sam9g45_uart1_device;
1808 configure_usart1_pins(pins);
1810 case AT91SAM9G45_ID_US2:
1811 pdev = &at91sam9g45_uart2_device;
1812 configure_usart2_pins(pins);
1814 case AT91SAM9G45_ID_US3:
1815 pdev = &at91sam9g45_uart3_device;
1816 configure_usart3_pins(pins);
1821 pdata = pdev->dev.platform_data;
1822 pdata->num = portnr; /* update to mapped ID */
1824 if (portnr < ATMEL_MAX_UART)
1825 at91_uarts[portnr] = pdev;
1828 void __init at91_add_device_serial(void)
1832 for (i = 0; i < ATMEL_MAX_UART; i++) {
1834 platform_device_register(at91_uarts[i]);
1838 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
1839 void __init at91_add_device_serial(void) {}
1842 /* --------------------------------------------------------------------
1844 * -------------------------------------------------------------------- */
1846 #if defined(CONFIG_CRYPTO_DEV_ATMEL_SHA) || defined(CONFIG_CRYPTO_DEV_ATMEL_SHA_MODULE)
1847 static struct resource sha_resources[] = {
1849 .start = AT91SAM9G45_BASE_SHA,
1850 .end = AT91SAM9G45_BASE_SHA + SZ_16K - 1,
1851 .flags = IORESOURCE_MEM,
1854 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_AESTDESSHA,
1855 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_AESTDESSHA,
1856 .flags = IORESOURCE_IRQ,
1860 static struct platform_device at91sam9g45_sha_device = {
1861 .name = "atmel_sha",
1863 .resource = sha_resources,
1864 .num_resources = ARRAY_SIZE(sha_resources),
1867 static void __init at91_add_device_sha(void)
1869 platform_device_register(&at91sam9g45_sha_device);
1872 static void __init at91_add_device_sha(void) {}
1875 /* --------------------------------------------------------------------
1877 * -------------------------------------------------------------------- */
1879 #if defined(CONFIG_CRYPTO_DEV_ATMEL_TDES) || defined(CONFIG_CRYPTO_DEV_ATMEL_TDES_MODULE)
1880 static struct resource tdes_resources[] = {
1882 .start = AT91SAM9G45_BASE_TDES,
1883 .end = AT91SAM9G45_BASE_TDES + SZ_16K - 1,
1884 .flags = IORESOURCE_MEM,
1887 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_AESTDESSHA,
1888 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_AESTDESSHA,
1889 .flags = IORESOURCE_IRQ,
1893 static struct platform_device at91sam9g45_tdes_device = {
1894 .name = "atmel_tdes",
1896 .resource = tdes_resources,
1897 .num_resources = ARRAY_SIZE(tdes_resources),
1900 static void __init at91_add_device_tdes(void)
1902 platform_device_register(&at91sam9g45_tdes_device);
1905 static void __init at91_add_device_tdes(void) {}
1908 /* --------------------------------------------------------------------
1910 * -------------------------------------------------------------------- */
1912 #if defined(CONFIG_CRYPTO_DEV_ATMEL_AES) || defined(CONFIG_CRYPTO_DEV_ATMEL_AES_MODULE)
1913 static struct crypto_platform_data aes_data;
1914 static struct crypto_dma_data alt_atslave;
1915 static u64 aes_dmamask = DMA_BIT_MASK(32);
1917 static struct resource aes_resources[] = {
1919 .start = AT91SAM9G45_BASE_AES,
1920 .end = AT91SAM9G45_BASE_AES + SZ_16K - 1,
1921 .flags = IORESOURCE_MEM,
1924 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_AESTDESSHA,
1925 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_AESTDESSHA,
1926 .flags = IORESOURCE_IRQ,
1930 static struct platform_device at91sam9g45_aes_device = {
1931 .name = "atmel_aes",
1934 .dma_mask = &aes_dmamask,
1935 .coherent_dma_mask = DMA_BIT_MASK(32),
1936 .platform_data = &aes_data,
1938 .resource = aes_resources,
1939 .num_resources = ARRAY_SIZE(aes_resources),
1942 static void __init at91_add_device_aes(void)
1944 struct at_dma_slave *atslave;
1946 /* DMA TX slave channel configuration */
1947 atslave = &alt_atslave.txdata;
1948 atslave->dma_dev = &at_hdmac_device.dev;
1949 atslave->cfg = ATC_FIFOCFG_ENOUGHSPACE | ATC_SRC_H2SEL_HW |
1950 ATC_SRC_PER(AT_DMA_ID_AES_RX);
1952 /* DMA RX slave channel configuration */
1953 atslave = &alt_atslave.rxdata;
1954 atslave->dma_dev = &at_hdmac_device.dev;
1955 atslave->cfg = ATC_FIFOCFG_ENOUGHSPACE | ATC_DST_H2SEL_HW |
1956 ATC_DST_PER(AT_DMA_ID_AES_TX);
1958 aes_data.dma_slave = &alt_atslave;
1959 platform_device_register(&at91sam9g45_aes_device);
1962 static void __init at91_add_device_aes(void) {}
1965 /* -------------------------------------------------------------------- */
1967 * These devices are always present and don't need any board-specific
1970 static int __init at91_add_standard_devices(void)
1972 if (of_have_populated_dt())
1975 at91_add_device_hdmac();
1976 at91_add_device_rtc();
1977 at91_add_device_rtt();
1978 at91_add_device_trng();
1979 at91_add_device_watchdog();
1980 at91_add_device_tc();
1981 at91_add_device_sha();
1982 at91_add_device_tdes();
1983 at91_add_device_aes();
1987 arch_initcall(at91_add_standard_devices);