2 * On-Chip devices setup code for the AT91SAM9G45 family
4 * Copyright (C) 2009 Atmel Corporation.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
12 #include <asm/mach/arch.h>
13 #include <asm/mach/map.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/gpio.h>
17 #include <linux/platform_device.h>
18 #include <linux/i2c-gpio.h>
19 #include <linux/atmel-mci.h>
22 #include <video/atmel_lcdc.h>
24 #include <mach/board.h>
25 #include <mach/at91sam9g45.h>
26 #include <mach/at91sam9g45_matrix.h>
27 #include <mach/at91sam9_smc.h>
28 #include <mach/at_hdmac.h>
29 #include <mach/atmel-mci.h>
34 /* --------------------------------------------------------------------
35 * HDMAC - AHB DMA Controller
36 * -------------------------------------------------------------------- */
38 #if defined(CONFIG_AT_HDMAC) || defined(CONFIG_AT_HDMAC_MODULE)
39 static u64 hdmac_dmamask = DMA_BIT_MASK(32);
41 static struct at_dma_platform_data atdma_pdata = {
45 static struct resource hdmac_resources[] = {
47 .start = AT91SAM9G45_BASE_DMA,
48 .end = AT91SAM9G45_BASE_DMA + SZ_512 - 1,
49 .flags = IORESOURCE_MEM,
52 .start = AT91SAM9G45_ID_DMA,
53 .end = AT91SAM9G45_ID_DMA,
54 .flags = IORESOURCE_IRQ,
58 static struct platform_device at_hdmac_device = {
62 .dma_mask = &hdmac_dmamask,
63 .coherent_dma_mask = DMA_BIT_MASK(32),
64 .platform_data = &atdma_pdata,
66 .resource = hdmac_resources,
67 .num_resources = ARRAY_SIZE(hdmac_resources),
70 void __init at91_add_device_hdmac(void)
72 dma_cap_set(DMA_MEMCPY, atdma_pdata.cap_mask);
73 dma_cap_set(DMA_SLAVE, atdma_pdata.cap_mask);
74 platform_device_register(&at_hdmac_device);
77 void __init at91_add_device_hdmac(void) {}
81 /* --------------------------------------------------------------------
83 * -------------------------------------------------------------------- */
85 #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
86 static u64 ohci_dmamask = DMA_BIT_MASK(32);
87 static struct at91_usbh_data usbh_ohci_data;
89 static struct resource usbh_ohci_resources[] = {
91 .start = AT91SAM9G45_OHCI_BASE,
92 .end = AT91SAM9G45_OHCI_BASE + SZ_1M - 1,
93 .flags = IORESOURCE_MEM,
96 .start = AT91SAM9G45_ID_UHPHS,
97 .end = AT91SAM9G45_ID_UHPHS,
98 .flags = IORESOURCE_IRQ,
102 static struct platform_device at91_usbh_ohci_device = {
106 .dma_mask = &ohci_dmamask,
107 .coherent_dma_mask = DMA_BIT_MASK(32),
108 .platform_data = &usbh_ohci_data,
110 .resource = usbh_ohci_resources,
111 .num_resources = ARRAY_SIZE(usbh_ohci_resources),
114 void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data)
121 /* Enable VBus control for UHP ports */
122 for (i = 0; i < data->ports; i++) {
123 if (gpio_is_valid(data->vbus_pin[i]))
124 at91_set_gpio_output(data->vbus_pin[i], 0);
127 /* Enable overcurrent notification */
128 for (i = 0; i < data->ports; i++) {
129 if (data->overcurrent_pin[i])
130 at91_set_gpio_input(data->overcurrent_pin[i], 1);
133 usbh_ohci_data = *data;
134 platform_device_register(&at91_usbh_ohci_device);
137 void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data) {}
141 /* --------------------------------------------------------------------
143 * Needs an OHCI host for low and full speed management
144 * -------------------------------------------------------------------- */
146 #if defined(CONFIG_USB_EHCI_HCD) || defined(CONFIG_USB_EHCI_HCD_MODULE)
147 static u64 ehci_dmamask = DMA_BIT_MASK(32);
148 static struct at91_usbh_data usbh_ehci_data;
150 static struct resource usbh_ehci_resources[] = {
152 .start = AT91SAM9G45_EHCI_BASE,
153 .end = AT91SAM9G45_EHCI_BASE + SZ_1M - 1,
154 .flags = IORESOURCE_MEM,
157 .start = AT91SAM9G45_ID_UHPHS,
158 .end = AT91SAM9G45_ID_UHPHS,
159 .flags = IORESOURCE_IRQ,
163 static struct platform_device at91_usbh_ehci_device = {
164 .name = "atmel-ehci",
167 .dma_mask = &ehci_dmamask,
168 .coherent_dma_mask = DMA_BIT_MASK(32),
169 .platform_data = &usbh_ehci_data,
171 .resource = usbh_ehci_resources,
172 .num_resources = ARRAY_SIZE(usbh_ehci_resources),
175 void __init at91_add_device_usbh_ehci(struct at91_usbh_data *data)
182 /* Enable VBus control for UHP ports */
183 for (i = 0; i < data->ports; i++) {
184 if (gpio_is_valid(data->vbus_pin[i]))
185 at91_set_gpio_output(data->vbus_pin[i], 0);
188 usbh_ehci_data = *data;
189 platform_device_register(&at91_usbh_ehci_device);
192 void __init at91_add_device_usbh_ehci(struct at91_usbh_data *data) {}
196 /* --------------------------------------------------------------------
197 * USB HS Device (Gadget)
198 * -------------------------------------------------------------------- */
200 #if defined(CONFIG_USB_ATMEL_USBA) || defined(CONFIG_USB_ATMEL_USBA_MODULE)
201 static struct resource usba_udc_resources[] = {
203 .start = AT91SAM9G45_UDPHS_FIFO,
204 .end = AT91SAM9G45_UDPHS_FIFO + SZ_512K - 1,
205 .flags = IORESOURCE_MEM,
208 .start = AT91SAM9G45_BASE_UDPHS,
209 .end = AT91SAM9G45_BASE_UDPHS + SZ_1K - 1,
210 .flags = IORESOURCE_MEM,
213 .start = AT91SAM9G45_ID_UDPHS,
214 .end = AT91SAM9G45_ID_UDPHS,
215 .flags = IORESOURCE_IRQ,
219 #define EP(nam, idx, maxpkt, maxbk, dma, isoc) \
223 .fifo_size = maxpkt, \
229 static struct usba_ep_data usba_udc_ep[] __initdata = {
230 EP("ep0", 0, 64, 1, 0, 0),
231 EP("ep1", 1, 1024, 2, 1, 1),
232 EP("ep2", 2, 1024, 2, 1, 1),
233 EP("ep3", 3, 1024, 3, 1, 0),
234 EP("ep4", 4, 1024, 3, 1, 0),
235 EP("ep5", 5, 1024, 3, 1, 1),
236 EP("ep6", 6, 1024, 3, 1, 1),
242 * pdata doesn't have room for any endpoints, so we need to
243 * append room for the ones we need right after it.
246 struct usba_platform_data pdata;
247 struct usba_ep_data ep[7];
250 static struct platform_device at91_usba_udc_device = {
251 .name = "atmel_usba_udc",
254 .platform_data = &usba_udc_data.pdata,
256 .resource = usba_udc_resources,
257 .num_resources = ARRAY_SIZE(usba_udc_resources),
260 void __init at91_add_device_usba(struct usba_platform_data *data)
262 usba_udc_data.pdata.vbus_pin = -EINVAL;
263 usba_udc_data.pdata.num_ep = ARRAY_SIZE(usba_udc_ep);
264 memcpy(usba_udc_data.ep, usba_udc_ep, sizeof(usba_udc_ep));
266 if (data && gpio_is_valid(data->vbus_pin)) {
267 at91_set_gpio_input(data->vbus_pin, 0);
268 at91_set_deglitch(data->vbus_pin, 1);
269 usba_udc_data.pdata.vbus_pin = data->vbus_pin;
272 /* Pullup pin is handled internally by USB device peripheral */
274 platform_device_register(&at91_usba_udc_device);
277 void __init at91_add_device_usba(struct usba_platform_data *data) {}
281 /* --------------------------------------------------------------------
283 * -------------------------------------------------------------------- */
285 #if defined(CONFIG_MACB) || defined(CONFIG_MACB_MODULE)
286 static u64 eth_dmamask = DMA_BIT_MASK(32);
287 static struct macb_platform_data eth_data;
289 static struct resource eth_resources[] = {
291 .start = AT91SAM9G45_BASE_EMAC,
292 .end = AT91SAM9G45_BASE_EMAC + SZ_16K - 1,
293 .flags = IORESOURCE_MEM,
296 .start = AT91SAM9G45_ID_EMAC,
297 .end = AT91SAM9G45_ID_EMAC,
298 .flags = IORESOURCE_IRQ,
302 static struct platform_device at91sam9g45_eth_device = {
306 .dma_mask = ð_dmamask,
307 .coherent_dma_mask = DMA_BIT_MASK(32),
308 .platform_data = ð_data,
310 .resource = eth_resources,
311 .num_resources = ARRAY_SIZE(eth_resources),
314 void __init at91_add_device_eth(struct macb_platform_data *data)
319 if (gpio_is_valid(data->phy_irq_pin)) {
320 at91_set_gpio_input(data->phy_irq_pin, 0);
321 at91_set_deglitch(data->phy_irq_pin, 1);
324 /* Pins used for MII and RMII */
325 at91_set_A_periph(AT91_PIN_PA17, 0); /* ETXCK_EREFCK */
326 at91_set_A_periph(AT91_PIN_PA15, 0); /* ERXDV */
327 at91_set_A_periph(AT91_PIN_PA12, 0); /* ERX0 */
328 at91_set_A_periph(AT91_PIN_PA13, 0); /* ERX1 */
329 at91_set_A_periph(AT91_PIN_PA16, 0); /* ERXER */
330 at91_set_A_periph(AT91_PIN_PA14, 0); /* ETXEN */
331 at91_set_A_periph(AT91_PIN_PA10, 0); /* ETX0 */
332 at91_set_A_periph(AT91_PIN_PA11, 0); /* ETX1 */
333 at91_set_A_periph(AT91_PIN_PA19, 0); /* EMDIO */
334 at91_set_A_periph(AT91_PIN_PA18, 0); /* EMDC */
336 if (!data->is_rmii) {
337 at91_set_B_periph(AT91_PIN_PA29, 0); /* ECRS */
338 at91_set_B_periph(AT91_PIN_PA30, 0); /* ECOL */
339 at91_set_B_periph(AT91_PIN_PA8, 0); /* ERX2 */
340 at91_set_B_periph(AT91_PIN_PA9, 0); /* ERX3 */
341 at91_set_B_periph(AT91_PIN_PA28, 0); /* ERXCK */
342 at91_set_B_periph(AT91_PIN_PA6, 0); /* ETX2 */
343 at91_set_B_periph(AT91_PIN_PA7, 0); /* ETX3 */
344 at91_set_B_periph(AT91_PIN_PA27, 0); /* ETXER */
348 platform_device_register(&at91sam9g45_eth_device);
351 void __init at91_add_device_eth(struct macb_platform_data *data) {}
355 /* --------------------------------------------------------------------
357 * -------------------------------------------------------------------- */
359 #if defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_ATMELMCI_MODULE)
360 static u64 mmc_dmamask = DMA_BIT_MASK(32);
361 static struct mci_platform_data mmc0_data, mmc1_data;
363 static struct resource mmc0_resources[] = {
365 .start = AT91SAM9G45_BASE_MCI0,
366 .end = AT91SAM9G45_BASE_MCI0 + SZ_16K - 1,
367 .flags = IORESOURCE_MEM,
370 .start = AT91SAM9G45_ID_MCI0,
371 .end = AT91SAM9G45_ID_MCI0,
372 .flags = IORESOURCE_IRQ,
376 static struct platform_device at91sam9g45_mmc0_device = {
380 .dma_mask = &mmc_dmamask,
381 .coherent_dma_mask = DMA_BIT_MASK(32),
382 .platform_data = &mmc0_data,
384 .resource = mmc0_resources,
385 .num_resources = ARRAY_SIZE(mmc0_resources),
388 static struct resource mmc1_resources[] = {
390 .start = AT91SAM9G45_BASE_MCI1,
391 .end = AT91SAM9G45_BASE_MCI1 + SZ_16K - 1,
392 .flags = IORESOURCE_MEM,
395 .start = AT91SAM9G45_ID_MCI1,
396 .end = AT91SAM9G45_ID_MCI1,
397 .flags = IORESOURCE_IRQ,
401 static struct platform_device at91sam9g45_mmc1_device = {
405 .dma_mask = &mmc_dmamask,
406 .coherent_dma_mask = DMA_BIT_MASK(32),
407 .platform_data = &mmc1_data,
409 .resource = mmc1_resources,
410 .num_resources = ARRAY_SIZE(mmc1_resources),
413 /* Consider only one slot : slot 0 */
414 void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data)
420 /* Must have at least one usable slot */
421 if (!data->slot[0].bus_width)
424 #if defined(CONFIG_AT_HDMAC) || defined(CONFIG_AT_HDMAC_MODULE)
426 struct at_dma_slave *atslave;
427 struct mci_dma_data *alt_atslave;
429 alt_atslave = kzalloc(sizeof(struct mci_dma_data), GFP_KERNEL);
430 atslave = &alt_atslave->sdata;
432 /* DMA slave channel configuration */
433 atslave->dma_dev = &at_hdmac_device.dev;
434 atslave->reg_width = AT_DMA_SLAVE_WIDTH_32BIT;
435 atslave->cfg = ATC_FIFOCFG_HALFFIFO
436 | ATC_SRC_H2SEL_HW | ATC_DST_H2SEL_HW;
437 atslave->ctrla = ATC_SCSIZE_16 | ATC_DCSIZE_16;
438 if (mmc_id == 0) /* MCI0 */
439 atslave->cfg |= ATC_SRC_PER(AT_DMA_ID_MCI0)
440 | ATC_DST_PER(AT_DMA_ID_MCI0);
443 atslave->cfg |= ATC_SRC_PER(AT_DMA_ID_MCI1)
444 | ATC_DST_PER(AT_DMA_ID_MCI1);
446 data->dma_slave = alt_atslave;
452 if (gpio_is_valid(data->slot[0].detect_pin)) {
453 at91_set_gpio_input(data->slot[0].detect_pin, 1);
454 at91_set_deglitch(data->slot[0].detect_pin, 1);
456 if (gpio_is_valid(data->slot[0].wp_pin))
457 at91_set_gpio_input(data->slot[0].wp_pin, 1);
459 if (mmc_id == 0) { /* MCI0 */
462 at91_set_A_periph(AT91_PIN_PA0, 0);
465 at91_set_A_periph(AT91_PIN_PA1, 1);
467 /* DAT0, maybe DAT1..DAT3 and maybe DAT4..DAT7 */
468 at91_set_A_periph(AT91_PIN_PA2, 1);
469 if (data->slot[0].bus_width == 4) {
470 at91_set_A_periph(AT91_PIN_PA3, 1);
471 at91_set_A_periph(AT91_PIN_PA4, 1);
472 at91_set_A_periph(AT91_PIN_PA5, 1);
473 if (data->slot[0].bus_width == 8) {
474 at91_set_A_periph(AT91_PIN_PA6, 1);
475 at91_set_A_periph(AT91_PIN_PA7, 1);
476 at91_set_A_periph(AT91_PIN_PA8, 1);
477 at91_set_A_periph(AT91_PIN_PA9, 1);
482 platform_device_register(&at91sam9g45_mmc0_device);
487 at91_set_A_periph(AT91_PIN_PA31, 0);
490 at91_set_A_periph(AT91_PIN_PA22, 1);
492 /* DAT0, maybe DAT1..DAT3 and maybe DAT4..DAT7 */
493 at91_set_A_periph(AT91_PIN_PA23, 1);
494 if (data->slot[0].bus_width == 4) {
495 at91_set_A_periph(AT91_PIN_PA24, 1);
496 at91_set_A_periph(AT91_PIN_PA25, 1);
497 at91_set_A_periph(AT91_PIN_PA26, 1);
498 if (data->slot[0].bus_width == 8) {
499 at91_set_A_periph(AT91_PIN_PA27, 1);
500 at91_set_A_periph(AT91_PIN_PA28, 1);
501 at91_set_A_periph(AT91_PIN_PA29, 1);
502 at91_set_A_periph(AT91_PIN_PA30, 1);
507 platform_device_register(&at91sam9g45_mmc1_device);
512 void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data) {}
516 /* --------------------------------------------------------------------
518 * -------------------------------------------------------------------- */
520 #if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE)
521 static struct atmel_nand_data nand_data;
523 #define NAND_BASE AT91_CHIPSELECT_3
525 static struct resource nand_resources[] = {
528 .end = NAND_BASE + SZ_256M - 1,
529 .flags = IORESOURCE_MEM,
532 .start = AT91SAM9G45_BASE_ECC,
533 .end = AT91SAM9G45_BASE_ECC + SZ_512 - 1,
534 .flags = IORESOURCE_MEM,
538 static struct platform_device at91sam9g45_nand_device = {
539 .name = "atmel_nand",
542 .platform_data = &nand_data,
544 .resource = nand_resources,
545 .num_resources = ARRAY_SIZE(nand_resources),
548 void __init at91_add_device_nand(struct atmel_nand_data *data)
555 csa = at91_sys_read(AT91_MATRIX_EBICSA);
556 at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA);
559 if (gpio_is_valid(data->enable_pin))
560 at91_set_gpio_output(data->enable_pin, 1);
563 if (gpio_is_valid(data->rdy_pin))
564 at91_set_gpio_input(data->rdy_pin, 1);
566 /* card detect pin */
567 if (gpio_is_valid(data->det_pin))
568 at91_set_gpio_input(data->det_pin, 1);
571 platform_device_register(&at91sam9g45_nand_device);
574 void __init at91_add_device_nand(struct atmel_nand_data *data) {}
578 /* --------------------------------------------------------------------
580 * -------------------------------------------------------------------- */
583 * Prefer the GPIO code since the TWI controller isn't robust
584 * (gets overruns and underruns under load) and can only issue
585 * repeated STARTs in one scenario (the driver doesn't yet handle them).
587 #if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
588 static struct i2c_gpio_platform_data pdata_i2c0 = {
589 .sda_pin = AT91_PIN_PA20,
590 .sda_is_open_drain = 1,
591 .scl_pin = AT91_PIN_PA21,
592 .scl_is_open_drain = 1,
593 .udelay = 5, /* ~100 kHz */
596 static struct platform_device at91sam9g45_twi0_device = {
599 .dev.platform_data = &pdata_i2c0,
602 static struct i2c_gpio_platform_data pdata_i2c1 = {
603 .sda_pin = AT91_PIN_PB10,
604 .sda_is_open_drain = 1,
605 .scl_pin = AT91_PIN_PB11,
606 .scl_is_open_drain = 1,
607 .udelay = 5, /* ~100 kHz */
610 static struct platform_device at91sam9g45_twi1_device = {
613 .dev.platform_data = &pdata_i2c1,
616 void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices)
618 i2c_register_board_info(i2c_id, devices, nr_devices);
621 at91_set_GPIO_periph(AT91_PIN_PA20, 1); /* TWD (SDA) */
622 at91_set_multi_drive(AT91_PIN_PA20, 1);
624 at91_set_GPIO_periph(AT91_PIN_PA21, 1); /* TWCK (SCL) */
625 at91_set_multi_drive(AT91_PIN_PA21, 1);
627 platform_device_register(&at91sam9g45_twi0_device);
629 at91_set_GPIO_periph(AT91_PIN_PB10, 1); /* TWD (SDA) */
630 at91_set_multi_drive(AT91_PIN_PB10, 1);
632 at91_set_GPIO_periph(AT91_PIN_PB11, 1); /* TWCK (SCL) */
633 at91_set_multi_drive(AT91_PIN_PB11, 1);
635 platform_device_register(&at91sam9g45_twi1_device);
639 #elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
640 static struct resource twi0_resources[] = {
642 .start = AT91SAM9G45_BASE_TWI0,
643 .end = AT91SAM9G45_BASE_TWI0 + SZ_16K - 1,
644 .flags = IORESOURCE_MEM,
647 .start = AT91SAM9G45_ID_TWI0,
648 .end = AT91SAM9G45_ID_TWI0,
649 .flags = IORESOURCE_IRQ,
653 static struct platform_device at91sam9g45_twi0_device = {
656 .resource = twi0_resources,
657 .num_resources = ARRAY_SIZE(twi0_resources),
660 static struct resource twi1_resources[] = {
662 .start = AT91SAM9G45_BASE_TWI1,
663 .end = AT91SAM9G45_BASE_TWI1 + SZ_16K - 1,
664 .flags = IORESOURCE_MEM,
667 .start = AT91SAM9G45_ID_TWI1,
668 .end = AT91SAM9G45_ID_TWI1,
669 .flags = IORESOURCE_IRQ,
673 static struct platform_device at91sam9g45_twi1_device = {
676 .resource = twi1_resources,
677 .num_resources = ARRAY_SIZE(twi1_resources),
680 void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices)
682 i2c_register_board_info(i2c_id, devices, nr_devices);
684 /* pins used for TWI interface */
686 at91_set_A_periph(AT91_PIN_PA20, 0); /* TWD */
687 at91_set_multi_drive(AT91_PIN_PA20, 1);
689 at91_set_A_periph(AT91_PIN_PA21, 0); /* TWCK */
690 at91_set_multi_drive(AT91_PIN_PA21, 1);
692 platform_device_register(&at91sam9g45_twi0_device);
694 at91_set_A_periph(AT91_PIN_PB10, 0); /* TWD */
695 at91_set_multi_drive(AT91_PIN_PB10, 1);
697 at91_set_A_periph(AT91_PIN_PB11, 0); /* TWCK */
698 at91_set_multi_drive(AT91_PIN_PB11, 1);
700 platform_device_register(&at91sam9g45_twi1_device);
704 void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices) {}
708 /* --------------------------------------------------------------------
710 * -------------------------------------------------------------------- */
712 #if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
713 static u64 spi_dmamask = DMA_BIT_MASK(32);
715 static struct resource spi0_resources[] = {
717 .start = AT91SAM9G45_BASE_SPI0,
718 .end = AT91SAM9G45_BASE_SPI0 + SZ_16K - 1,
719 .flags = IORESOURCE_MEM,
722 .start = AT91SAM9G45_ID_SPI0,
723 .end = AT91SAM9G45_ID_SPI0,
724 .flags = IORESOURCE_IRQ,
728 static struct platform_device at91sam9g45_spi0_device = {
732 .dma_mask = &spi_dmamask,
733 .coherent_dma_mask = DMA_BIT_MASK(32),
735 .resource = spi0_resources,
736 .num_resources = ARRAY_SIZE(spi0_resources),
739 static const unsigned spi0_standard_cs[4] = { AT91_PIN_PB3, AT91_PIN_PB18, AT91_PIN_PB19, AT91_PIN_PD27 };
741 static struct resource spi1_resources[] = {
743 .start = AT91SAM9G45_BASE_SPI1,
744 .end = AT91SAM9G45_BASE_SPI1 + SZ_16K - 1,
745 .flags = IORESOURCE_MEM,
748 .start = AT91SAM9G45_ID_SPI1,
749 .end = AT91SAM9G45_ID_SPI1,
750 .flags = IORESOURCE_IRQ,
754 static struct platform_device at91sam9g45_spi1_device = {
758 .dma_mask = &spi_dmamask,
759 .coherent_dma_mask = DMA_BIT_MASK(32),
761 .resource = spi1_resources,
762 .num_resources = ARRAY_SIZE(spi1_resources),
765 static const unsigned spi1_standard_cs[4] = { AT91_PIN_PB17, AT91_PIN_PD28, AT91_PIN_PD18, AT91_PIN_PD19 };
767 void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
770 unsigned long cs_pin;
771 short enable_spi0 = 0;
772 short enable_spi1 = 0;
774 /* Choose SPI chip-selects */
775 for (i = 0; i < nr_devices; i++) {
776 if (devices[i].controller_data)
777 cs_pin = (unsigned long) devices[i].controller_data;
778 else if (devices[i].bus_num == 0)
779 cs_pin = spi0_standard_cs[devices[i].chip_select];
781 cs_pin = spi1_standard_cs[devices[i].chip_select];
783 if (devices[i].bus_num == 0)
788 /* enable chip-select pin */
789 at91_set_gpio_output(cs_pin, 1);
791 /* pass chip-select pin to driver */
792 devices[i].controller_data = (void *) cs_pin;
795 spi_register_board_info(devices, nr_devices);
797 /* Configure SPI bus(es) */
799 at91_set_A_periph(AT91_PIN_PB0, 0); /* SPI0_MISO */
800 at91_set_A_periph(AT91_PIN_PB1, 0); /* SPI0_MOSI */
801 at91_set_A_periph(AT91_PIN_PB2, 0); /* SPI0_SPCK */
803 platform_device_register(&at91sam9g45_spi0_device);
806 at91_set_A_periph(AT91_PIN_PB14, 0); /* SPI1_MISO */
807 at91_set_A_periph(AT91_PIN_PB15, 0); /* SPI1_MOSI */
808 at91_set_A_periph(AT91_PIN_PB16, 0); /* SPI1_SPCK */
810 platform_device_register(&at91sam9g45_spi1_device);
814 void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
818 /* --------------------------------------------------------------------
820 * -------------------------------------------------------------------- */
822 #if defined(CONFIG_SND_ATMEL_AC97C) || defined(CONFIG_SND_ATMEL_AC97C_MODULE)
823 static u64 ac97_dmamask = DMA_BIT_MASK(32);
824 static struct ac97c_platform_data ac97_data;
826 static struct resource ac97_resources[] = {
828 .start = AT91SAM9G45_BASE_AC97C,
829 .end = AT91SAM9G45_BASE_AC97C + SZ_16K - 1,
830 .flags = IORESOURCE_MEM,
833 .start = AT91SAM9G45_ID_AC97C,
834 .end = AT91SAM9G45_ID_AC97C,
835 .flags = IORESOURCE_IRQ,
839 static struct platform_device at91sam9g45_ac97_device = {
840 .name = "atmel_ac97c",
843 .dma_mask = &ac97_dmamask,
844 .coherent_dma_mask = DMA_BIT_MASK(32),
845 .platform_data = &ac97_data,
847 .resource = ac97_resources,
848 .num_resources = ARRAY_SIZE(ac97_resources),
851 void __init at91_add_device_ac97(struct ac97c_platform_data *data)
856 at91_set_A_periph(AT91_PIN_PD8, 0); /* AC97FS */
857 at91_set_A_periph(AT91_PIN_PD9, 0); /* AC97CK */
858 at91_set_A_periph(AT91_PIN_PD7, 0); /* AC97TX */
859 at91_set_A_periph(AT91_PIN_PD6, 0); /* AC97RX */
862 if (gpio_is_valid(data->reset_pin))
863 at91_set_gpio_output(data->reset_pin, 0);
866 platform_device_register(&at91sam9g45_ac97_device);
869 void __init at91_add_device_ac97(struct ac97c_platform_data *data) {}
873 /* --------------------------------------------------------------------
875 * -------------------------------------------------------------------- */
877 #if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
878 static u64 lcdc_dmamask = DMA_BIT_MASK(32);
879 static struct atmel_lcdfb_info lcdc_data;
881 static struct resource lcdc_resources[] = {
883 .start = AT91SAM9G45_LCDC_BASE,
884 .end = AT91SAM9G45_LCDC_BASE + SZ_4K - 1,
885 .flags = IORESOURCE_MEM,
888 .start = AT91SAM9G45_ID_LCDC,
889 .end = AT91SAM9G45_ID_LCDC,
890 .flags = IORESOURCE_IRQ,
894 static struct platform_device at91_lcdc_device = {
895 .name = "atmel_lcdfb",
898 .dma_mask = &lcdc_dmamask,
899 .coherent_dma_mask = DMA_BIT_MASK(32),
900 .platform_data = &lcdc_data,
902 .resource = lcdc_resources,
903 .num_resources = ARRAY_SIZE(lcdc_resources),
906 void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
911 at91_set_A_periph(AT91_PIN_PE0, 0); /* LCDDPWR */
913 at91_set_A_periph(AT91_PIN_PE2, 0); /* LCDCC */
914 at91_set_A_periph(AT91_PIN_PE3, 0); /* LCDVSYNC */
915 at91_set_A_periph(AT91_PIN_PE4, 0); /* LCDHSYNC */
916 at91_set_A_periph(AT91_PIN_PE5, 0); /* LCDDOTCK */
917 at91_set_A_periph(AT91_PIN_PE6, 0); /* LCDDEN */
918 at91_set_A_periph(AT91_PIN_PE7, 0); /* LCDD0 */
919 at91_set_A_periph(AT91_PIN_PE8, 0); /* LCDD1 */
920 at91_set_A_periph(AT91_PIN_PE9, 0); /* LCDD2 */
921 at91_set_A_periph(AT91_PIN_PE10, 0); /* LCDD3 */
922 at91_set_A_periph(AT91_PIN_PE11, 0); /* LCDD4 */
923 at91_set_A_periph(AT91_PIN_PE12, 0); /* LCDD5 */
924 at91_set_A_periph(AT91_PIN_PE13, 0); /* LCDD6 */
925 at91_set_A_periph(AT91_PIN_PE14, 0); /* LCDD7 */
926 at91_set_A_periph(AT91_PIN_PE15, 0); /* LCDD8 */
927 at91_set_A_periph(AT91_PIN_PE16, 0); /* LCDD9 */
928 at91_set_A_periph(AT91_PIN_PE17, 0); /* LCDD10 */
929 at91_set_A_periph(AT91_PIN_PE18, 0); /* LCDD11 */
930 at91_set_A_periph(AT91_PIN_PE19, 0); /* LCDD12 */
931 at91_set_A_periph(AT91_PIN_PE20, 0); /* LCDD13 */
932 at91_set_A_periph(AT91_PIN_PE21, 0); /* LCDD14 */
933 at91_set_A_periph(AT91_PIN_PE22, 0); /* LCDD15 */
934 at91_set_A_periph(AT91_PIN_PE23, 0); /* LCDD16 */
935 at91_set_A_periph(AT91_PIN_PE24, 0); /* LCDD17 */
936 at91_set_A_periph(AT91_PIN_PE25, 0); /* LCDD18 */
937 at91_set_A_periph(AT91_PIN_PE26, 0); /* LCDD19 */
938 at91_set_A_periph(AT91_PIN_PE27, 0); /* LCDD20 */
939 at91_set_A_periph(AT91_PIN_PE28, 0); /* LCDD21 */
940 at91_set_A_periph(AT91_PIN_PE29, 0); /* LCDD22 */
941 at91_set_A_periph(AT91_PIN_PE30, 0); /* LCDD23 */
944 platform_device_register(&at91_lcdc_device);
947 void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {}
951 /* --------------------------------------------------------------------
952 * Timer/Counter block
953 * -------------------------------------------------------------------- */
955 #ifdef CONFIG_ATMEL_TCLIB
956 static struct resource tcb0_resources[] = {
958 .start = AT91SAM9G45_BASE_TCB0,
959 .end = AT91SAM9G45_BASE_TCB0 + SZ_16K - 1,
960 .flags = IORESOURCE_MEM,
963 .start = AT91SAM9G45_ID_TCB,
964 .end = AT91SAM9G45_ID_TCB,
965 .flags = IORESOURCE_IRQ,
969 static struct platform_device at91sam9g45_tcb0_device = {
972 .resource = tcb0_resources,
973 .num_resources = ARRAY_SIZE(tcb0_resources),
976 /* TCB1 begins with TC3 */
977 static struct resource tcb1_resources[] = {
979 .start = AT91SAM9G45_BASE_TCB1,
980 .end = AT91SAM9G45_BASE_TCB1 + SZ_16K - 1,
981 .flags = IORESOURCE_MEM,
984 .start = AT91SAM9G45_ID_TCB,
985 .end = AT91SAM9G45_ID_TCB,
986 .flags = IORESOURCE_IRQ,
990 static struct platform_device at91sam9g45_tcb1_device = {
993 .resource = tcb1_resources,
994 .num_resources = ARRAY_SIZE(tcb1_resources),
997 static void __init at91_add_device_tc(void)
999 platform_device_register(&at91sam9g45_tcb0_device);
1000 platform_device_register(&at91sam9g45_tcb1_device);
1003 static void __init at91_add_device_tc(void) { }
1007 /* --------------------------------------------------------------------
1009 * -------------------------------------------------------------------- */
1011 #if defined(CONFIG_RTC_DRV_AT91RM9200) || defined(CONFIG_RTC_DRV_AT91RM9200_MODULE)
1012 static struct resource rtc_resources[] = {
1014 .start = AT91SAM9G45_BASE_RTC,
1015 .end = AT91SAM9G45_BASE_RTC + SZ_256 - 1,
1016 .flags = IORESOURCE_MEM,
1019 .start = AT91_ID_SYS,
1021 .flags = IORESOURCE_IRQ,
1025 static struct platform_device at91sam9g45_rtc_device = {
1028 .resource = rtc_resources,
1029 .num_resources = ARRAY_SIZE(rtc_resources),
1032 static void __init at91_add_device_rtc(void)
1034 platform_device_register(&at91sam9g45_rtc_device);
1037 static void __init at91_add_device_rtc(void) {}
1041 /* --------------------------------------------------------------------
1043 * -------------------------------------------------------------------- */
1045 #if defined(CONFIG_TOUCHSCREEN_ATMEL_TSADCC) || defined(CONFIG_TOUCHSCREEN_ATMEL_TSADCC_MODULE)
1046 static u64 tsadcc_dmamask = DMA_BIT_MASK(32);
1047 static struct at91_tsadcc_data tsadcc_data;
1049 static struct resource tsadcc_resources[] = {
1051 .start = AT91SAM9G45_BASE_TSC,
1052 .end = AT91SAM9G45_BASE_TSC + SZ_16K - 1,
1053 .flags = IORESOURCE_MEM,
1056 .start = AT91SAM9G45_ID_TSC,
1057 .end = AT91SAM9G45_ID_TSC,
1058 .flags = IORESOURCE_IRQ,
1062 static struct platform_device at91sam9g45_tsadcc_device = {
1063 .name = "atmel_tsadcc",
1066 .dma_mask = &tsadcc_dmamask,
1067 .coherent_dma_mask = DMA_BIT_MASK(32),
1068 .platform_data = &tsadcc_data,
1070 .resource = tsadcc_resources,
1071 .num_resources = ARRAY_SIZE(tsadcc_resources),
1074 void __init at91_add_device_tsadcc(struct at91_tsadcc_data *data)
1079 at91_set_gpio_input(AT91_PIN_PD20, 0); /* AD0_XR */
1080 at91_set_gpio_input(AT91_PIN_PD21, 0); /* AD1_XL */
1081 at91_set_gpio_input(AT91_PIN_PD22, 0); /* AD2_YT */
1082 at91_set_gpio_input(AT91_PIN_PD23, 0); /* AD3_TB */
1084 tsadcc_data = *data;
1085 platform_device_register(&at91sam9g45_tsadcc_device);
1088 void __init at91_add_device_tsadcc(struct at91_tsadcc_data *data) {}
1092 /* --------------------------------------------------------------------
1094 * -------------------------------------------------------------------- */
1096 static struct resource rtt_resources[] = {
1098 .start = AT91SAM9G45_BASE_RTT,
1099 .end = AT91SAM9G45_BASE_RTT + SZ_16 - 1,
1100 .flags = IORESOURCE_MEM,
1104 static struct platform_device at91sam9g45_rtt_device = {
1107 .resource = rtt_resources,
1108 .num_resources = ARRAY_SIZE(rtt_resources),
1111 static void __init at91_add_device_rtt(void)
1113 platform_device_register(&at91sam9g45_rtt_device);
1117 /* --------------------------------------------------------------------
1119 * -------------------------------------------------------------------- */
1121 #if defined(CONFIG_HW_RANDOM_ATMEL) || defined(CONFIG_HW_RANDOM_ATMEL_MODULE)
1122 static struct resource trng_resources[] = {
1124 .start = AT91SAM9G45_BASE_TRNG,
1125 .end = AT91SAM9G45_BASE_TRNG + SZ_16K - 1,
1126 .flags = IORESOURCE_MEM,
1130 static struct platform_device at91sam9g45_trng_device = {
1131 .name = "atmel-trng",
1133 .resource = trng_resources,
1134 .num_resources = ARRAY_SIZE(trng_resources),
1137 static void __init at91_add_device_trng(void)
1139 platform_device_register(&at91sam9g45_trng_device);
1142 static void __init at91_add_device_trng(void) {}
1145 /* --------------------------------------------------------------------
1147 * -------------------------------------------------------------------- */
1149 #if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
1150 static struct resource wdt_resources[] = {
1152 .start = AT91SAM9G45_BASE_WDT,
1153 .end = AT91SAM9G45_BASE_WDT + SZ_16 - 1,
1154 .flags = IORESOURCE_MEM,
1158 static struct platform_device at91sam9g45_wdt_device = {
1161 .resource = wdt_resources,
1162 .num_resources = ARRAY_SIZE(wdt_resources),
1165 static void __init at91_add_device_watchdog(void)
1167 platform_device_register(&at91sam9g45_wdt_device);
1170 static void __init at91_add_device_watchdog(void) {}
1174 /* --------------------------------------------------------------------
1176 * --------------------------------------------------------------------*/
1178 #if defined(CONFIG_ATMEL_PWM) || defined(CONFIG_ATMEL_PWM_MODULE)
1179 static u32 pwm_mask;
1181 static struct resource pwm_resources[] = {
1183 .start = AT91SAM9G45_BASE_PWMC,
1184 .end = AT91SAM9G45_BASE_PWMC + SZ_16K - 1,
1185 .flags = IORESOURCE_MEM,
1188 .start = AT91SAM9G45_ID_PWMC,
1189 .end = AT91SAM9G45_ID_PWMC,
1190 .flags = IORESOURCE_IRQ,
1194 static struct platform_device at91sam9g45_pwm0_device = {
1195 .name = "atmel_pwm",
1198 .platform_data = &pwm_mask,
1200 .resource = pwm_resources,
1201 .num_resources = ARRAY_SIZE(pwm_resources),
1204 void __init at91_add_device_pwm(u32 mask)
1206 if (mask & (1 << AT91_PWM0))
1207 at91_set_B_periph(AT91_PIN_PD24, 1); /* enable PWM0 */
1209 if (mask & (1 << AT91_PWM1))
1210 at91_set_B_periph(AT91_PIN_PD31, 1); /* enable PWM1 */
1212 if (mask & (1 << AT91_PWM2))
1213 at91_set_B_periph(AT91_PIN_PD26, 1); /* enable PWM2 */
1215 if (mask & (1 << AT91_PWM3))
1216 at91_set_B_periph(AT91_PIN_PD0, 1); /* enable PWM3 */
1220 platform_device_register(&at91sam9g45_pwm0_device);
1223 void __init at91_add_device_pwm(u32 mask) {}
1227 /* --------------------------------------------------------------------
1228 * SSC -- Synchronous Serial Controller
1229 * -------------------------------------------------------------------- */
1231 #if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE)
1232 static u64 ssc0_dmamask = DMA_BIT_MASK(32);
1234 static struct resource ssc0_resources[] = {
1236 .start = AT91SAM9G45_BASE_SSC0,
1237 .end = AT91SAM9G45_BASE_SSC0 + SZ_16K - 1,
1238 .flags = IORESOURCE_MEM,
1241 .start = AT91SAM9G45_ID_SSC0,
1242 .end = AT91SAM9G45_ID_SSC0,
1243 .flags = IORESOURCE_IRQ,
1247 static struct platform_device at91sam9g45_ssc0_device = {
1251 .dma_mask = &ssc0_dmamask,
1252 .coherent_dma_mask = DMA_BIT_MASK(32),
1254 .resource = ssc0_resources,
1255 .num_resources = ARRAY_SIZE(ssc0_resources),
1258 static inline void configure_ssc0_pins(unsigned pins)
1260 if (pins & ATMEL_SSC_TF)
1261 at91_set_A_periph(AT91_PIN_PD1, 1);
1262 if (pins & ATMEL_SSC_TK)
1263 at91_set_A_periph(AT91_PIN_PD0, 1);
1264 if (pins & ATMEL_SSC_TD)
1265 at91_set_A_periph(AT91_PIN_PD2, 1);
1266 if (pins & ATMEL_SSC_RD)
1267 at91_set_A_periph(AT91_PIN_PD3, 1);
1268 if (pins & ATMEL_SSC_RK)
1269 at91_set_A_periph(AT91_PIN_PD4, 1);
1270 if (pins & ATMEL_SSC_RF)
1271 at91_set_A_periph(AT91_PIN_PD5, 1);
1274 static u64 ssc1_dmamask = DMA_BIT_MASK(32);
1276 static struct resource ssc1_resources[] = {
1278 .start = AT91SAM9G45_BASE_SSC1,
1279 .end = AT91SAM9G45_BASE_SSC1 + SZ_16K - 1,
1280 .flags = IORESOURCE_MEM,
1283 .start = AT91SAM9G45_ID_SSC1,
1284 .end = AT91SAM9G45_ID_SSC1,
1285 .flags = IORESOURCE_IRQ,
1289 static struct platform_device at91sam9g45_ssc1_device = {
1293 .dma_mask = &ssc1_dmamask,
1294 .coherent_dma_mask = DMA_BIT_MASK(32),
1296 .resource = ssc1_resources,
1297 .num_resources = ARRAY_SIZE(ssc1_resources),
1300 static inline void configure_ssc1_pins(unsigned pins)
1302 if (pins & ATMEL_SSC_TF)
1303 at91_set_A_periph(AT91_PIN_PD14, 1);
1304 if (pins & ATMEL_SSC_TK)
1305 at91_set_A_periph(AT91_PIN_PD12, 1);
1306 if (pins & ATMEL_SSC_TD)
1307 at91_set_A_periph(AT91_PIN_PD10, 1);
1308 if (pins & ATMEL_SSC_RD)
1309 at91_set_A_periph(AT91_PIN_PD11, 1);
1310 if (pins & ATMEL_SSC_RK)
1311 at91_set_A_periph(AT91_PIN_PD13, 1);
1312 if (pins & ATMEL_SSC_RF)
1313 at91_set_A_periph(AT91_PIN_PD15, 1);
1317 * SSC controllers are accessed through library code, instead of any
1318 * kind of all-singing/all-dancing driver. For example one could be
1319 * used by a particular I2S audio codec's driver, while another one
1320 * on the same system might be used by a custom data capture driver.
1322 void __init at91_add_device_ssc(unsigned id, unsigned pins)
1324 struct platform_device *pdev;
1327 * NOTE: caller is responsible for passing information matching
1328 * "pins" to whatever will be using each particular controller.
1331 case AT91SAM9G45_ID_SSC0:
1332 pdev = &at91sam9g45_ssc0_device;
1333 configure_ssc0_pins(pins);
1335 case AT91SAM9G45_ID_SSC1:
1336 pdev = &at91sam9g45_ssc1_device;
1337 configure_ssc1_pins(pins);
1343 platform_device_register(pdev);
1347 void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
1351 /* --------------------------------------------------------------------
1353 * -------------------------------------------------------------------- */
1355 #if defined(CONFIG_SERIAL_ATMEL)
1356 static struct resource dbgu_resources[] = {
1358 .start = AT91SAM9G45_BASE_DBGU,
1359 .end = AT91SAM9G45_BASE_DBGU + SZ_512 - 1,
1360 .flags = IORESOURCE_MEM,
1363 .start = AT91_ID_SYS,
1365 .flags = IORESOURCE_IRQ,
1369 static struct atmel_uart_data dbgu_data = {
1374 static u64 dbgu_dmamask = DMA_BIT_MASK(32);
1376 static struct platform_device at91sam9g45_dbgu_device = {
1377 .name = "atmel_usart",
1380 .dma_mask = &dbgu_dmamask,
1381 .coherent_dma_mask = DMA_BIT_MASK(32),
1382 .platform_data = &dbgu_data,
1384 .resource = dbgu_resources,
1385 .num_resources = ARRAY_SIZE(dbgu_resources),
1388 static inline void configure_dbgu_pins(void)
1390 at91_set_A_periph(AT91_PIN_PB12, 0); /* DRXD */
1391 at91_set_A_periph(AT91_PIN_PB13, 1); /* DTXD */
1394 static struct resource uart0_resources[] = {
1396 .start = AT91SAM9G45_BASE_US0,
1397 .end = AT91SAM9G45_BASE_US0 + SZ_16K - 1,
1398 .flags = IORESOURCE_MEM,
1401 .start = AT91SAM9G45_ID_US0,
1402 .end = AT91SAM9G45_ID_US0,
1403 .flags = IORESOURCE_IRQ,
1407 static struct atmel_uart_data uart0_data = {
1412 static u64 uart0_dmamask = DMA_BIT_MASK(32);
1414 static struct platform_device at91sam9g45_uart0_device = {
1415 .name = "atmel_usart",
1418 .dma_mask = &uart0_dmamask,
1419 .coherent_dma_mask = DMA_BIT_MASK(32),
1420 .platform_data = &uart0_data,
1422 .resource = uart0_resources,
1423 .num_resources = ARRAY_SIZE(uart0_resources),
1426 static inline void configure_usart0_pins(unsigned pins)
1428 at91_set_A_periph(AT91_PIN_PB19, 1); /* TXD0 */
1429 at91_set_A_periph(AT91_PIN_PB18, 0); /* RXD0 */
1431 if (pins & ATMEL_UART_RTS)
1432 at91_set_B_periph(AT91_PIN_PB17, 0); /* RTS0 */
1433 if (pins & ATMEL_UART_CTS)
1434 at91_set_B_periph(AT91_PIN_PB15, 0); /* CTS0 */
1437 static struct resource uart1_resources[] = {
1439 .start = AT91SAM9G45_BASE_US1,
1440 .end = AT91SAM9G45_BASE_US1 + SZ_16K - 1,
1441 .flags = IORESOURCE_MEM,
1444 .start = AT91SAM9G45_ID_US1,
1445 .end = AT91SAM9G45_ID_US1,
1446 .flags = IORESOURCE_IRQ,
1450 static struct atmel_uart_data uart1_data = {
1455 static u64 uart1_dmamask = DMA_BIT_MASK(32);
1457 static struct platform_device at91sam9g45_uart1_device = {
1458 .name = "atmel_usart",
1461 .dma_mask = &uart1_dmamask,
1462 .coherent_dma_mask = DMA_BIT_MASK(32),
1463 .platform_data = &uart1_data,
1465 .resource = uart1_resources,
1466 .num_resources = ARRAY_SIZE(uart1_resources),
1469 static inline void configure_usart1_pins(unsigned pins)
1471 at91_set_A_periph(AT91_PIN_PB4, 1); /* TXD1 */
1472 at91_set_A_periph(AT91_PIN_PB5, 0); /* RXD1 */
1474 if (pins & ATMEL_UART_RTS)
1475 at91_set_A_periph(AT91_PIN_PD16, 0); /* RTS1 */
1476 if (pins & ATMEL_UART_CTS)
1477 at91_set_A_periph(AT91_PIN_PD17, 0); /* CTS1 */
1480 static struct resource uart2_resources[] = {
1482 .start = AT91SAM9G45_BASE_US2,
1483 .end = AT91SAM9G45_BASE_US2 + SZ_16K - 1,
1484 .flags = IORESOURCE_MEM,
1487 .start = AT91SAM9G45_ID_US2,
1488 .end = AT91SAM9G45_ID_US2,
1489 .flags = IORESOURCE_IRQ,
1493 static struct atmel_uart_data uart2_data = {
1498 static u64 uart2_dmamask = DMA_BIT_MASK(32);
1500 static struct platform_device at91sam9g45_uart2_device = {
1501 .name = "atmel_usart",
1504 .dma_mask = &uart2_dmamask,
1505 .coherent_dma_mask = DMA_BIT_MASK(32),
1506 .platform_data = &uart2_data,
1508 .resource = uart2_resources,
1509 .num_resources = ARRAY_SIZE(uart2_resources),
1512 static inline void configure_usart2_pins(unsigned pins)
1514 at91_set_A_periph(AT91_PIN_PB6, 1); /* TXD2 */
1515 at91_set_A_periph(AT91_PIN_PB7, 0); /* RXD2 */
1517 if (pins & ATMEL_UART_RTS)
1518 at91_set_B_periph(AT91_PIN_PC9, 0); /* RTS2 */
1519 if (pins & ATMEL_UART_CTS)
1520 at91_set_B_periph(AT91_PIN_PC11, 0); /* CTS2 */
1523 static struct resource uart3_resources[] = {
1525 .start = AT91SAM9G45_BASE_US3,
1526 .end = AT91SAM9G45_BASE_US3 + SZ_16K - 1,
1527 .flags = IORESOURCE_MEM,
1530 .start = AT91SAM9G45_ID_US3,
1531 .end = AT91SAM9G45_ID_US3,
1532 .flags = IORESOURCE_IRQ,
1536 static struct atmel_uart_data uart3_data = {
1541 static u64 uart3_dmamask = DMA_BIT_MASK(32);
1543 static struct platform_device at91sam9g45_uart3_device = {
1544 .name = "atmel_usart",
1547 .dma_mask = &uart3_dmamask,
1548 .coherent_dma_mask = DMA_BIT_MASK(32),
1549 .platform_data = &uart3_data,
1551 .resource = uart3_resources,
1552 .num_resources = ARRAY_SIZE(uart3_resources),
1555 static inline void configure_usart3_pins(unsigned pins)
1557 at91_set_A_periph(AT91_PIN_PB8, 1); /* TXD3 */
1558 at91_set_A_periph(AT91_PIN_PB9, 0); /* RXD3 */
1560 if (pins & ATMEL_UART_RTS)
1561 at91_set_B_periph(AT91_PIN_PA23, 0); /* RTS3 */
1562 if (pins & ATMEL_UART_CTS)
1563 at91_set_B_periph(AT91_PIN_PA24, 0); /* CTS3 */
1566 static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
1567 struct platform_device *atmel_default_console_device; /* the serial console device */
1569 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
1571 struct platform_device *pdev;
1572 struct atmel_uart_data *pdata;
1576 pdev = &at91sam9g45_dbgu_device;
1577 configure_dbgu_pins();
1579 case AT91SAM9G45_ID_US0:
1580 pdev = &at91sam9g45_uart0_device;
1581 configure_usart0_pins(pins);
1583 case AT91SAM9G45_ID_US1:
1584 pdev = &at91sam9g45_uart1_device;
1585 configure_usart1_pins(pins);
1587 case AT91SAM9G45_ID_US2:
1588 pdev = &at91sam9g45_uart2_device;
1589 configure_usart2_pins(pins);
1591 case AT91SAM9G45_ID_US3:
1592 pdev = &at91sam9g45_uart3_device;
1593 configure_usart3_pins(pins);
1598 pdata = pdev->dev.platform_data;
1599 pdata->num = portnr; /* update to mapped ID */
1601 if (portnr < ATMEL_MAX_UART)
1602 at91_uarts[portnr] = pdev;
1605 void __init at91_set_serial_console(unsigned portnr)
1607 if (portnr < ATMEL_MAX_UART) {
1608 atmel_default_console_device = at91_uarts[portnr];
1609 at91sam9g45_set_console_clock(at91_uarts[portnr]->id);
1613 void __init at91_add_device_serial(void)
1617 for (i = 0; i < ATMEL_MAX_UART; i++) {
1619 platform_device_register(at91_uarts[i]);
1622 if (!atmel_default_console_device)
1623 printk(KERN_INFO "AT91: No default serial console defined.\n");
1626 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
1627 void __init at91_set_serial_console(unsigned portnr) {}
1628 void __init at91_add_device_serial(void) {}
1632 /* -------------------------------------------------------------------- */
1634 * These devices are always present and don't need any board-specific
1637 static int __init at91_add_standard_devices(void)
1639 at91_add_device_hdmac();
1640 at91_add_device_rtc();
1641 at91_add_device_rtt();
1642 at91_add_device_trng();
1643 at91_add_device_watchdog();
1644 at91_add_device_tc();
1648 arch_initcall(at91_add_standard_devices);