2 * arch/arm/mach-at91/at91sam9rl.c
4 * Copyright (C) 2005 SAN People
5 * Copyright (C) 2007 Atmel Corporation
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file COPYING in the main directory of this archive for
12 #include <linux/module.h>
14 #include <asm/proc-fns.h>
16 #include <asm/mach/arch.h>
17 #include <asm/mach/map.h>
19 #include <mach/at91_dbgu.h>
20 #include <mach/at91sam9rl.h>
21 #include <mach/at91_pmc.h>
22 #include <mach/at91_rstc.h>
29 /* --------------------------------------------------------------------
31 * -------------------------------------------------------------------- */
34 * The peripheral clocks.
36 static struct clk pioA_clk = {
38 .pmc_mask = 1 << AT91SAM9RL_ID_PIOA,
39 .type = CLK_TYPE_PERIPHERAL,
41 static struct clk pioB_clk = {
43 .pmc_mask = 1 << AT91SAM9RL_ID_PIOB,
44 .type = CLK_TYPE_PERIPHERAL,
46 static struct clk pioC_clk = {
48 .pmc_mask = 1 << AT91SAM9RL_ID_PIOC,
49 .type = CLK_TYPE_PERIPHERAL,
51 static struct clk pioD_clk = {
53 .pmc_mask = 1 << AT91SAM9RL_ID_PIOD,
54 .type = CLK_TYPE_PERIPHERAL,
56 static struct clk usart0_clk = {
58 .pmc_mask = 1 << AT91SAM9RL_ID_US0,
59 .type = CLK_TYPE_PERIPHERAL,
61 static struct clk usart1_clk = {
63 .pmc_mask = 1 << AT91SAM9RL_ID_US1,
64 .type = CLK_TYPE_PERIPHERAL,
66 static struct clk usart2_clk = {
68 .pmc_mask = 1 << AT91SAM9RL_ID_US2,
69 .type = CLK_TYPE_PERIPHERAL,
71 static struct clk usart3_clk = {
73 .pmc_mask = 1 << AT91SAM9RL_ID_US3,
74 .type = CLK_TYPE_PERIPHERAL,
76 static struct clk mmc_clk = {
78 .pmc_mask = 1 << AT91SAM9RL_ID_MCI,
79 .type = CLK_TYPE_PERIPHERAL,
81 static struct clk twi0_clk = {
83 .pmc_mask = 1 << AT91SAM9RL_ID_TWI0,
84 .type = CLK_TYPE_PERIPHERAL,
86 static struct clk twi1_clk = {
88 .pmc_mask = 1 << AT91SAM9RL_ID_TWI1,
89 .type = CLK_TYPE_PERIPHERAL,
91 static struct clk spi_clk = {
93 .pmc_mask = 1 << AT91SAM9RL_ID_SPI,
94 .type = CLK_TYPE_PERIPHERAL,
96 static struct clk ssc0_clk = {
98 .pmc_mask = 1 << AT91SAM9RL_ID_SSC0,
99 .type = CLK_TYPE_PERIPHERAL,
101 static struct clk ssc1_clk = {
103 .pmc_mask = 1 << AT91SAM9RL_ID_SSC1,
104 .type = CLK_TYPE_PERIPHERAL,
106 static struct clk tc0_clk = {
108 .pmc_mask = 1 << AT91SAM9RL_ID_TC0,
109 .type = CLK_TYPE_PERIPHERAL,
111 static struct clk tc1_clk = {
113 .pmc_mask = 1 << AT91SAM9RL_ID_TC1,
114 .type = CLK_TYPE_PERIPHERAL,
116 static struct clk tc2_clk = {
118 .pmc_mask = 1 << AT91SAM9RL_ID_TC2,
119 .type = CLK_TYPE_PERIPHERAL,
121 static struct clk pwm_clk = {
123 .pmc_mask = 1 << AT91SAM9RL_ID_PWMC,
124 .type = CLK_TYPE_PERIPHERAL,
126 static struct clk tsc_clk = {
128 .pmc_mask = 1 << AT91SAM9RL_ID_TSC,
129 .type = CLK_TYPE_PERIPHERAL,
131 static struct clk dma_clk = {
133 .pmc_mask = 1 << AT91SAM9RL_ID_DMA,
134 .type = CLK_TYPE_PERIPHERAL,
136 static struct clk udphs_clk = {
138 .pmc_mask = 1 << AT91SAM9RL_ID_UDPHS,
139 .type = CLK_TYPE_PERIPHERAL,
141 static struct clk lcdc_clk = {
143 .pmc_mask = 1 << AT91SAM9RL_ID_LCDC,
144 .type = CLK_TYPE_PERIPHERAL,
146 static struct clk ac97_clk = {
148 .pmc_mask = 1 << AT91SAM9RL_ID_AC97C,
149 .type = CLK_TYPE_PERIPHERAL,
152 static struct clk *periph_clocks[] __initdata = {
179 static struct clk_lookup periph_clocks_lookups[] = {
180 CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
181 CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
182 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
183 CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
184 CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
185 CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
186 CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
187 CLKDEV_CON_ID("pioA", &pioA_clk),
188 CLKDEV_CON_ID("pioB", &pioB_clk),
189 CLKDEV_CON_ID("pioC", &pioC_clk),
190 CLKDEV_CON_ID("pioD", &pioD_clk),
193 static struct clk_lookup usart_clocks_lookups[] = {
194 CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
195 CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
196 CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
197 CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
198 CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
202 * The two programmable clocks.
203 * You must configure pin multiplexing to bring these signals out.
205 static struct clk pck0 = {
207 .pmc_mask = AT91_PMC_PCK0,
208 .type = CLK_TYPE_PROGRAMMABLE,
211 static struct clk pck1 = {
213 .pmc_mask = AT91_PMC_PCK1,
214 .type = CLK_TYPE_PROGRAMMABLE,
218 static void __init at91sam9rl_register_clocks(void)
222 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
223 clk_register(periph_clocks[i]);
225 clkdev_add_table(periph_clocks_lookups,
226 ARRAY_SIZE(periph_clocks_lookups));
227 clkdev_add_table(usart_clocks_lookups,
228 ARRAY_SIZE(usart_clocks_lookups));
234 static struct clk_lookup console_clock_lookup;
236 void __init at91sam9rl_set_console_clock(int id)
238 if (id >= ARRAY_SIZE(usart_clocks_lookups))
241 console_clock_lookup.con_id = "usart";
242 console_clock_lookup.clk = usart_clocks_lookups[id].clk;
243 clkdev_add(&console_clock_lookup);
246 /* --------------------------------------------------------------------
248 * -------------------------------------------------------------------- */
250 static struct at91_gpio_bank at91sam9rl_gpio[] __initdata = {
252 .id = AT91SAM9RL_ID_PIOA,
253 .regbase = AT91SAM9RL_BASE_PIOA,
255 .id = AT91SAM9RL_ID_PIOB,
256 .regbase = AT91SAM9RL_BASE_PIOB,
258 .id = AT91SAM9RL_ID_PIOC,
259 .regbase = AT91SAM9RL_BASE_PIOC,
261 .id = AT91SAM9RL_ID_PIOD,
262 .regbase = AT91SAM9RL_BASE_PIOD,
266 /* --------------------------------------------------------------------
267 * AT91SAM9RL processor initialization
268 * -------------------------------------------------------------------- */
270 static void __init at91sam9rl_map_io(void)
272 unsigned long sram_size;
274 switch (at91_soc_initdata.cidr & AT91_CIDR_SRAMSIZ) {
275 case AT91_CIDR_SRAMSIZ_32K:
276 sram_size = 2 * SZ_16K;
278 case AT91_CIDR_SRAMSIZ_16K:
284 at91_init_sram(0, AT91SAM9RL_SRAM_BASE, sram_size);
287 static void __init at91sam9rl_ioremap_registers(void)
289 at91_ioremap_shdwc(AT91SAM9RL_BASE_SHDWC);
290 at91_ioremap_rstc(AT91SAM9RL_BASE_RSTC);
291 at91_ioremap_ramc(0, AT91SAM9RL_BASE_SDRAMC, 512);
292 at91sam926x_ioremap_pit(AT91SAM9RL_BASE_PIT);
293 at91sam9_ioremap_smc(0, AT91SAM9RL_BASE_SMC);
294 at91_ioremap_matrix(AT91SAM9RL_BASE_MATRIX);
297 static void __init at91sam9rl_initialize(void)
299 arm_pm_idle = at91sam9_idle;
300 arm_pm_restart = at91sam9_alt_restart;
301 at91_extern_irq = (1 << AT91SAM9RL_ID_IRQ0);
303 /* Register GPIO subsystem */
304 at91_gpio_init(at91sam9rl_gpio, 4);
307 /* --------------------------------------------------------------------
308 * Interrupt initialization
309 * -------------------------------------------------------------------- */
312 * The default interrupt priority levels (0 = lowest, 7 = highest).
314 static unsigned int at91sam9rl_default_irq_priority[NR_AIC_IRQS] __initdata = {
315 7, /* Advanced Interrupt Controller */
316 7, /* System Peripherals */
317 1, /* Parallel IO Controller A */
318 1, /* Parallel IO Controller B */
319 1, /* Parallel IO Controller C */
320 1, /* Parallel IO Controller D */
325 0, /* Multimedia Card Interface */
326 6, /* Two-Wire Interface 0 */
327 6, /* Two-Wire Interface 1 */
328 5, /* Serial Peripheral Interface */
329 4, /* Serial Synchronous Controller 0 */
330 4, /* Serial Synchronous Controller 1 */
331 0, /* Timer Counter 0 */
332 0, /* Timer Counter 1 */
333 0, /* Timer Counter 2 */
335 0, /* Touch Screen Controller */
336 0, /* DMA Controller */
337 2, /* USB Device High speed port */
338 2, /* LCD Controller */
339 6, /* AC97 Controller */
346 0, /* Advanced Interrupt Controller */
349 struct at91_init_soc __initdata at91sam9rl_soc = {
350 .map_io = at91sam9rl_map_io,
351 .default_irq_priority = at91sam9rl_default_irq_priority,
352 .ioremap_registers = at91sam9rl_ioremap_registers,
353 .register_clocks = at91sam9rl_register_clocks,
354 .init = at91sam9rl_initialize,