2 * arch/arm/mach-at91/at91sam9rl.c
4 * Copyright (C) 2005 SAN People
5 * Copyright (C) 2007 Atmel Corporation
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file COPYING in the main directory of this archive for
12 #include <linux/module.h>
13 #include <linux/clk/at91_pmc.h>
15 #include <asm/proc-fns.h>
17 #include <asm/mach/arch.h>
18 #include <asm/mach/map.h>
19 #include <asm/system_misc.h>
21 #include <mach/at91_dbgu.h>
22 #include <mach/at91sam9rl.h>
23 #include <mach/hardware.h>
26 #include "at91_rstc.h"
32 /* --------------------------------------------------------------------
34 * -------------------------------------------------------------------- */
35 #if defined(CONFIG_OLD_CLK_AT91)
39 * The peripheral clocks.
41 static struct clk pioA_clk = {
43 .pmc_mask = 1 << AT91SAM9RL_ID_PIOA,
44 .type = CLK_TYPE_PERIPHERAL,
46 static struct clk pioB_clk = {
48 .pmc_mask = 1 << AT91SAM9RL_ID_PIOB,
49 .type = CLK_TYPE_PERIPHERAL,
51 static struct clk pioC_clk = {
53 .pmc_mask = 1 << AT91SAM9RL_ID_PIOC,
54 .type = CLK_TYPE_PERIPHERAL,
56 static struct clk pioD_clk = {
58 .pmc_mask = 1 << AT91SAM9RL_ID_PIOD,
59 .type = CLK_TYPE_PERIPHERAL,
61 static struct clk usart0_clk = {
63 .pmc_mask = 1 << AT91SAM9RL_ID_US0,
64 .type = CLK_TYPE_PERIPHERAL,
66 static struct clk usart1_clk = {
68 .pmc_mask = 1 << AT91SAM9RL_ID_US1,
69 .type = CLK_TYPE_PERIPHERAL,
71 static struct clk usart2_clk = {
73 .pmc_mask = 1 << AT91SAM9RL_ID_US2,
74 .type = CLK_TYPE_PERIPHERAL,
76 static struct clk usart3_clk = {
78 .pmc_mask = 1 << AT91SAM9RL_ID_US3,
79 .type = CLK_TYPE_PERIPHERAL,
81 static struct clk mmc_clk = {
83 .pmc_mask = 1 << AT91SAM9RL_ID_MCI,
84 .type = CLK_TYPE_PERIPHERAL,
86 static struct clk twi0_clk = {
88 .pmc_mask = 1 << AT91SAM9RL_ID_TWI0,
89 .type = CLK_TYPE_PERIPHERAL,
91 static struct clk twi1_clk = {
93 .pmc_mask = 1 << AT91SAM9RL_ID_TWI1,
94 .type = CLK_TYPE_PERIPHERAL,
96 static struct clk spi_clk = {
98 .pmc_mask = 1 << AT91SAM9RL_ID_SPI,
99 .type = CLK_TYPE_PERIPHERAL,
101 static struct clk ssc0_clk = {
103 .pmc_mask = 1 << AT91SAM9RL_ID_SSC0,
104 .type = CLK_TYPE_PERIPHERAL,
106 static struct clk ssc1_clk = {
108 .pmc_mask = 1 << AT91SAM9RL_ID_SSC1,
109 .type = CLK_TYPE_PERIPHERAL,
111 static struct clk tc0_clk = {
113 .pmc_mask = 1 << AT91SAM9RL_ID_TC0,
114 .type = CLK_TYPE_PERIPHERAL,
116 static struct clk tc1_clk = {
118 .pmc_mask = 1 << AT91SAM9RL_ID_TC1,
119 .type = CLK_TYPE_PERIPHERAL,
121 static struct clk tc2_clk = {
123 .pmc_mask = 1 << AT91SAM9RL_ID_TC2,
124 .type = CLK_TYPE_PERIPHERAL,
126 static struct clk pwm_clk = {
128 .pmc_mask = 1 << AT91SAM9RL_ID_PWMC,
129 .type = CLK_TYPE_PERIPHERAL,
131 static struct clk tsc_clk = {
133 .pmc_mask = 1 << AT91SAM9RL_ID_TSC,
134 .type = CLK_TYPE_PERIPHERAL,
136 static struct clk dma_clk = {
138 .pmc_mask = 1 << AT91SAM9RL_ID_DMA,
139 .type = CLK_TYPE_PERIPHERAL,
141 static struct clk udphs_clk = {
143 .pmc_mask = 1 << AT91SAM9RL_ID_UDPHS,
144 .type = CLK_TYPE_PERIPHERAL,
146 static struct clk lcdc_clk = {
148 .pmc_mask = 1 << AT91SAM9RL_ID_LCDC,
149 .type = CLK_TYPE_PERIPHERAL,
151 static struct clk ac97_clk = {
153 .pmc_mask = 1 << AT91SAM9RL_ID_AC97C,
154 .type = CLK_TYPE_PERIPHERAL,
156 static struct clk adc_op_clk = {
157 .name = "adc_op_clk",
158 .type = CLK_TYPE_PERIPHERAL,
162 static struct clk *periph_clocks[] __initdata = {
190 static struct clk_lookup periph_clocks_lookups[] = {
191 CLKDEV_CON_DEV_ID("hclk", "at91sam9rl-lcdfb.0", &lcdc_clk),
192 CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
193 CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
194 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
195 CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
196 CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
197 CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.0", &ssc0_clk),
198 CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.1", &ssc1_clk),
199 CLKDEV_CON_DEV_ID("pclk", "fffc0000.ssc", &ssc0_clk),
200 CLKDEV_CON_DEV_ID("pclk", "fffc4000.ssc", &ssc1_clk),
201 CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g20.0", &twi0_clk),
202 CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g20.1", &twi1_clk),
203 CLKDEV_CON_ID("pioA", &pioA_clk),
204 CLKDEV_CON_ID("pioB", &pioB_clk),
205 CLKDEV_CON_ID("pioC", &pioC_clk),
206 CLKDEV_CON_ID("pioD", &pioD_clk),
207 /* more lookup table for DT entries */
208 CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
209 CLKDEV_CON_DEV_ID("usart", "fffb0000.serial", &usart0_clk),
210 CLKDEV_CON_DEV_ID("usart", "ffffb400.serial", &usart1_clk),
211 CLKDEV_CON_DEV_ID("usart", "ffffb800.serial", &usart2_clk),
212 CLKDEV_CON_DEV_ID("usart", "ffffbc00.serial", &usart3_clk),
213 CLKDEV_CON_DEV_ID("t0_clk", "fffa0000.timer", &tc0_clk),
214 CLKDEV_CON_DEV_ID("t1_clk", "fffa0000.timer", &tc1_clk),
215 CLKDEV_CON_DEV_ID("t2_clk", "fffa0000.timer", &tc2_clk),
216 CLKDEV_CON_DEV_ID("mci_clk", "fffa4000.mmc", &mmc_clk),
217 CLKDEV_CON_DEV_ID(NULL, "fffa8000.i2c", &twi0_clk),
218 CLKDEV_CON_DEV_ID(NULL, "fffac000.i2c", &twi1_clk),
219 CLKDEV_CON_DEV_ID(NULL, "fffc8000.pwm", &pwm_clk),
220 CLKDEV_CON_DEV_ID(NULL, "ffffc800.pwm", &pwm_clk),
221 CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioA_clk),
222 CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioB_clk),
223 CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioC_clk),
224 CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioD_clk),
225 CLKDEV_CON_ID("adc_clk", &tsc_clk),
228 static struct clk_lookup usart_clocks_lookups[] = {
229 CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
230 CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
231 CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
232 CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
233 CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
237 * The two programmable clocks.
238 * You must configure pin multiplexing to bring these signals out.
240 static struct clk pck0 = {
242 .pmc_mask = AT91_PMC_PCK0,
243 .type = CLK_TYPE_PROGRAMMABLE,
246 static struct clk pck1 = {
248 .pmc_mask = AT91_PMC_PCK1,
249 .type = CLK_TYPE_PROGRAMMABLE,
253 static void __init at91sam9rl_register_clocks(void)
257 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
258 clk_register(periph_clocks[i]);
260 clkdev_add_table(periph_clocks_lookups,
261 ARRAY_SIZE(periph_clocks_lookups));
262 clkdev_add_table(usart_clocks_lookups,
263 ARRAY_SIZE(usart_clocks_lookups));
270 /* --------------------------------------------------------------------
272 * -------------------------------------------------------------------- */
274 static struct at91_gpio_bank at91sam9rl_gpio[] __initdata = {
276 .id = AT91SAM9RL_ID_PIOA,
277 .regbase = AT91SAM9RL_BASE_PIOA,
279 .id = AT91SAM9RL_ID_PIOB,
280 .regbase = AT91SAM9RL_BASE_PIOB,
282 .id = AT91SAM9RL_ID_PIOC,
283 .regbase = AT91SAM9RL_BASE_PIOC,
285 .id = AT91SAM9RL_ID_PIOD,
286 .regbase = AT91SAM9RL_BASE_PIOD,
290 /* --------------------------------------------------------------------
291 * AT91SAM9RL processor initialization
292 * -------------------------------------------------------------------- */
294 static void __init at91sam9rl_map_io(void)
296 unsigned long sram_size;
298 switch (at91_soc_initdata.cidr & AT91_CIDR_SRAMSIZ) {
299 case AT91_CIDR_SRAMSIZ_32K:
300 sram_size = 2 * SZ_16K;
302 case AT91_CIDR_SRAMSIZ_16K:
308 at91_init_sram(0, AT91SAM9RL_SRAM_BASE, sram_size);
311 static void __init at91sam9rl_ioremap_registers(void)
313 at91_ioremap_shdwc(AT91SAM9RL_BASE_SHDWC);
314 at91_ioremap_rstc(AT91SAM9RL_BASE_RSTC);
315 at91_ioremap_ramc(0, AT91SAM9RL_BASE_SDRAMC, 512);
316 at91sam926x_ioremap_pit(AT91SAM9RL_BASE_PIT);
317 at91sam9_ioremap_smc(0, AT91SAM9RL_BASE_SMC);
318 at91_ioremap_matrix(AT91SAM9RL_BASE_MATRIX);
319 at91_pm_set_standby(at91sam9_sdram_standby);
322 static void __init at91sam9rl_initialize(void)
324 arm_pm_idle = at91sam9_idle;
325 arm_pm_restart = at91sam9_alt_restart;
327 at91_sysirq_mask_rtc(AT91SAM9RL_BASE_RTC);
328 at91_sysirq_mask_rtt(AT91SAM9RL_BASE_RTT);
330 /* Register GPIO subsystem */
331 at91_gpio_init(at91sam9rl_gpio, 4);
334 /* --------------------------------------------------------------------
335 * Interrupt initialization
336 * -------------------------------------------------------------------- */
339 * The default interrupt priority levels (0 = lowest, 7 = highest).
341 static unsigned int at91sam9rl_default_irq_priority[NR_AIC_IRQS] __initdata = {
342 7, /* Advanced Interrupt Controller */
343 7, /* System Peripherals */
344 1, /* Parallel IO Controller A */
345 1, /* Parallel IO Controller B */
346 1, /* Parallel IO Controller C */
347 1, /* Parallel IO Controller D */
352 0, /* Multimedia Card Interface */
353 6, /* Two-Wire Interface 0 */
354 6, /* Two-Wire Interface 1 */
355 5, /* Serial Peripheral Interface */
356 4, /* Serial Synchronous Controller 0 */
357 4, /* Serial Synchronous Controller 1 */
358 0, /* Timer Counter 0 */
359 0, /* Timer Counter 1 */
360 0, /* Timer Counter 2 */
362 0, /* Touch Screen Controller */
363 0, /* DMA Controller */
364 2, /* USB Device High speed port */
365 2, /* LCD Controller */
366 6, /* AC97 Controller */
373 0, /* Advanced Interrupt Controller */
376 AT91_SOC_START(at91sam9rl)
377 .map_io = at91sam9rl_map_io,
378 .default_irq_priority = at91sam9rl_default_irq_priority,
379 .extern_irq = (1 << AT91SAM9RL_ID_IRQ0),
380 .ioremap_registers = at91sam9rl_ioremap_registers,
381 #if defined(CONFIG_OLD_CLK_AT91)
382 .register_clocks = at91sam9rl_register_clocks,
384 .init = at91sam9rl_initialize,