2 * arch/arm/mach-at91/at91sam9rl.c
4 * Copyright (C) 2005 SAN People
5 * Copyright (C) 2007 Atmel Corporation
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file COPYING in the main directory of this archive for
12 #include <linux/module.h>
14 #include <asm/proc-fns.h>
16 #include <asm/mach/arch.h>
17 #include <asm/mach/map.h>
18 #include <asm/system_misc.h>
20 #include <mach/at91_dbgu.h>
21 #include <mach/at91sam9rl.h>
22 #include <mach/at91_aic.h>
23 #include <mach/at91_pmc.h>
24 #include <mach/at91_rstc.h>
31 /* --------------------------------------------------------------------
33 * -------------------------------------------------------------------- */
36 * The peripheral clocks.
38 static struct clk pioA_clk = {
40 .pmc_mask = 1 << AT91SAM9RL_ID_PIOA,
41 .type = CLK_TYPE_PERIPHERAL,
43 static struct clk pioB_clk = {
45 .pmc_mask = 1 << AT91SAM9RL_ID_PIOB,
46 .type = CLK_TYPE_PERIPHERAL,
48 static struct clk pioC_clk = {
50 .pmc_mask = 1 << AT91SAM9RL_ID_PIOC,
51 .type = CLK_TYPE_PERIPHERAL,
53 static struct clk pioD_clk = {
55 .pmc_mask = 1 << AT91SAM9RL_ID_PIOD,
56 .type = CLK_TYPE_PERIPHERAL,
58 static struct clk usart0_clk = {
60 .pmc_mask = 1 << AT91SAM9RL_ID_US0,
61 .type = CLK_TYPE_PERIPHERAL,
63 static struct clk usart1_clk = {
65 .pmc_mask = 1 << AT91SAM9RL_ID_US1,
66 .type = CLK_TYPE_PERIPHERAL,
68 static struct clk usart2_clk = {
70 .pmc_mask = 1 << AT91SAM9RL_ID_US2,
71 .type = CLK_TYPE_PERIPHERAL,
73 static struct clk usart3_clk = {
75 .pmc_mask = 1 << AT91SAM9RL_ID_US3,
76 .type = CLK_TYPE_PERIPHERAL,
78 static struct clk mmc_clk = {
80 .pmc_mask = 1 << AT91SAM9RL_ID_MCI,
81 .type = CLK_TYPE_PERIPHERAL,
83 static struct clk twi0_clk = {
85 .pmc_mask = 1 << AT91SAM9RL_ID_TWI0,
86 .type = CLK_TYPE_PERIPHERAL,
88 static struct clk twi1_clk = {
90 .pmc_mask = 1 << AT91SAM9RL_ID_TWI1,
91 .type = CLK_TYPE_PERIPHERAL,
93 static struct clk spi_clk = {
95 .pmc_mask = 1 << AT91SAM9RL_ID_SPI,
96 .type = CLK_TYPE_PERIPHERAL,
98 static struct clk ssc0_clk = {
100 .pmc_mask = 1 << AT91SAM9RL_ID_SSC0,
101 .type = CLK_TYPE_PERIPHERAL,
103 static struct clk ssc1_clk = {
105 .pmc_mask = 1 << AT91SAM9RL_ID_SSC1,
106 .type = CLK_TYPE_PERIPHERAL,
108 static struct clk tc0_clk = {
110 .pmc_mask = 1 << AT91SAM9RL_ID_TC0,
111 .type = CLK_TYPE_PERIPHERAL,
113 static struct clk tc1_clk = {
115 .pmc_mask = 1 << AT91SAM9RL_ID_TC1,
116 .type = CLK_TYPE_PERIPHERAL,
118 static struct clk tc2_clk = {
120 .pmc_mask = 1 << AT91SAM9RL_ID_TC2,
121 .type = CLK_TYPE_PERIPHERAL,
123 static struct clk pwm_clk = {
125 .pmc_mask = 1 << AT91SAM9RL_ID_PWMC,
126 .type = CLK_TYPE_PERIPHERAL,
128 static struct clk tsc_clk = {
130 .pmc_mask = 1 << AT91SAM9RL_ID_TSC,
131 .type = CLK_TYPE_PERIPHERAL,
133 static struct clk dma_clk = {
135 .pmc_mask = 1 << AT91SAM9RL_ID_DMA,
136 .type = CLK_TYPE_PERIPHERAL,
138 static struct clk udphs_clk = {
140 .pmc_mask = 1 << AT91SAM9RL_ID_UDPHS,
141 .type = CLK_TYPE_PERIPHERAL,
143 static struct clk lcdc_clk = {
145 .pmc_mask = 1 << AT91SAM9RL_ID_LCDC,
146 .type = CLK_TYPE_PERIPHERAL,
148 static struct clk ac97_clk = {
150 .pmc_mask = 1 << AT91SAM9RL_ID_AC97C,
151 .type = CLK_TYPE_PERIPHERAL,
154 static struct clk *periph_clocks[] __initdata = {
181 static struct clk_lookup periph_clocks_lookups[] = {
182 CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
183 CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
184 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
185 CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
186 CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
187 CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
188 CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
189 CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g20.0", &twi0_clk),
190 CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g20.1", &twi1_clk),
191 CLKDEV_CON_ID("pioA", &pioA_clk),
192 CLKDEV_CON_ID("pioB", &pioB_clk),
193 CLKDEV_CON_ID("pioC", &pioC_clk),
194 CLKDEV_CON_ID("pioD", &pioD_clk),
197 static struct clk_lookup usart_clocks_lookups[] = {
198 CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
199 CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
200 CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
201 CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
202 CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
206 * The two programmable clocks.
207 * You must configure pin multiplexing to bring these signals out.
209 static struct clk pck0 = {
211 .pmc_mask = AT91_PMC_PCK0,
212 .type = CLK_TYPE_PROGRAMMABLE,
215 static struct clk pck1 = {
217 .pmc_mask = AT91_PMC_PCK1,
218 .type = CLK_TYPE_PROGRAMMABLE,
222 static void __init at91sam9rl_register_clocks(void)
226 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
227 clk_register(periph_clocks[i]);
229 clkdev_add_table(periph_clocks_lookups,
230 ARRAY_SIZE(periph_clocks_lookups));
231 clkdev_add_table(usart_clocks_lookups,
232 ARRAY_SIZE(usart_clocks_lookups));
238 /* --------------------------------------------------------------------
240 * -------------------------------------------------------------------- */
242 static struct at91_gpio_bank at91sam9rl_gpio[] __initdata = {
244 .id = AT91SAM9RL_ID_PIOA,
245 .regbase = AT91SAM9RL_BASE_PIOA,
247 .id = AT91SAM9RL_ID_PIOB,
248 .regbase = AT91SAM9RL_BASE_PIOB,
250 .id = AT91SAM9RL_ID_PIOC,
251 .regbase = AT91SAM9RL_BASE_PIOC,
253 .id = AT91SAM9RL_ID_PIOD,
254 .regbase = AT91SAM9RL_BASE_PIOD,
258 /* --------------------------------------------------------------------
259 * AT91SAM9RL processor initialization
260 * -------------------------------------------------------------------- */
262 static void __init at91sam9rl_map_io(void)
264 unsigned long sram_size;
266 switch (at91_soc_initdata.cidr & AT91_CIDR_SRAMSIZ) {
267 case AT91_CIDR_SRAMSIZ_32K:
268 sram_size = 2 * SZ_16K;
270 case AT91_CIDR_SRAMSIZ_16K:
276 at91_init_sram(0, AT91SAM9RL_SRAM_BASE, sram_size);
279 static void __init at91sam9rl_ioremap_registers(void)
281 at91_ioremap_shdwc(AT91SAM9RL_BASE_SHDWC);
282 at91_ioremap_rstc(AT91SAM9RL_BASE_RSTC);
283 at91_ioremap_ramc(0, AT91SAM9RL_BASE_SDRAMC, 512);
284 at91sam926x_ioremap_pit(AT91SAM9RL_BASE_PIT);
285 at91sam9_ioremap_smc(0, AT91SAM9RL_BASE_SMC);
286 at91_ioremap_matrix(AT91SAM9RL_BASE_MATRIX);
289 static void __init at91sam9rl_initialize(void)
291 arm_pm_idle = at91sam9_idle;
292 arm_pm_restart = at91sam9_alt_restart;
293 at91_extern_irq = (1 << AT91SAM9RL_ID_IRQ0);
295 /* Register GPIO subsystem */
296 at91_gpio_init(at91sam9rl_gpio, 4);
299 /* --------------------------------------------------------------------
300 * Interrupt initialization
301 * -------------------------------------------------------------------- */
304 * The default interrupt priority levels (0 = lowest, 7 = highest).
306 static unsigned int at91sam9rl_default_irq_priority[NR_AIC_IRQS] __initdata = {
307 7, /* Advanced Interrupt Controller */
308 7, /* System Peripherals */
309 1, /* Parallel IO Controller A */
310 1, /* Parallel IO Controller B */
311 1, /* Parallel IO Controller C */
312 1, /* Parallel IO Controller D */
317 0, /* Multimedia Card Interface */
318 6, /* Two-Wire Interface 0 */
319 6, /* Two-Wire Interface 1 */
320 5, /* Serial Peripheral Interface */
321 4, /* Serial Synchronous Controller 0 */
322 4, /* Serial Synchronous Controller 1 */
323 0, /* Timer Counter 0 */
324 0, /* Timer Counter 1 */
325 0, /* Timer Counter 2 */
327 0, /* Touch Screen Controller */
328 0, /* DMA Controller */
329 2, /* USB Device High speed port */
330 2, /* LCD Controller */
331 6, /* AC97 Controller */
338 0, /* Advanced Interrupt Controller */
341 AT91_SOC_START(sam9rl)
342 .map_io = at91sam9rl_map_io,
343 .default_irq_priority = at91sam9rl_default_irq_priority,
344 .ioremap_registers = at91sam9rl_ioremap_registers,
345 .register_clocks = at91sam9rl_register_clocks,
346 .init = at91sam9rl_initialize,