2 * arch/arm/mach-at91/at91sam9rl.c
4 * Copyright (C) 2005 SAN People
5 * Copyright (C) 2007 Atmel Corporation
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file COPYING in the main directory of this archive for
12 #include <linux/module.h>
14 #include <asm/proc-fns.h>
16 #include <asm/mach/arch.h>
17 #include <asm/mach/map.h>
18 #include <asm/system_misc.h>
20 #include <mach/at91_dbgu.h>
21 #include <mach/at91sam9rl.h>
22 #include <mach/at91_pmc.h>
23 #include <mach/at91_rstc.h>
30 /* --------------------------------------------------------------------
32 * -------------------------------------------------------------------- */
35 * The peripheral clocks.
37 static struct clk pioA_clk = {
39 .pmc_mask = 1 << AT91SAM9RL_ID_PIOA,
40 .type = CLK_TYPE_PERIPHERAL,
42 static struct clk pioB_clk = {
44 .pmc_mask = 1 << AT91SAM9RL_ID_PIOB,
45 .type = CLK_TYPE_PERIPHERAL,
47 static struct clk pioC_clk = {
49 .pmc_mask = 1 << AT91SAM9RL_ID_PIOC,
50 .type = CLK_TYPE_PERIPHERAL,
52 static struct clk pioD_clk = {
54 .pmc_mask = 1 << AT91SAM9RL_ID_PIOD,
55 .type = CLK_TYPE_PERIPHERAL,
57 static struct clk usart0_clk = {
59 .pmc_mask = 1 << AT91SAM9RL_ID_US0,
60 .type = CLK_TYPE_PERIPHERAL,
62 static struct clk usart1_clk = {
64 .pmc_mask = 1 << AT91SAM9RL_ID_US1,
65 .type = CLK_TYPE_PERIPHERAL,
67 static struct clk usart2_clk = {
69 .pmc_mask = 1 << AT91SAM9RL_ID_US2,
70 .type = CLK_TYPE_PERIPHERAL,
72 static struct clk usart3_clk = {
74 .pmc_mask = 1 << AT91SAM9RL_ID_US3,
75 .type = CLK_TYPE_PERIPHERAL,
77 static struct clk mmc_clk = {
79 .pmc_mask = 1 << AT91SAM9RL_ID_MCI,
80 .type = CLK_TYPE_PERIPHERAL,
82 static struct clk twi0_clk = {
84 .pmc_mask = 1 << AT91SAM9RL_ID_TWI0,
85 .type = CLK_TYPE_PERIPHERAL,
87 static struct clk twi1_clk = {
89 .pmc_mask = 1 << AT91SAM9RL_ID_TWI1,
90 .type = CLK_TYPE_PERIPHERAL,
92 static struct clk spi_clk = {
94 .pmc_mask = 1 << AT91SAM9RL_ID_SPI,
95 .type = CLK_TYPE_PERIPHERAL,
97 static struct clk ssc0_clk = {
99 .pmc_mask = 1 << AT91SAM9RL_ID_SSC0,
100 .type = CLK_TYPE_PERIPHERAL,
102 static struct clk ssc1_clk = {
104 .pmc_mask = 1 << AT91SAM9RL_ID_SSC1,
105 .type = CLK_TYPE_PERIPHERAL,
107 static struct clk tc0_clk = {
109 .pmc_mask = 1 << AT91SAM9RL_ID_TC0,
110 .type = CLK_TYPE_PERIPHERAL,
112 static struct clk tc1_clk = {
114 .pmc_mask = 1 << AT91SAM9RL_ID_TC1,
115 .type = CLK_TYPE_PERIPHERAL,
117 static struct clk tc2_clk = {
119 .pmc_mask = 1 << AT91SAM9RL_ID_TC2,
120 .type = CLK_TYPE_PERIPHERAL,
122 static struct clk pwm_clk = {
124 .pmc_mask = 1 << AT91SAM9RL_ID_PWMC,
125 .type = CLK_TYPE_PERIPHERAL,
127 static struct clk tsc_clk = {
129 .pmc_mask = 1 << AT91SAM9RL_ID_TSC,
130 .type = CLK_TYPE_PERIPHERAL,
132 static struct clk dma_clk = {
134 .pmc_mask = 1 << AT91SAM9RL_ID_DMA,
135 .type = CLK_TYPE_PERIPHERAL,
137 static struct clk udphs_clk = {
139 .pmc_mask = 1 << AT91SAM9RL_ID_UDPHS,
140 .type = CLK_TYPE_PERIPHERAL,
142 static struct clk lcdc_clk = {
144 .pmc_mask = 1 << AT91SAM9RL_ID_LCDC,
145 .type = CLK_TYPE_PERIPHERAL,
147 static struct clk ac97_clk = {
149 .pmc_mask = 1 << AT91SAM9RL_ID_AC97C,
150 .type = CLK_TYPE_PERIPHERAL,
153 static struct clk *periph_clocks[] __initdata = {
180 static struct clk_lookup periph_clocks_lookups[] = {
181 CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
182 CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
183 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
184 CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
185 CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
186 CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
187 CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
188 CLKDEV_CON_ID("pioA", &pioA_clk),
189 CLKDEV_CON_ID("pioB", &pioB_clk),
190 CLKDEV_CON_ID("pioC", &pioC_clk),
191 CLKDEV_CON_ID("pioD", &pioD_clk),
194 static struct clk_lookup usart_clocks_lookups[] = {
195 CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
196 CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
197 CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
198 CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
199 CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
203 * The two programmable clocks.
204 * You must configure pin multiplexing to bring these signals out.
206 static struct clk pck0 = {
208 .pmc_mask = AT91_PMC_PCK0,
209 .type = CLK_TYPE_PROGRAMMABLE,
212 static struct clk pck1 = {
214 .pmc_mask = AT91_PMC_PCK1,
215 .type = CLK_TYPE_PROGRAMMABLE,
219 static void __init at91sam9rl_register_clocks(void)
223 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
224 clk_register(periph_clocks[i]);
226 clkdev_add_table(periph_clocks_lookups,
227 ARRAY_SIZE(periph_clocks_lookups));
228 clkdev_add_table(usart_clocks_lookups,
229 ARRAY_SIZE(usart_clocks_lookups));
235 /* --------------------------------------------------------------------
237 * -------------------------------------------------------------------- */
239 static struct at91_gpio_bank at91sam9rl_gpio[] __initdata = {
241 .id = AT91SAM9RL_ID_PIOA,
242 .regbase = AT91SAM9RL_BASE_PIOA,
244 .id = AT91SAM9RL_ID_PIOB,
245 .regbase = AT91SAM9RL_BASE_PIOB,
247 .id = AT91SAM9RL_ID_PIOC,
248 .regbase = AT91SAM9RL_BASE_PIOC,
250 .id = AT91SAM9RL_ID_PIOD,
251 .regbase = AT91SAM9RL_BASE_PIOD,
255 /* --------------------------------------------------------------------
256 * AT91SAM9RL processor initialization
257 * -------------------------------------------------------------------- */
259 static void __init at91sam9rl_map_io(void)
261 unsigned long sram_size;
263 switch (at91_soc_initdata.cidr & AT91_CIDR_SRAMSIZ) {
264 case AT91_CIDR_SRAMSIZ_32K:
265 sram_size = 2 * SZ_16K;
267 case AT91_CIDR_SRAMSIZ_16K:
273 at91_init_sram(0, AT91SAM9RL_SRAM_BASE, sram_size);
276 static void __init at91sam9rl_ioremap_registers(void)
278 at91_ioremap_shdwc(AT91SAM9RL_BASE_SHDWC);
279 at91_ioremap_rstc(AT91SAM9RL_BASE_RSTC);
280 at91_ioremap_ramc(0, AT91SAM9RL_BASE_SDRAMC, 512);
281 at91sam926x_ioremap_pit(AT91SAM9RL_BASE_PIT);
282 at91sam9_ioremap_smc(0, AT91SAM9RL_BASE_SMC);
283 at91_ioremap_matrix(AT91SAM9RL_BASE_MATRIX);
286 static void __init at91sam9rl_initialize(void)
288 arm_pm_idle = at91sam9_idle;
289 arm_pm_restart = at91sam9_alt_restart;
290 at91_extern_irq = (1 << AT91SAM9RL_ID_IRQ0);
292 /* Register GPIO subsystem */
293 at91_gpio_init(at91sam9rl_gpio, 4);
296 /* --------------------------------------------------------------------
297 * Interrupt initialization
298 * -------------------------------------------------------------------- */
301 * The default interrupt priority levels (0 = lowest, 7 = highest).
303 static unsigned int at91sam9rl_default_irq_priority[NR_AIC_IRQS] __initdata = {
304 7, /* Advanced Interrupt Controller */
305 7, /* System Peripherals */
306 1, /* Parallel IO Controller A */
307 1, /* Parallel IO Controller B */
308 1, /* Parallel IO Controller C */
309 1, /* Parallel IO Controller D */
314 0, /* Multimedia Card Interface */
315 6, /* Two-Wire Interface 0 */
316 6, /* Two-Wire Interface 1 */
317 5, /* Serial Peripheral Interface */
318 4, /* Serial Synchronous Controller 0 */
319 4, /* Serial Synchronous Controller 1 */
320 0, /* Timer Counter 0 */
321 0, /* Timer Counter 1 */
322 0, /* Timer Counter 2 */
324 0, /* Touch Screen Controller */
325 0, /* DMA Controller */
326 2, /* USB Device High speed port */
327 2, /* LCD Controller */
328 6, /* AC97 Controller */
335 0, /* Advanced Interrupt Controller */
338 struct at91_init_soc __initdata at91sam9rl_soc = {
339 .map_io = at91sam9rl_map_io,
340 .default_irq_priority = at91sam9rl_default_irq_priority,
341 .ioremap_registers = at91sam9rl_ioremap_registers,
342 .register_clocks = at91sam9rl_register_clocks,
343 .init = at91sam9rl_initialize,