2 * Copyright (C) 2007 Atmel Corporation
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file COPYING in the main directory of this archive for
9 #include <asm/mach/arch.h>
10 #include <asm/mach/map.h>
12 #include <linux/dma-mapping.h>
13 #include <linux/gpio.h>
14 #include <linux/platform_device.h>
15 #include <linux/i2c-gpio.h>
18 #include <video/atmel_lcdc.h>
20 #include <mach/board.h>
21 #include <mach/at91sam9rl.h>
22 #include <mach/at91sam9rl_matrix.h>
23 #include <mach/at91_matrix.h>
24 #include <mach/at91sam9_smc.h>
25 #include <mach/at_hdmac.h>
30 /* --------------------------------------------------------------------
31 * HDMAC - AHB DMA Controller
32 * -------------------------------------------------------------------- */
34 #if defined(CONFIG_AT_HDMAC) || defined(CONFIG_AT_HDMAC_MODULE)
35 static u64 hdmac_dmamask = DMA_BIT_MASK(32);
37 static struct resource hdmac_resources[] = {
39 .start = AT91SAM9RL_BASE_DMA,
40 .end = AT91SAM9RL_BASE_DMA + SZ_512 - 1,
41 .flags = IORESOURCE_MEM,
44 .start = AT91SAM9RL_ID_DMA,
45 .end = AT91SAM9RL_ID_DMA,
46 .flags = IORESOURCE_IRQ,
50 static struct platform_device at_hdmac_device = {
51 .name = "at91sam9rl_dma",
54 .dma_mask = &hdmac_dmamask,
55 .coherent_dma_mask = DMA_BIT_MASK(32),
57 .resource = hdmac_resources,
58 .num_resources = ARRAY_SIZE(hdmac_resources),
61 void __init at91_add_device_hdmac(void)
63 platform_device_register(&at_hdmac_device);
66 void __init at91_add_device_hdmac(void) {}
69 /* --------------------------------------------------------------------
70 * USB HS Device (Gadget)
71 * -------------------------------------------------------------------- */
73 #if defined(CONFIG_USB_ATMEL_USBA) || defined(CONFIG_USB_ATMEL_USBA_MODULE)
75 static struct resource usba_udc_resources[] = {
77 .start = AT91SAM9RL_UDPHS_FIFO,
78 .end = AT91SAM9RL_UDPHS_FIFO + SZ_512K - 1,
79 .flags = IORESOURCE_MEM,
82 .start = AT91SAM9RL_BASE_UDPHS,
83 .end = AT91SAM9RL_BASE_UDPHS + SZ_1K - 1,
84 .flags = IORESOURCE_MEM,
87 .start = AT91SAM9RL_ID_UDPHS,
88 .end = AT91SAM9RL_ID_UDPHS,
89 .flags = IORESOURCE_IRQ,
93 #define EP(nam, idx, maxpkt, maxbk, dma, isoc) \
97 .fifo_size = maxpkt, \
103 static struct usba_ep_data usba_udc_ep[] __initdata = {
104 EP("ep0", 0, 64, 1, 0, 0),
105 EP("ep1", 1, 1024, 2, 1, 1),
106 EP("ep2", 2, 1024, 2, 1, 1),
107 EP("ep3", 3, 1024, 3, 1, 0),
108 EP("ep4", 4, 1024, 3, 1, 0),
109 EP("ep5", 5, 1024, 3, 1, 1),
110 EP("ep6", 6, 1024, 3, 1, 1),
116 * pdata doesn't have room for any endpoints, so we need to
117 * append room for the ones we need right after it.
120 struct usba_platform_data pdata;
121 struct usba_ep_data ep[7];
124 static struct platform_device at91_usba_udc_device = {
125 .name = "atmel_usba_udc",
128 .platform_data = &usba_udc_data.pdata,
130 .resource = usba_udc_resources,
131 .num_resources = ARRAY_SIZE(usba_udc_resources),
134 void __init at91_add_device_usba(struct usba_platform_data *data)
137 * Invalid pins are 0 on AT91, but the usba driver is shared
138 * with AVR32, which use negative values instead. Once/if
139 * gpio_is_valid() is ported to AT91, revisit this code.
141 usba_udc_data.pdata.vbus_pin = -EINVAL;
142 usba_udc_data.pdata.num_ep = ARRAY_SIZE(usba_udc_ep);
143 memcpy(usba_udc_data.ep, usba_udc_ep, sizeof(usba_udc_ep));
145 if (data && gpio_is_valid(data->vbus_pin)) {
146 at91_set_gpio_input(data->vbus_pin, 0);
147 at91_set_deglitch(data->vbus_pin, 1);
148 usba_udc_data.pdata.vbus_pin = data->vbus_pin;
151 /* Pullup pin is handled internally by USB device peripheral */
153 platform_device_register(&at91_usba_udc_device);
156 void __init at91_add_device_usba(struct usba_platform_data *data) {}
160 /* --------------------------------------------------------------------
162 * -------------------------------------------------------------------- */
164 #if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE)
165 static u64 mmc_dmamask = DMA_BIT_MASK(32);
166 static struct at91_mmc_data mmc_data;
168 static struct resource mmc_resources[] = {
170 .start = AT91SAM9RL_BASE_MCI,
171 .end = AT91SAM9RL_BASE_MCI + SZ_16K - 1,
172 .flags = IORESOURCE_MEM,
175 .start = AT91SAM9RL_ID_MCI,
176 .end = AT91SAM9RL_ID_MCI,
177 .flags = IORESOURCE_IRQ,
181 static struct platform_device at91sam9rl_mmc_device = {
185 .dma_mask = &mmc_dmamask,
186 .coherent_dma_mask = DMA_BIT_MASK(32),
187 .platform_data = &mmc_data,
189 .resource = mmc_resources,
190 .num_resources = ARRAY_SIZE(mmc_resources),
193 void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
199 if (gpio_is_valid(data->det_pin)) {
200 at91_set_gpio_input(data->det_pin, 1);
201 at91_set_deglitch(data->det_pin, 1);
203 if (gpio_is_valid(data->wp_pin))
204 at91_set_gpio_input(data->wp_pin, 1);
205 if (gpio_is_valid(data->vcc_pin))
206 at91_set_gpio_output(data->vcc_pin, 0);
209 at91_set_A_periph(AT91_PIN_PA2, 0);
212 at91_set_A_periph(AT91_PIN_PA1, 1);
214 /* DAT0, maybe DAT1..DAT3 */
215 at91_set_A_periph(AT91_PIN_PA0, 1);
217 at91_set_A_periph(AT91_PIN_PA3, 1);
218 at91_set_A_periph(AT91_PIN_PA4, 1);
219 at91_set_A_periph(AT91_PIN_PA5, 1);
223 platform_device_register(&at91sam9rl_mmc_device);
226 void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {}
230 /* --------------------------------------------------------------------
232 * -------------------------------------------------------------------- */
234 #if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE)
235 static struct atmel_nand_data nand_data;
237 #define NAND_BASE AT91_CHIPSELECT_3
239 static struct resource nand_resources[] = {
242 .end = NAND_BASE + SZ_256M - 1,
243 .flags = IORESOURCE_MEM,
246 .start = AT91SAM9RL_BASE_ECC,
247 .end = AT91SAM9RL_BASE_ECC + SZ_512 - 1,
248 .flags = IORESOURCE_MEM,
252 static struct platform_device atmel_nand_device = {
253 .name = "atmel_nand",
256 .platform_data = &nand_data,
258 .resource = nand_resources,
259 .num_resources = ARRAY_SIZE(nand_resources),
262 void __init at91_add_device_nand(struct atmel_nand_data *data)
269 csa = at91_matrix_read(AT91_MATRIX_EBICSA);
270 at91_matrix_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
273 if (gpio_is_valid(data->enable_pin))
274 at91_set_gpio_output(data->enable_pin, 1);
277 if (gpio_is_valid(data->rdy_pin))
278 at91_set_gpio_input(data->rdy_pin, 1);
280 /* card detect pin */
281 if (gpio_is_valid(data->det_pin))
282 at91_set_gpio_input(data->det_pin, 1);
284 at91_set_A_periph(AT91_PIN_PB4, 0); /* NANDOE */
285 at91_set_A_periph(AT91_PIN_PB5, 0); /* NANDWE */
288 platform_device_register(&atmel_nand_device);
292 void __init at91_add_device_nand(struct atmel_nand_data *data) {}
296 /* --------------------------------------------------------------------
298 * -------------------------------------------------------------------- */
301 * Prefer the GPIO code since the TWI controller isn't robust
302 * (gets overruns and underruns under load) and can only issue
303 * repeated STARTs in one scenario (the driver doesn't yet handle them).
305 #if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
307 static struct i2c_gpio_platform_data pdata = {
308 .sda_pin = AT91_PIN_PA23,
309 .sda_is_open_drain = 1,
310 .scl_pin = AT91_PIN_PA24,
311 .scl_is_open_drain = 1,
312 .udelay = 2, /* ~100 kHz */
315 static struct platform_device at91sam9rl_twi_device = {
318 .dev.platform_data = &pdata,
321 void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
323 at91_set_GPIO_periph(AT91_PIN_PA23, 1); /* TWD (SDA) */
324 at91_set_multi_drive(AT91_PIN_PA23, 1);
326 at91_set_GPIO_periph(AT91_PIN_PA24, 1); /* TWCK (SCL) */
327 at91_set_multi_drive(AT91_PIN_PA24, 1);
329 i2c_register_board_info(0, devices, nr_devices);
330 platform_device_register(&at91sam9rl_twi_device);
333 #elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
335 static struct resource twi_resources[] = {
337 .start = AT91SAM9RL_BASE_TWI0,
338 .end = AT91SAM9RL_BASE_TWI0 + SZ_16K - 1,
339 .flags = IORESOURCE_MEM,
342 .start = AT91SAM9RL_ID_TWI0,
343 .end = AT91SAM9RL_ID_TWI0,
344 .flags = IORESOURCE_IRQ,
348 static struct platform_device at91sam9rl_twi_device = {
351 .resource = twi_resources,
352 .num_resources = ARRAY_SIZE(twi_resources),
355 void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
357 /* pins used for TWI interface */
358 at91_set_A_periph(AT91_PIN_PA23, 0); /* TWD */
359 at91_set_multi_drive(AT91_PIN_PA23, 1);
361 at91_set_A_periph(AT91_PIN_PA24, 0); /* TWCK */
362 at91_set_multi_drive(AT91_PIN_PA24, 1);
364 i2c_register_board_info(0, devices, nr_devices);
365 platform_device_register(&at91sam9rl_twi_device);
368 void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) {}
372 /* --------------------------------------------------------------------
374 * -------------------------------------------------------------------- */
376 #if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
377 static u64 spi_dmamask = DMA_BIT_MASK(32);
379 static struct resource spi_resources[] = {
381 .start = AT91SAM9RL_BASE_SPI,
382 .end = AT91SAM9RL_BASE_SPI + SZ_16K - 1,
383 .flags = IORESOURCE_MEM,
386 .start = AT91SAM9RL_ID_SPI,
387 .end = AT91SAM9RL_ID_SPI,
388 .flags = IORESOURCE_IRQ,
392 static struct platform_device at91sam9rl_spi_device = {
396 .dma_mask = &spi_dmamask,
397 .coherent_dma_mask = DMA_BIT_MASK(32),
399 .resource = spi_resources,
400 .num_resources = ARRAY_SIZE(spi_resources),
403 static const unsigned spi_standard_cs[4] = { AT91_PIN_PA28, AT91_PIN_PB7, AT91_PIN_PD8, AT91_PIN_PD9 };
406 void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
409 unsigned long cs_pin;
411 at91_set_A_periph(AT91_PIN_PA25, 0); /* MISO */
412 at91_set_A_periph(AT91_PIN_PA26, 0); /* MOSI */
413 at91_set_A_periph(AT91_PIN_PA27, 0); /* SPCK */
415 /* Enable SPI chip-selects */
416 for (i = 0; i < nr_devices; i++) {
417 if (devices[i].controller_data)
418 cs_pin = (unsigned long) devices[i].controller_data;
420 cs_pin = spi_standard_cs[devices[i].chip_select];
422 if (!gpio_is_valid(cs_pin))
425 /* enable chip-select pin */
426 at91_set_gpio_output(cs_pin, 1);
428 /* pass chip-select pin to driver */
429 devices[i].controller_data = (void *) cs_pin;
432 spi_register_board_info(devices, nr_devices);
433 platform_device_register(&at91sam9rl_spi_device);
436 void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
440 /* --------------------------------------------------------------------
442 * -------------------------------------------------------------------- */
444 #if defined(CONFIG_SND_ATMEL_AC97C) || defined(CONFIG_SND_ATMEL_AC97C_MODULE)
445 static u64 ac97_dmamask = DMA_BIT_MASK(32);
446 static struct ac97c_platform_data ac97_data;
448 static struct resource ac97_resources[] = {
450 .start = AT91SAM9RL_BASE_AC97C,
451 .end = AT91SAM9RL_BASE_AC97C + SZ_16K - 1,
452 .flags = IORESOURCE_MEM,
455 .start = AT91SAM9RL_ID_AC97C,
456 .end = AT91SAM9RL_ID_AC97C,
457 .flags = IORESOURCE_IRQ,
461 static struct platform_device at91sam9rl_ac97_device = {
462 .name = "atmel_ac97c",
465 .dma_mask = &ac97_dmamask,
466 .coherent_dma_mask = DMA_BIT_MASK(32),
467 .platform_data = &ac97_data,
469 .resource = ac97_resources,
470 .num_resources = ARRAY_SIZE(ac97_resources),
473 void __init at91_add_device_ac97(struct ac97c_platform_data *data)
478 at91_set_A_periph(AT91_PIN_PD1, 0); /* AC97FS */
479 at91_set_A_periph(AT91_PIN_PD2, 0); /* AC97CK */
480 at91_set_A_periph(AT91_PIN_PD3, 0); /* AC97TX */
481 at91_set_A_periph(AT91_PIN_PD4, 0); /* AC97RX */
484 if (gpio_is_valid(data->reset_pin))
485 at91_set_gpio_output(data->reset_pin, 0);
488 platform_device_register(&at91sam9rl_ac97_device);
491 void __init at91_add_device_ac97(struct ac97c_platform_data *data) {}
495 /* --------------------------------------------------------------------
497 * -------------------------------------------------------------------- */
499 #if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
500 static u64 lcdc_dmamask = DMA_BIT_MASK(32);
501 static struct atmel_lcdfb_info lcdc_data;
503 static struct resource lcdc_resources[] = {
505 .start = AT91SAM9RL_LCDC_BASE,
506 .end = AT91SAM9RL_LCDC_BASE + SZ_4K - 1,
507 .flags = IORESOURCE_MEM,
510 .start = AT91SAM9RL_ID_LCDC,
511 .end = AT91SAM9RL_ID_LCDC,
512 .flags = IORESOURCE_IRQ,
516 static struct platform_device at91_lcdc_device = {
517 .name = "atmel_lcdfb",
520 .dma_mask = &lcdc_dmamask,
521 .coherent_dma_mask = DMA_BIT_MASK(32),
522 .platform_data = &lcdc_data,
524 .resource = lcdc_resources,
525 .num_resources = ARRAY_SIZE(lcdc_resources),
528 void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
534 at91_set_B_periph(AT91_PIN_PC1, 0); /* LCDPWR */
535 at91_set_A_periph(AT91_PIN_PC5, 0); /* LCDHSYNC */
536 at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDDOTCK */
537 at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDDEN */
538 at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDCC */
539 at91_set_B_periph(AT91_PIN_PC9, 0); /* LCDD3 */
540 at91_set_B_periph(AT91_PIN_PC10, 0); /* LCDD4 */
541 at91_set_B_periph(AT91_PIN_PC11, 0); /* LCDD5 */
542 at91_set_B_periph(AT91_PIN_PC12, 0); /* LCDD6 */
543 at91_set_B_periph(AT91_PIN_PC13, 0); /* LCDD7 */
544 at91_set_B_periph(AT91_PIN_PC15, 0); /* LCDD11 */
545 at91_set_B_periph(AT91_PIN_PC16, 0); /* LCDD12 */
546 at91_set_B_periph(AT91_PIN_PC17, 0); /* LCDD13 */
547 at91_set_B_periph(AT91_PIN_PC18, 0); /* LCDD14 */
548 at91_set_B_periph(AT91_PIN_PC19, 0); /* LCDD15 */
549 at91_set_B_periph(AT91_PIN_PC20, 0); /* LCDD18 */
550 at91_set_B_periph(AT91_PIN_PC21, 0); /* LCDD19 */
551 at91_set_B_periph(AT91_PIN_PC22, 0); /* LCDD20 */
552 at91_set_B_periph(AT91_PIN_PC23, 0); /* LCDD21 */
553 at91_set_B_periph(AT91_PIN_PC24, 0); /* LCDD22 */
554 at91_set_B_periph(AT91_PIN_PC25, 0); /* LCDD23 */
557 platform_device_register(&at91_lcdc_device);
560 void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {}
564 /* --------------------------------------------------------------------
565 * Timer/Counter block
566 * -------------------------------------------------------------------- */
568 #ifdef CONFIG_ATMEL_TCLIB
570 static struct resource tcb_resources[] = {
572 .start = AT91SAM9RL_BASE_TCB0,
573 .end = AT91SAM9RL_BASE_TCB0 + SZ_16K - 1,
574 .flags = IORESOURCE_MEM,
577 .start = AT91SAM9RL_ID_TC0,
578 .end = AT91SAM9RL_ID_TC0,
579 .flags = IORESOURCE_IRQ,
582 .start = AT91SAM9RL_ID_TC1,
583 .end = AT91SAM9RL_ID_TC1,
584 .flags = IORESOURCE_IRQ,
587 .start = AT91SAM9RL_ID_TC2,
588 .end = AT91SAM9RL_ID_TC2,
589 .flags = IORESOURCE_IRQ,
593 static struct platform_device at91sam9rl_tcb_device = {
596 .resource = tcb_resources,
597 .num_resources = ARRAY_SIZE(tcb_resources),
600 static void __init at91_add_device_tc(void)
602 platform_device_register(&at91sam9rl_tcb_device);
605 static void __init at91_add_device_tc(void) { }
609 /* --------------------------------------------------------------------
611 * -------------------------------------------------------------------- */
613 #if defined(CONFIG_TOUCHSCREEN_ATMEL_TSADCC) || defined(CONFIG_TOUCHSCREEN_ATMEL_TSADCC_MODULE)
614 static u64 tsadcc_dmamask = DMA_BIT_MASK(32);
615 static struct at91_tsadcc_data tsadcc_data;
617 static struct resource tsadcc_resources[] = {
619 .start = AT91SAM9RL_BASE_TSC,
620 .end = AT91SAM9RL_BASE_TSC + SZ_16K - 1,
621 .flags = IORESOURCE_MEM,
624 .start = AT91SAM9RL_ID_TSC,
625 .end = AT91SAM9RL_ID_TSC,
626 .flags = IORESOURCE_IRQ,
630 static struct platform_device at91sam9rl_tsadcc_device = {
631 .name = "atmel_tsadcc",
634 .dma_mask = &tsadcc_dmamask,
635 .coherent_dma_mask = DMA_BIT_MASK(32),
636 .platform_data = &tsadcc_data,
638 .resource = tsadcc_resources,
639 .num_resources = ARRAY_SIZE(tsadcc_resources),
642 void __init at91_add_device_tsadcc(struct at91_tsadcc_data *data)
647 at91_set_A_periph(AT91_PIN_PA17, 0); /* AD0_XR */
648 at91_set_A_periph(AT91_PIN_PA18, 0); /* AD1_XL */
649 at91_set_A_periph(AT91_PIN_PA19, 0); /* AD2_YT */
650 at91_set_A_periph(AT91_PIN_PA20, 0); /* AD3_TB */
653 platform_device_register(&at91sam9rl_tsadcc_device);
656 void __init at91_add_device_tsadcc(struct at91_tsadcc_data *data) {}
660 /* --------------------------------------------------------------------
662 * -------------------------------------------------------------------- */
664 #if defined(CONFIG_RTC_DRV_AT91RM9200) || defined(CONFIG_RTC_DRV_AT91RM9200_MODULE)
665 static struct platform_device at91sam9rl_rtc_device = {
671 static void __init at91_add_device_rtc(void)
673 platform_device_register(&at91sam9rl_rtc_device);
676 static void __init at91_add_device_rtc(void) {}
680 /* --------------------------------------------------------------------
682 * -------------------------------------------------------------------- */
684 static struct resource rtt_resources[] = {
686 .start = AT91SAM9RL_BASE_RTT,
687 .end = AT91SAM9RL_BASE_RTT + SZ_16 - 1,
688 .flags = IORESOURCE_MEM,
690 .flags = IORESOURCE_MEM,
694 static struct platform_device at91sam9rl_rtt_device = {
697 .resource = rtt_resources,
700 #if IS_ENABLED(CONFIG_RTC_DRV_AT91SAM9)
701 static void __init at91_add_device_rtt_rtc(void)
703 at91sam9rl_rtt_device.name = "rtc-at91sam9";
705 * The second resource is needed:
706 * GPBR will serve as the storage for RTC time offset
708 at91sam9rl_rtt_device.num_resources = 2;
709 rtt_resources[1].start = AT91SAM9RL_BASE_GPBR +
710 4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
711 rtt_resources[1].end = rtt_resources[1].start + 3;
714 static void __init at91_add_device_rtt_rtc(void)
716 /* Only one resource is needed: RTT not used as RTC */
717 at91sam9rl_rtt_device.num_resources = 1;
721 static void __init at91_add_device_rtt(void)
723 at91_add_device_rtt_rtc();
724 platform_device_register(&at91sam9rl_rtt_device);
728 /* --------------------------------------------------------------------
730 * -------------------------------------------------------------------- */
732 #if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
733 static struct resource wdt_resources[] = {
735 .start = AT91SAM9RL_BASE_WDT,
736 .end = AT91SAM9RL_BASE_WDT + SZ_16 - 1,
737 .flags = IORESOURCE_MEM,
741 static struct platform_device at91sam9rl_wdt_device = {
744 .resource = wdt_resources,
745 .num_resources = ARRAY_SIZE(wdt_resources),
748 static void __init at91_add_device_watchdog(void)
750 platform_device_register(&at91sam9rl_wdt_device);
753 static void __init at91_add_device_watchdog(void) {}
757 /* --------------------------------------------------------------------
759 * --------------------------------------------------------------------*/
761 #if defined(CONFIG_ATMEL_PWM)
764 static struct resource pwm_resources[] = {
766 .start = AT91SAM9RL_BASE_PWMC,
767 .end = AT91SAM9RL_BASE_PWMC + SZ_16K - 1,
768 .flags = IORESOURCE_MEM,
771 .start = AT91SAM9RL_ID_PWMC,
772 .end = AT91SAM9RL_ID_PWMC,
773 .flags = IORESOURCE_IRQ,
777 static struct platform_device at91sam9rl_pwm0_device = {
781 .platform_data = &pwm_mask,
783 .resource = pwm_resources,
784 .num_resources = ARRAY_SIZE(pwm_resources),
787 void __init at91_add_device_pwm(u32 mask)
789 if (mask & (1 << AT91_PWM0))
790 at91_set_B_periph(AT91_PIN_PB8, 1); /* enable PWM0 */
792 if (mask & (1 << AT91_PWM1))
793 at91_set_B_periph(AT91_PIN_PB9, 1); /* enable PWM1 */
795 if (mask & (1 << AT91_PWM2))
796 at91_set_B_periph(AT91_PIN_PD5, 1); /* enable PWM2 */
798 if (mask & (1 << AT91_PWM3))
799 at91_set_B_periph(AT91_PIN_PD8, 1); /* enable PWM3 */
803 platform_device_register(&at91sam9rl_pwm0_device);
806 void __init at91_add_device_pwm(u32 mask) {}
810 /* --------------------------------------------------------------------
811 * SSC -- Synchronous Serial Controller
812 * -------------------------------------------------------------------- */
814 #if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE)
815 static u64 ssc0_dmamask = DMA_BIT_MASK(32);
817 static struct resource ssc0_resources[] = {
819 .start = AT91SAM9RL_BASE_SSC0,
820 .end = AT91SAM9RL_BASE_SSC0 + SZ_16K - 1,
821 .flags = IORESOURCE_MEM,
824 .start = AT91SAM9RL_ID_SSC0,
825 .end = AT91SAM9RL_ID_SSC0,
826 .flags = IORESOURCE_IRQ,
830 static struct platform_device at91sam9rl_ssc0_device = {
834 .dma_mask = &ssc0_dmamask,
835 .coherent_dma_mask = DMA_BIT_MASK(32),
837 .resource = ssc0_resources,
838 .num_resources = ARRAY_SIZE(ssc0_resources),
841 static inline void configure_ssc0_pins(unsigned pins)
843 if (pins & ATMEL_SSC_TF)
844 at91_set_A_periph(AT91_PIN_PC0, 1);
845 if (pins & ATMEL_SSC_TK)
846 at91_set_A_periph(AT91_PIN_PC1, 1);
847 if (pins & ATMEL_SSC_TD)
848 at91_set_A_periph(AT91_PIN_PA15, 1);
849 if (pins & ATMEL_SSC_RD)
850 at91_set_A_periph(AT91_PIN_PA16, 1);
851 if (pins & ATMEL_SSC_RK)
852 at91_set_B_periph(AT91_PIN_PA10, 1);
853 if (pins & ATMEL_SSC_RF)
854 at91_set_B_periph(AT91_PIN_PA22, 1);
857 static u64 ssc1_dmamask = DMA_BIT_MASK(32);
859 static struct resource ssc1_resources[] = {
861 .start = AT91SAM9RL_BASE_SSC1,
862 .end = AT91SAM9RL_BASE_SSC1 + SZ_16K - 1,
863 .flags = IORESOURCE_MEM,
866 .start = AT91SAM9RL_ID_SSC1,
867 .end = AT91SAM9RL_ID_SSC1,
868 .flags = IORESOURCE_IRQ,
872 static struct platform_device at91sam9rl_ssc1_device = {
876 .dma_mask = &ssc1_dmamask,
877 .coherent_dma_mask = DMA_BIT_MASK(32),
879 .resource = ssc1_resources,
880 .num_resources = ARRAY_SIZE(ssc1_resources),
883 static inline void configure_ssc1_pins(unsigned pins)
885 if (pins & ATMEL_SSC_TF)
886 at91_set_B_periph(AT91_PIN_PA29, 1);
887 if (pins & ATMEL_SSC_TK)
888 at91_set_B_periph(AT91_PIN_PA30, 1);
889 if (pins & ATMEL_SSC_TD)
890 at91_set_B_periph(AT91_PIN_PA13, 1);
891 if (pins & ATMEL_SSC_RD)
892 at91_set_B_periph(AT91_PIN_PA14, 1);
893 if (pins & ATMEL_SSC_RK)
894 at91_set_B_periph(AT91_PIN_PA9, 1);
895 if (pins & ATMEL_SSC_RF)
896 at91_set_B_periph(AT91_PIN_PA8, 1);
900 * SSC controllers are accessed through library code, instead of any
901 * kind of all-singing/all-dancing driver. For example one could be
902 * used by a particular I2S audio codec's driver, while another one
903 * on the same system might be used by a custom data capture driver.
905 void __init at91_add_device_ssc(unsigned id, unsigned pins)
907 struct platform_device *pdev;
910 * NOTE: caller is responsible for passing information matching
911 * "pins" to whatever will be using each particular controller.
914 case AT91SAM9RL_ID_SSC0:
915 pdev = &at91sam9rl_ssc0_device;
916 configure_ssc0_pins(pins);
918 case AT91SAM9RL_ID_SSC1:
919 pdev = &at91sam9rl_ssc1_device;
920 configure_ssc1_pins(pins);
926 platform_device_register(pdev);
930 void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
934 /* --------------------------------------------------------------------
936 * -------------------------------------------------------------------- */
938 #if defined(CONFIG_SERIAL_ATMEL)
939 static struct resource dbgu_resources[] = {
941 .start = AT91SAM9RL_BASE_DBGU,
942 .end = AT91SAM9RL_BASE_DBGU + SZ_512 - 1,
943 .flags = IORESOURCE_MEM,
946 .start = AT91_ID_SYS,
948 .flags = IORESOURCE_IRQ,
952 static struct atmel_uart_data dbgu_data = {
954 .use_dma_rx = 0, /* DBGU not capable of receive DMA */
957 static u64 dbgu_dmamask = DMA_BIT_MASK(32);
959 static struct platform_device at91sam9rl_dbgu_device = {
960 .name = "atmel_usart",
963 .dma_mask = &dbgu_dmamask,
964 .coherent_dma_mask = DMA_BIT_MASK(32),
965 .platform_data = &dbgu_data,
967 .resource = dbgu_resources,
968 .num_resources = ARRAY_SIZE(dbgu_resources),
971 static inline void configure_dbgu_pins(void)
973 at91_set_A_periph(AT91_PIN_PA21, 0); /* DRXD */
974 at91_set_A_periph(AT91_PIN_PA22, 1); /* DTXD */
977 static struct resource uart0_resources[] = {
979 .start = AT91SAM9RL_BASE_US0,
980 .end = AT91SAM9RL_BASE_US0 + SZ_16K - 1,
981 .flags = IORESOURCE_MEM,
984 .start = AT91SAM9RL_ID_US0,
985 .end = AT91SAM9RL_ID_US0,
986 .flags = IORESOURCE_IRQ,
990 static struct atmel_uart_data uart0_data = {
995 static u64 uart0_dmamask = DMA_BIT_MASK(32);
997 static struct platform_device at91sam9rl_uart0_device = {
998 .name = "atmel_usart",
1001 .dma_mask = &uart0_dmamask,
1002 .coherent_dma_mask = DMA_BIT_MASK(32),
1003 .platform_data = &uart0_data,
1005 .resource = uart0_resources,
1006 .num_resources = ARRAY_SIZE(uart0_resources),
1009 static inline void configure_usart0_pins(unsigned pins)
1011 at91_set_A_periph(AT91_PIN_PA6, 1); /* TXD0 */
1012 at91_set_A_periph(AT91_PIN_PA7, 0); /* RXD0 */
1014 if (pins & ATMEL_UART_RTS)
1015 at91_set_A_periph(AT91_PIN_PA9, 0); /* RTS0 */
1016 if (pins & ATMEL_UART_CTS)
1017 at91_set_A_periph(AT91_PIN_PA10, 0); /* CTS0 */
1018 if (pins & ATMEL_UART_DSR)
1019 at91_set_A_periph(AT91_PIN_PD14, 0); /* DSR0 */
1020 if (pins & ATMEL_UART_DTR)
1021 at91_set_A_periph(AT91_PIN_PD15, 0); /* DTR0 */
1022 if (pins & ATMEL_UART_DCD)
1023 at91_set_A_periph(AT91_PIN_PD16, 0); /* DCD0 */
1024 if (pins & ATMEL_UART_RI)
1025 at91_set_A_periph(AT91_PIN_PD17, 0); /* RI0 */
1028 static struct resource uart1_resources[] = {
1030 .start = AT91SAM9RL_BASE_US1,
1031 .end = AT91SAM9RL_BASE_US1 + SZ_16K - 1,
1032 .flags = IORESOURCE_MEM,
1035 .start = AT91SAM9RL_ID_US1,
1036 .end = AT91SAM9RL_ID_US1,
1037 .flags = IORESOURCE_IRQ,
1041 static struct atmel_uart_data uart1_data = {
1046 static u64 uart1_dmamask = DMA_BIT_MASK(32);
1048 static struct platform_device at91sam9rl_uart1_device = {
1049 .name = "atmel_usart",
1052 .dma_mask = &uart1_dmamask,
1053 .coherent_dma_mask = DMA_BIT_MASK(32),
1054 .platform_data = &uart1_data,
1056 .resource = uart1_resources,
1057 .num_resources = ARRAY_SIZE(uart1_resources),
1060 static inline void configure_usart1_pins(unsigned pins)
1062 at91_set_A_periph(AT91_PIN_PA11, 1); /* TXD1 */
1063 at91_set_A_periph(AT91_PIN_PA12, 0); /* RXD1 */
1065 if (pins & ATMEL_UART_RTS)
1066 at91_set_B_periph(AT91_PIN_PA18, 0); /* RTS1 */
1067 if (pins & ATMEL_UART_CTS)
1068 at91_set_B_periph(AT91_PIN_PA19, 0); /* CTS1 */
1071 static struct resource uart2_resources[] = {
1073 .start = AT91SAM9RL_BASE_US2,
1074 .end = AT91SAM9RL_BASE_US2 + SZ_16K - 1,
1075 .flags = IORESOURCE_MEM,
1078 .start = AT91SAM9RL_ID_US2,
1079 .end = AT91SAM9RL_ID_US2,
1080 .flags = IORESOURCE_IRQ,
1084 static struct atmel_uart_data uart2_data = {
1089 static u64 uart2_dmamask = DMA_BIT_MASK(32);
1091 static struct platform_device at91sam9rl_uart2_device = {
1092 .name = "atmel_usart",
1095 .dma_mask = &uart2_dmamask,
1096 .coherent_dma_mask = DMA_BIT_MASK(32),
1097 .platform_data = &uart2_data,
1099 .resource = uart2_resources,
1100 .num_resources = ARRAY_SIZE(uart2_resources),
1103 static inline void configure_usart2_pins(unsigned pins)
1105 at91_set_A_periph(AT91_PIN_PA13, 1); /* TXD2 */
1106 at91_set_A_periph(AT91_PIN_PA14, 0); /* RXD2 */
1108 if (pins & ATMEL_UART_RTS)
1109 at91_set_A_periph(AT91_PIN_PA29, 0); /* RTS2 */
1110 if (pins & ATMEL_UART_CTS)
1111 at91_set_A_periph(AT91_PIN_PA30, 0); /* CTS2 */
1114 static struct resource uart3_resources[] = {
1116 .start = AT91SAM9RL_BASE_US3,
1117 .end = AT91SAM9RL_BASE_US3 + SZ_16K - 1,
1118 .flags = IORESOURCE_MEM,
1121 .start = AT91SAM9RL_ID_US3,
1122 .end = AT91SAM9RL_ID_US3,
1123 .flags = IORESOURCE_IRQ,
1127 static struct atmel_uart_data uart3_data = {
1132 static u64 uart3_dmamask = DMA_BIT_MASK(32);
1134 static struct platform_device at91sam9rl_uart3_device = {
1135 .name = "atmel_usart",
1138 .dma_mask = &uart3_dmamask,
1139 .coherent_dma_mask = DMA_BIT_MASK(32),
1140 .platform_data = &uart3_data,
1142 .resource = uart3_resources,
1143 .num_resources = ARRAY_SIZE(uart3_resources),
1146 static inline void configure_usart3_pins(unsigned pins)
1148 at91_set_A_periph(AT91_PIN_PB0, 1); /* TXD3 */
1149 at91_set_A_periph(AT91_PIN_PB1, 0); /* RXD3 */
1151 if (pins & ATMEL_UART_RTS)
1152 at91_set_B_periph(AT91_PIN_PD4, 0); /* RTS3 */
1153 if (pins & ATMEL_UART_CTS)
1154 at91_set_B_periph(AT91_PIN_PD3, 0); /* CTS3 */
1157 static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
1159 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
1161 struct platform_device *pdev;
1162 struct atmel_uart_data *pdata;
1166 pdev = &at91sam9rl_dbgu_device;
1167 configure_dbgu_pins();
1169 case AT91SAM9RL_ID_US0:
1170 pdev = &at91sam9rl_uart0_device;
1171 configure_usart0_pins(pins);
1173 case AT91SAM9RL_ID_US1:
1174 pdev = &at91sam9rl_uart1_device;
1175 configure_usart1_pins(pins);
1177 case AT91SAM9RL_ID_US2:
1178 pdev = &at91sam9rl_uart2_device;
1179 configure_usart2_pins(pins);
1181 case AT91SAM9RL_ID_US3:
1182 pdev = &at91sam9rl_uart3_device;
1183 configure_usart3_pins(pins);
1188 pdata = pdev->dev.platform_data;
1189 pdata->num = portnr; /* update to mapped ID */
1191 if (portnr < ATMEL_MAX_UART)
1192 at91_uarts[portnr] = pdev;
1195 void __init at91_add_device_serial(void)
1199 for (i = 0; i < ATMEL_MAX_UART; i++) {
1201 platform_device_register(at91_uarts[i]);
1205 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
1206 void __init at91_add_device_serial(void) {}
1210 /* -------------------------------------------------------------------- */
1213 * These devices are always present and don't need any board-specific
1216 static int __init at91_add_standard_devices(void)
1218 at91_add_device_hdmac();
1219 at91_add_device_rtc();
1220 at91_add_device_rtt();
1221 at91_add_device_watchdog();
1222 at91_add_device_tc();
1226 arch_initcall(at91_add_standard_devices);