2 * Chip-specific setup code for the AT91SAM9x5 family
4 * Copyright (C) 2010-2012 Atmel Corporation.
6 * Licensed under GPLv2 or later.
9 #include <linux/module.h>
10 #include <linux/dma-mapping.h>
13 #include <asm/mach/arch.h>
14 #include <asm/mach/map.h>
15 #include <mach/at91sam9x5.h>
16 #include <mach/at91_pmc.h>
25 /* --------------------------------------------------------------------
27 * -------------------------------------------------------------------- */
30 * The peripheral clocks.
32 static struct clk pioAB_clk = {
34 .pmc_mask = 1 << AT91SAM9X5_ID_PIOAB,
35 .type = CLK_TYPE_PERIPHERAL,
37 static struct clk pioCD_clk = {
39 .pmc_mask = 1 << AT91SAM9X5_ID_PIOCD,
40 .type = CLK_TYPE_PERIPHERAL,
42 static struct clk smd_clk = {
44 .pmc_mask = 1 << AT91SAM9X5_ID_SMD,
45 .type = CLK_TYPE_PERIPHERAL,
47 static struct clk usart0_clk = {
49 .pmc_mask = 1 << AT91SAM9X5_ID_USART0,
50 .type = CLK_TYPE_PERIPHERAL,
52 static struct clk usart1_clk = {
54 .pmc_mask = 1 << AT91SAM9X5_ID_USART1,
55 .type = CLK_TYPE_PERIPHERAL,
57 static struct clk usart2_clk = {
59 .pmc_mask = 1 << AT91SAM9X5_ID_USART2,
60 .type = CLK_TYPE_PERIPHERAL,
62 /* USART3 clock - Only for sam9g25/sam9x25 */
63 static struct clk usart3_clk = {
65 .pmc_mask = 1 << AT91SAM9X5_ID_USART3,
66 .type = CLK_TYPE_PERIPHERAL,
68 static struct clk twi0_clk = {
70 .pmc_mask = 1 << AT91SAM9X5_ID_TWI0,
71 .type = CLK_TYPE_PERIPHERAL,
73 static struct clk twi1_clk = {
75 .pmc_mask = 1 << AT91SAM9X5_ID_TWI1,
76 .type = CLK_TYPE_PERIPHERAL,
78 static struct clk twi2_clk = {
80 .pmc_mask = 1 << AT91SAM9X5_ID_TWI2,
81 .type = CLK_TYPE_PERIPHERAL,
83 static struct clk mmc0_clk = {
85 .pmc_mask = 1 << AT91SAM9X5_ID_MCI0,
86 .type = CLK_TYPE_PERIPHERAL,
88 static struct clk spi0_clk = {
90 .pmc_mask = 1 << AT91SAM9X5_ID_SPI0,
91 .type = CLK_TYPE_PERIPHERAL,
93 static struct clk spi1_clk = {
95 .pmc_mask = 1 << AT91SAM9X5_ID_SPI1,
96 .type = CLK_TYPE_PERIPHERAL,
98 static struct clk uart0_clk = {
100 .pmc_mask = 1 << AT91SAM9X5_ID_UART0,
101 .type = CLK_TYPE_PERIPHERAL,
103 static struct clk uart1_clk = {
105 .pmc_mask = 1 << AT91SAM9X5_ID_UART1,
106 .type = CLK_TYPE_PERIPHERAL,
108 static struct clk tcb0_clk = {
110 .pmc_mask = 1 << AT91SAM9X5_ID_TCB,
111 .type = CLK_TYPE_PERIPHERAL,
113 static struct clk pwm_clk = {
115 .pmc_mask = 1 << AT91SAM9X5_ID_PWM,
116 .type = CLK_TYPE_PERIPHERAL,
118 static struct clk adc_clk = {
120 .pmc_mask = 1 << AT91SAM9X5_ID_ADC,
121 .type = CLK_TYPE_PERIPHERAL,
123 static struct clk adc_op_clk = {
124 .name = "adc_op_clk",
125 .type = CLK_TYPE_PERIPHERAL,
128 static struct clk dma0_clk = {
130 .pmc_mask = 1 << AT91SAM9X5_ID_DMA0,
131 .type = CLK_TYPE_PERIPHERAL,
133 static struct clk dma1_clk = {
135 .pmc_mask = 1 << AT91SAM9X5_ID_DMA1,
136 .type = CLK_TYPE_PERIPHERAL,
138 static struct clk uhphs_clk = {
140 .pmc_mask = 1 << AT91SAM9X5_ID_UHPHS,
141 .type = CLK_TYPE_PERIPHERAL,
143 static struct clk udphs_clk = {
145 .pmc_mask = 1 << AT91SAM9X5_ID_UDPHS,
146 .type = CLK_TYPE_PERIPHERAL,
148 /* emac0 clock - Only for sam9g25/sam9x25/sam9g35/sam9x35 */
149 static struct clk macb0_clk = {
151 .pmc_mask = 1 << AT91SAM9X5_ID_EMAC0,
152 .type = CLK_TYPE_PERIPHERAL,
154 /* lcd clock - Only for sam9g15/sam9g35/sam9x35 */
155 static struct clk lcdc_clk = {
157 .pmc_mask = 1 << AT91SAM9X5_ID_LCDC,
158 .type = CLK_TYPE_PERIPHERAL,
160 /* isi clock - Only for sam9g25 */
161 static struct clk isi_clk = {
163 .pmc_mask = 1 << AT91SAM9X5_ID_ISI,
164 .type = CLK_TYPE_PERIPHERAL,
166 static struct clk mmc1_clk = {
168 .pmc_mask = 1 << AT91SAM9X5_ID_MCI1,
169 .type = CLK_TYPE_PERIPHERAL,
171 /* emac1 clock - Only for sam9x25 */
172 static struct clk macb1_clk = {
174 .pmc_mask = 1 << AT91SAM9X5_ID_EMAC1,
175 .type = CLK_TYPE_PERIPHERAL,
177 static struct clk ssc_clk = {
179 .pmc_mask = 1 << AT91SAM9X5_ID_SSC,
180 .type = CLK_TYPE_PERIPHERAL,
182 /* can0 clock - Only for sam9x35 */
183 static struct clk can0_clk = {
185 .pmc_mask = 1 << AT91SAM9X5_ID_CAN0,
186 .type = CLK_TYPE_PERIPHERAL,
188 /* can1 clock - Only for sam9x35 */
189 static struct clk can1_clk = {
191 .pmc_mask = 1 << AT91SAM9X5_ID_CAN1,
192 .type = CLK_TYPE_PERIPHERAL,
195 static struct clk *periph_clocks[] __initdata = {
223 static struct clk_lookup periph_clocks_lookups[] = {
224 /* lookup table for DT entries */
225 CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
226 CLKDEV_CON_DEV_ID("usart", "f801c000.serial", &usart0_clk),
227 CLKDEV_CON_DEV_ID("usart", "f8020000.serial", &usart1_clk),
228 CLKDEV_CON_DEV_ID("usart", "f8024000.serial", &usart2_clk),
229 CLKDEV_CON_DEV_ID("usart", "f8028000.serial", &usart3_clk),
230 CLKDEV_CON_DEV_ID("t0_clk", "f8008000.timer", &tcb0_clk),
231 CLKDEV_CON_DEV_ID("t0_clk", "f800c000.timer", &tcb0_clk),
232 CLKDEV_CON_DEV_ID("mci_clk", "f0008000.mmc", &mmc0_clk),
233 CLKDEV_CON_DEV_ID("mci_clk", "f000c000.mmc", &mmc1_clk),
234 CLKDEV_CON_DEV_ID("dma_clk", "ffffec00.dma-controller", &dma0_clk),
235 CLKDEV_CON_DEV_ID("dma_clk", "ffffee00.dma-controller", &dma1_clk),
236 CLKDEV_CON_DEV_ID("pclk", "f0010000.ssc", &ssc_clk),
237 CLKDEV_CON_DEV_ID(NULL, "f8010000.i2c", &twi0_clk),
238 CLKDEV_CON_DEV_ID(NULL, "f8014000.i2c", &twi1_clk),
239 CLKDEV_CON_DEV_ID(NULL, "f8018000.i2c", &twi2_clk),
240 CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioAB_clk),
241 CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioAB_clk),
242 CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioCD_clk),
243 CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioCD_clk),
244 /* additional fake clock for macb_hclk */
245 CLKDEV_CON_DEV_ID("hclk", "f802c000.ethernet", &macb0_clk),
246 CLKDEV_CON_DEV_ID("hclk", "f8030000.ethernet", &macb1_clk),
247 CLKDEV_CON_DEV_ID("hclk", "600000.ohci", &uhphs_clk),
248 CLKDEV_CON_DEV_ID("ohci_clk", "600000.ohci", &uhphs_clk),
249 CLKDEV_CON_DEV_ID("ehci_clk", "700000.ehci", &uhphs_clk),
253 * The two programmable clocks.
254 * You must configure pin multiplexing to bring these signals out.
256 static struct clk pck0 = {
258 .pmc_mask = AT91_PMC_PCK0,
259 .type = CLK_TYPE_PROGRAMMABLE,
262 static struct clk pck1 = {
264 .pmc_mask = AT91_PMC_PCK1,
265 .type = CLK_TYPE_PROGRAMMABLE,
269 static void __init at91sam9x5_register_clocks(void)
273 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
274 clk_register(periph_clocks[i]);
276 clkdev_add_table(periph_clocks_lookups,
277 ARRAY_SIZE(periph_clocks_lookups));
279 if (cpu_is_at91sam9g25()
280 || cpu_is_at91sam9x25())
281 clk_register(&usart3_clk);
283 if (cpu_is_at91sam9g25()
284 || cpu_is_at91sam9x25()
285 || cpu_is_at91sam9g35()
286 || cpu_is_at91sam9x35())
287 clk_register(&macb0_clk);
289 if (cpu_is_at91sam9g15()
290 || cpu_is_at91sam9g35()
291 || cpu_is_at91sam9x35())
292 clk_register(&lcdc_clk);
294 if (cpu_is_at91sam9g25())
295 clk_register(&isi_clk);
297 if (cpu_is_at91sam9x25())
298 clk_register(&macb1_clk);
300 if (cpu_is_at91sam9x25()
301 || cpu_is_at91sam9x35()) {
302 clk_register(&can0_clk);
303 clk_register(&can1_clk);
310 /* --------------------------------------------------------------------
311 * AT91SAM9x5 processor initialization
312 * -------------------------------------------------------------------- */
314 static void __init at91sam9x5_map_io(void)
316 at91_init_sram(0, AT91SAM9X5_SRAM_BASE, AT91SAM9X5_SRAM_SIZE);
319 /* --------------------------------------------------------------------
320 * Interrupt initialization
321 * -------------------------------------------------------------------- */
323 AT91_SOC_START(sam9x5)
324 .map_io = at91sam9x5_map_io,
325 .register_clocks = at91sam9x5_register_clocks,