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Merge tag 'tty-3.3-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty
[karo-tx-linux.git] / arch / arm / mach-at91 / board-yl-9200.c
1 /*
2  * linux/arch/arm/mach-at91/board-yl-9200.c
3  *
4  * Adapted from various board files in arch/arm/mach-at91
5  *
6  * Modifications for YL-9200 platform:
7  *  Copyright (C) 2007 S. Birtles
8  *
9  * This program is free software; you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License as published by
11  * the Free Software Foundation; either version 2 of the License, or
12  * (at your option) any later version.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  * GNU General Public License for more details.
18  *
19  * You should have received a copy of the GNU General Public License
20  * along with this program; if not, write to the Free Software
21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
22  */
23
24 #include <linux/types.h>
25 #include <linux/gpio.h>
26 #include <linux/init.h>
27 #include <linux/mm.h>
28 #include <linux/module.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/platform_device.h>
31 #include <linux/spi/spi.h>
32 #include <linux/spi/ads7846.h>
33 #include <linux/mtd/physmap.h>
34 #include <linux/gpio_keys.h>
35 #include <linux/input.h>
36
37 #include <asm/setup.h>
38 #include <asm/mach-types.h>
39 #include <asm/irq.h>
40
41 #include <asm/mach/arch.h>
42 #include <asm/mach/map.h>
43 #include <asm/mach/irq.h>
44
45 #include <mach/hardware.h>
46 #include <mach/board.h>
47 #include <mach/at91rm9200_mc.h>
48 #include <mach/cpu.h>
49
50 #include "generic.h"
51
52
53 static void __init yl9200_init_early(void)
54 {
55         /* Set cpu type: PQFP */
56         at91rm9200_set_type(ARCH_REVISON_9200_PQFP);
57
58         /* Initialize processor: 18.432 MHz crystal */
59         at91_initialize(18432000);
60
61         /* Setup the LEDs D2=PB17 (timer), D3=PB16 (cpu) */
62         at91_init_leds(AT91_PIN_PB16, AT91_PIN_PB17);
63
64         /* DBGU on ttyS0. (Rx & Tx only) */
65         at91_register_uart(0, 0, 0);
66
67         /* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
68         at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
69                         | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
70                         | ATMEL_UART_RI);
71
72         /* USART0 on ttyS2. (Rx & Tx only to JP3) */
73         at91_register_uart(AT91RM9200_ID_US0, 2, 0);
74
75         /* USART3 on ttyS3. (Rx, Tx, RTS - RS485 interface) */
76         at91_register_uart(AT91RM9200_ID_US3, 3, ATMEL_UART_RTS);
77
78         /* set serial console to ttyS0 (ie, DBGU) */
79         at91_set_serial_console(0);
80 }
81
82 /*
83  * LEDs
84  */
85 static struct gpio_led yl9200_leds[] = {
86         {       /* D2 */
87                 .name                   = "led2",
88                 .gpio                   = AT91_PIN_PB17,
89                 .active_low             = 1,
90                 .default_trigger        = "timer",
91         },
92         {       /* D3 */
93                 .name                   = "led3",
94                 .gpio                   = AT91_PIN_PB16,
95                 .active_low             = 1,
96                 .default_trigger        = "heartbeat",
97         },
98         {       /* D4 */
99                 .name                   = "led4",
100                 .gpio                   = AT91_PIN_PB15,
101                 .active_low             = 1,
102         },
103         {       /* D5 */
104                 .name                   = "led5",
105                 .gpio                   = AT91_PIN_PB8,
106                 .active_low             = 1,
107         }
108 };
109
110 /*
111  * Ethernet
112  */
113 static struct macb_platform_data __initdata yl9200_eth_data = {
114         .phy_irq_pin            = AT91_PIN_PB28,
115         .is_rmii                = 1,
116 };
117
118 /*
119  * USB Host
120  */
121 static struct at91_usbh_data __initdata yl9200_usbh_data = {
122         .ports                  = 1,    /* PQFP version of AT91RM9200 */
123         .vbus_pin               = {-EINVAL, -EINVAL},
124         .overcurrent_pin= {-EINVAL, -EINVAL},
125 };
126
127 /*
128  * USB Device
129  */
130 static struct at91_udc_data __initdata yl9200_udc_data = {
131         .pullup_pin             = AT91_PIN_PC4,
132         .vbus_pin               = AT91_PIN_PC5,
133         .pullup_active_low      = 1,    /* Active Low due to PNP transistor (pg 7) */
134
135 };
136
137 /*
138  * MMC
139  */
140 static struct at91_mmc_data __initdata yl9200_mmc_data = {
141         .det_pin        = AT91_PIN_PB9,
142         .wire4          = 1,
143         .wp_pin         = -EINVAL,
144         .vcc_pin        = -EINVAL,
145 };
146
147 /*
148  * NAND Flash
149  */
150 static struct mtd_partition __initdata yl9200_nand_partition[] = {
151         {
152                 .name   = "AT91 NAND partition 1, boot",
153                 .offset = 0,
154                 .size   = SZ_256K
155         },
156         {
157                 .name   = "AT91 NAND partition 2, kernel",
158                 .offset = MTDPART_OFS_NXTBLK,
159                 .size   = (2 * SZ_1M) - SZ_256K
160         },
161         {
162                 .name   = "AT91 NAND partition 3, filesystem",
163                 .offset = MTDPART_OFS_NXTBLK,
164                 .size   = 14 * SZ_1M
165         },
166         {
167                 .name   = "AT91 NAND partition 4, storage",
168                 .offset = MTDPART_OFS_NXTBLK,
169                 .size   = SZ_16M
170         },
171         {
172                 .name   = "AT91 NAND partition 5, ext-fs",
173                 .offset = MTDPART_OFS_NXTBLK,
174                 .size   = SZ_32M
175         }
176 };
177
178 static struct atmel_nand_data __initdata yl9200_nand_data = {
179         .ale            = 6,
180         .cle            = 7,
181         .det_pin        = -EINVAL,
182         .rdy_pin        = AT91_PIN_PC14,        /* R/!B (Sheet10) */
183         .enable_pin     = AT91_PIN_PC15,        /* !CE  (Sheet10) */
184         .parts          = yl9200_nand_partition,
185         .num_parts      = ARRAY_SIZE(yl9200_nand_partition),
186 };
187
188 /*
189  * NOR Flash
190  */
191 #define YL9200_FLASH_BASE       AT91_CHIPSELECT_0
192 #define YL9200_FLASH_SIZE       SZ_16M
193
194 static struct mtd_partition yl9200_flash_partitions[] = {
195         {
196                 .name           = "Bootloader",
197                 .offset         = 0,
198                 .size           = SZ_256K,
199                 .mask_flags     = MTD_WRITEABLE,        /* force read-only */
200         },
201         {
202                 .name           = "Kernel",
203                 .offset         = MTDPART_OFS_NXTBLK,
204                 .size           = (2 * SZ_1M) - SZ_256K
205         },
206         {
207                 .name           = "Filesystem",
208                 .offset         = MTDPART_OFS_NXTBLK,
209                 .size           = MTDPART_SIZ_FULL
210         }
211 };
212
213 static struct physmap_flash_data yl9200_flash_data = {
214         .width          = 2,
215         .parts          = yl9200_flash_partitions,
216         .nr_parts       = ARRAY_SIZE(yl9200_flash_partitions),
217 };
218
219 static struct resource yl9200_flash_resources[] = {
220         {
221                 .start  = YL9200_FLASH_BASE,
222                 .end    = YL9200_FLASH_BASE + YL9200_FLASH_SIZE - 1,
223                 .flags  = IORESOURCE_MEM,
224         }
225 };
226
227 static struct platform_device yl9200_flash = {
228         .name           = "physmap-flash",
229         .id             = 0,
230         .dev            = {
231                                 .platform_data  = &yl9200_flash_data,
232                         },
233         .resource       = yl9200_flash_resources,
234         .num_resources  = ARRAY_SIZE(yl9200_flash_resources),
235 };
236
237 /*
238  * I2C (TWI)
239  */
240 static struct i2c_board_info __initdata yl9200_i2c_devices[] = {
241         {       /* EEPROM */
242                 I2C_BOARD_INFO("24c128", 0x50),
243         }
244 };
245
246 /*
247  * GPIO Buttons
248 */
249 #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
250 static struct gpio_keys_button yl9200_buttons[] = {
251         {
252                 .gpio           = AT91_PIN_PA24,
253                 .code           = BTN_2,
254                 .desc           = "SW2",
255                 .active_low     = 1,
256                 .wakeup         = 1,
257         },
258         {
259                 .gpio           = AT91_PIN_PB1,
260                 .code           = BTN_3,
261                 .desc           = "SW3",
262                 .active_low     = 1,
263                 .wakeup         = 1,
264         },
265         {
266                 .gpio           = AT91_PIN_PB2,
267                 .code           = BTN_4,
268                 .desc           = "SW4",
269                 .active_low     = 1,
270                 .wakeup         = 1,
271         },
272         {
273                 .gpio           = AT91_PIN_PB6,
274                 .code           = BTN_5,
275                 .desc           = "SW5",
276                 .active_low     = 1,
277                 .wakeup         = 1,
278         }
279 };
280
281 static struct gpio_keys_platform_data yl9200_button_data = {
282         .buttons        = yl9200_buttons,
283         .nbuttons       = ARRAY_SIZE(yl9200_buttons),
284 };
285
286 static struct platform_device yl9200_button_device = {
287         .name           = "gpio-keys",
288         .id             = -1,
289         .num_resources  = 0,
290         .dev            = {
291                 .platform_data  = &yl9200_button_data,
292         }
293 };
294
295 static void __init yl9200_add_device_buttons(void)
296 {
297         at91_set_gpio_input(AT91_PIN_PA24, 1);  /* SW2 */
298         at91_set_deglitch(AT91_PIN_PA24, 1);
299         at91_set_gpio_input(AT91_PIN_PB1, 1);   /* SW3 */
300         at91_set_deglitch(AT91_PIN_PB1, 1);
301         at91_set_gpio_input(AT91_PIN_PB2, 1);   /* SW4 */
302         at91_set_deglitch(AT91_PIN_PB2, 1);
303         at91_set_gpio_input(AT91_PIN_PB6, 1);   /* SW5 */
304         at91_set_deglitch(AT91_PIN_PB6, 1);
305
306         /* Enable buttons (Sheet 5) */
307         at91_set_gpio_output(AT91_PIN_PB7, 1);
308
309         platform_device_register(&yl9200_button_device);
310 }
311 #else
312 static void __init yl9200_add_device_buttons(void) {}
313 #endif
314
315 /*
316  * Touchscreen
317  */
318 #if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
319 static int ads7843_pendown_state(void)
320 {
321         return !at91_get_gpio_value(AT91_PIN_PB11);     /* Touchscreen PENIRQ */
322 }
323
324 static struct ads7846_platform_data ads_info = {
325         .model                  = 7843,
326         .x_min                  = 150,
327         .x_max                  = 3830,
328         .y_min                  = 190,
329         .y_max                  = 3830,
330         .vref_delay_usecs       = 100,
331
332         /* For a 8" touch-screen */
333         // .x_plate_ohms                = 603,
334         // .y_plate_ohms                = 332,
335
336         /* For a 10.4" touch-screen */
337         // .x_plate_ohms                = 611,
338         // .y_plate_ohms                = 325,
339
340         .x_plate_ohms           = 576,
341         .y_plate_ohms           = 366,
342
343         .pressure_max           = 15000, /* generally nonsense on the 7843 */
344         .debounce_max           = 1,
345         .debounce_rep           = 0,
346         .debounce_tol           = (~0),
347         .get_pendown_state      = ads7843_pendown_state,
348 };
349
350 static void __init yl9200_add_device_ts(void)
351 {
352         at91_set_gpio_input(AT91_PIN_PB11, 1);  /* Touchscreen interrupt pin */
353         at91_set_gpio_input(AT91_PIN_PB10, 1);  /* Touchscreen BUSY signal - not used! */
354 }
355 #else
356 static void __init yl9200_add_device_ts(void) {}
357 #endif
358
359 /*
360  * SPI devices
361  */
362 static struct spi_board_info yl9200_spi_devices[] = {
363 #if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
364         {       /* Touchscreen */
365                 .modalias       = "ads7846",
366                 .chip_select    = 0,
367                 .max_speed_hz   = 5000 * 26,
368                 .platform_data  = &ads_info,
369                 .irq            = AT91_PIN_PB11,
370         },
371 #endif
372         {       /* CAN */
373                 .modalias       = "mcp2510",
374                 .chip_select    = 1,
375                 .max_speed_hz   = 25000 * 26,
376                 .irq            = AT91_PIN_PC0,
377         }
378 };
379
380 /*
381  * LCD / VGA
382  *
383  * EPSON S1D13806 FB (discontinued chip)
384  * EPSON S1D13506 FB
385  */
386 #if defined(CONFIG_FB_S1D13XXX) || defined(CONFIG_FB_S1D13XXX_MODULE)
387 #include <video/s1d13xxxfb.h>
388
389
390 static void yl9200_init_video(void)
391 {
392         /* NWAIT Signal */
393         at91_set_A_periph(AT91_PIN_PC6, 0);
394
395         /* Initialization of the Static Memory Controller for Chip Select 2 */
396         at91_sys_write(AT91_SMC_CSR(2), AT91_SMC_DBW_16         /* 16 bit */
397                         | AT91_SMC_WSEN | AT91_SMC_NWS_(0x4)    /* wait states */
398                         | AT91_SMC_TDF_(0x100)                  /* float time */
399         );
400 }
401
402 static struct s1d13xxxfb_regval yl9200_s1dfb_initregs[] =
403 {
404         {S1DREG_MISC,                   0x00},  /* Miscellaneous Register*/
405         {S1DREG_COM_DISP_MODE,          0x01},  /* Display Mode Register, LCD only*/
406         {S1DREG_GPIO_CNF0,              0x00},  /* General IO Pins Configuration Register*/
407         {S1DREG_GPIO_CTL0,              0x00},  /* General IO Pins Control Register*/
408         {S1DREG_CLK_CNF,                0x11},  /* Memory Clock Configuration Register*/
409         {S1DREG_LCD_CLK_CNF,            0x10},  /* LCD Pixel Clock Configuration Register*/
410         {S1DREG_CRT_CLK_CNF,            0x12},  /* CRT/TV Pixel Clock Configuration Register*/
411         {S1DREG_MPLUG_CLK_CNF,          0x01},  /* MediaPlug Clock Configuration Register*/
412         {S1DREG_CPU2MEM_WST_SEL,        0x02},  /* CPU To Memory Wait State Select Register*/
413         {S1DREG_MEM_CNF,                0x00},  /* Memory Configuration Register*/
414         {S1DREG_SDRAM_REF_RATE,         0x04},  /* DRAM Refresh Rate Register, MCLK source*/
415         {S1DREG_SDRAM_TC0,              0x12},  /* DRAM Timings Control Register 0*/
416         {S1DREG_SDRAM_TC1,              0x02},  /* DRAM Timings Control Register 1*/
417         {S1DREG_PANEL_TYPE,             0x25},  /* Panel Type Register*/
418         {S1DREG_MOD_RATE,               0x00},  /* MOD Rate Register*/
419         {S1DREG_LCD_DISP_HWIDTH,        0x4F},  /* LCD Horizontal Display Width Register*/
420         {S1DREG_LCD_NDISP_HPER,         0x13},  /* LCD Horizontal Non-Display Period Register*/
421         {S1DREG_TFT_FPLINE_START,       0x01},  /* TFT FPLINE Start Position Register*/
422         {S1DREG_TFT_FPLINE_PWIDTH,      0x0c},  /* TFT FPLINE Pulse Width Register*/
423         {S1DREG_LCD_DISP_VHEIGHT0,      0xDF},  /* LCD Vertical Display Height Register 0*/
424         {S1DREG_LCD_DISP_VHEIGHT1,      0x01},  /* LCD Vertical Display Height Register 1*/
425         {S1DREG_LCD_NDISP_VPER,         0x2c},  /* LCD Vertical Non-Display Period Register*/
426         {S1DREG_TFT_FPFRAME_START,      0x0a},  /* TFT FPFRAME Start Position Register*/
427         {S1DREG_TFT_FPFRAME_PWIDTH,     0x02},  /* TFT FPFRAME Pulse Width Register*/
428         {S1DREG_LCD_DISP_MODE,          0x05},  /* LCD Display Mode Register*/
429         {S1DREG_LCD_MISC,               0x01},  /* LCD Miscellaneous Register*/
430         {S1DREG_LCD_DISP_START0,        0x00},  /* LCD Display Start Address Register 0*/
431         {S1DREG_LCD_DISP_START1,        0x00},  /* LCD Display Start Address Register 1*/
432         {S1DREG_LCD_DISP_START2,        0x00},  /* LCD Display Start Address Register 2*/
433         {S1DREG_LCD_MEM_OFF0,           0x80},  /* LCD Memory Address Offset Register 0*/
434         {S1DREG_LCD_MEM_OFF1,           0x02},  /* LCD Memory Address Offset Register 1*/
435         {S1DREG_LCD_PIX_PAN,            0x03},  /* LCD Pixel Panning Register*/
436         {S1DREG_LCD_DISP_FIFO_HTC,      0x00},  /* LCD Display FIFO High Threshold Control Register*/
437         {S1DREG_LCD_DISP_FIFO_LTC,      0x00},  /* LCD Display FIFO Low Threshold Control Register*/
438         {S1DREG_CRT_DISP_HWIDTH,        0x4F},  /* CRT/TV Horizontal Display Width Register*/
439         {S1DREG_CRT_NDISP_HPER,         0x13},  /* CRT/TV Horizontal Non-Display Period Register*/
440         {S1DREG_CRT_HRTC_START,         0x01},  /* CRT/TV HRTC Start Position Register*/
441         {S1DREG_CRT_HRTC_PWIDTH,        0x0B},  /* CRT/TV HRTC Pulse Width Register*/
442         {S1DREG_CRT_DISP_VHEIGHT0,      0xDF},  /* CRT/TV Vertical Display Height Register 0*/
443         {S1DREG_CRT_DISP_VHEIGHT1,      0x01},  /* CRT/TV Vertical Display Height Register 1*/
444         {S1DREG_CRT_NDISP_VPER,         0x2B},  /* CRT/TV Vertical Non-Display Period Register*/
445         {S1DREG_CRT_VRTC_START,         0x09},  /* CRT/TV VRTC Start Position Register*/
446         {S1DREG_CRT_VRTC_PWIDTH,        0x01},  /* CRT/TV VRTC Pulse Width Register*/
447         {S1DREG_TV_OUT_CTL,             0x18},  /* TV Output Control Register */
448         {S1DREG_CRT_DISP_MODE,          0x05},  /* CRT/TV Display Mode Register, 16BPP*/
449         {S1DREG_CRT_DISP_START0,        0x00},  /* CRT/TV Display Start Address Register 0*/
450         {S1DREG_CRT_DISP_START1,        0x00},  /* CRT/TV Display Start Address Register 1*/
451         {S1DREG_CRT_DISP_START2,        0x00},  /* CRT/TV Display Start Address Register 2*/
452         {S1DREG_CRT_MEM_OFF0,           0x80},  /* CRT/TV Memory Address Offset Register 0*/
453         {S1DREG_CRT_MEM_OFF1,           0x02},  /* CRT/TV Memory Address Offset Register 1*/
454         {S1DREG_CRT_PIX_PAN,            0x00},  /* CRT/TV Pixel Panning Register*/
455         {S1DREG_CRT_DISP_FIFO_HTC,      0x00},  /* CRT/TV Display FIFO High Threshold Control Register*/
456         {S1DREG_CRT_DISP_FIFO_LTC,      0x00},  /* CRT/TV Display FIFO Low Threshold Control Register*/
457         {S1DREG_LCD_CUR_CTL,            0x00},  /* LCD Ink/Cursor Control Register*/
458         {S1DREG_LCD_CUR_START,          0x01},  /* LCD Ink/Cursor Start Address Register*/
459         {S1DREG_LCD_CUR_XPOS0,          0x00},  /* LCD Cursor X Position Register 0*/
460         {S1DREG_LCD_CUR_XPOS1,          0x00},  /* LCD Cursor X Position Register 1*/
461         {S1DREG_LCD_CUR_YPOS0,          0x00},  /* LCD Cursor Y Position Register 0*/
462         {S1DREG_LCD_CUR_YPOS1,          0x00},  /* LCD Cursor Y Position Register 1*/
463         {S1DREG_LCD_CUR_BCTL0,          0x00},  /* LCD Ink/Cursor Blue Color 0 Register*/
464         {S1DREG_LCD_CUR_GCTL0,          0x00},  /* LCD Ink/Cursor Green Color 0 Register*/
465         {S1DREG_LCD_CUR_RCTL0,          0x00},  /* LCD Ink/Cursor Red Color 0 Register*/
466         {S1DREG_LCD_CUR_BCTL1,          0x1F},  /* LCD Ink/Cursor Blue Color 1 Register*/
467         {S1DREG_LCD_CUR_GCTL1,          0x3F},  /* LCD Ink/Cursor Green Color 1 Register*/
468         {S1DREG_LCD_CUR_RCTL1,          0x1F},  /* LCD Ink/Cursor Red Color 1 Register*/
469         {S1DREG_LCD_CUR_FIFO_HTC,       0x00},  /* LCD Ink/Cursor FIFO Threshold Register*/
470         {S1DREG_CRT_CUR_CTL,            0x00},  /* CRT/TV Ink/Cursor Control Register*/
471         {S1DREG_CRT_CUR_START,          0x01},  /* CRT/TV Ink/Cursor Start Address Register*/
472         {S1DREG_CRT_CUR_XPOS0,          0x00},  /* CRT/TV Cursor X Position Register 0*/
473         {S1DREG_CRT_CUR_XPOS1,          0x00},  /* CRT/TV Cursor X Position Register 1*/
474         {S1DREG_CRT_CUR_YPOS0,          0x00},  /* CRT/TV Cursor Y Position Register 0*/
475         {S1DREG_CRT_CUR_YPOS1,          0x00},  /* CRT/TV Cursor Y Position Register 1*/
476         {S1DREG_CRT_CUR_BCTL0,          0x00},  /* CRT/TV Ink/Cursor Blue Color 0 Register*/
477         {S1DREG_CRT_CUR_GCTL0,          0x00},  /* CRT/TV Ink/Cursor Green Color 0 Register*/
478         {S1DREG_CRT_CUR_RCTL0,          0x00},  /* CRT/TV Ink/Cursor Red Color 0 Register*/
479         {S1DREG_CRT_CUR_BCTL1,          0x1F},  /* CRT/TV Ink/Cursor Blue Color 1 Register*/
480         {S1DREG_CRT_CUR_GCTL1,          0x3F},  /* CRT/TV Ink/Cursor Green Color 1 Register*/
481         {S1DREG_CRT_CUR_RCTL1,          0x1F},  /* CRT/TV Ink/Cursor Red Color 1 Register*/
482         {S1DREG_CRT_CUR_FIFO_HTC,       0x00},  /* CRT/TV Ink/Cursor FIFO Threshold Register*/
483         {S1DREG_BBLT_CTL0,              0x00},  /* BitBlt Control Register 0*/
484         {S1DREG_BBLT_CTL1,              0x01},  /* BitBlt Control Register 1*/
485         {S1DREG_BBLT_CC_EXP,            0x00},  /* BitBlt ROP Code/Color Expansion Register*/
486         {S1DREG_BBLT_OP,                0x00},  /* BitBlt Operation Register*/
487         {S1DREG_BBLT_SRC_START0,        0x00},  /* BitBlt Source Start Address Register 0*/
488         {S1DREG_BBLT_SRC_START1,        0x00},  /* BitBlt Source Start Address Register 1*/
489         {S1DREG_BBLT_SRC_START2,        0x00},  /* BitBlt Source Start Address Register 2*/
490         {S1DREG_BBLT_DST_START0,        0x00},  /* BitBlt Destination Start Address Register 0*/
491         {S1DREG_BBLT_DST_START1,        0x00},  /* BitBlt Destination Start Address Register 1*/
492         {S1DREG_BBLT_DST_START2,        0x00},  /* BitBlt Destination Start Address Register 2*/
493         {S1DREG_BBLT_MEM_OFF0,          0x00},  /* BitBlt Memory Address Offset Register 0*/
494         {S1DREG_BBLT_MEM_OFF1,          0x00},  /* BitBlt Memory Address Offset Register 1*/
495         {S1DREG_BBLT_WIDTH0,            0x00},  /* BitBlt Width Register 0*/
496         {S1DREG_BBLT_WIDTH1,            0x00},  /* BitBlt Width Register 1*/
497         {S1DREG_BBLT_HEIGHT0,           0x00},  /* BitBlt Height Register 0*/
498         {S1DREG_BBLT_HEIGHT1,           0x00},  /* BitBlt Height Register 1*/
499         {S1DREG_BBLT_BGC0,              0x00},  /* BitBlt Background Color Register 0*/
500         {S1DREG_BBLT_BGC1,              0x00},  /* BitBlt Background Color Register 1*/
501         {S1DREG_BBLT_FGC0,              0x00},  /* BitBlt Foreground Color Register 0*/
502         {S1DREG_BBLT_FGC1,              0x00},  /* BitBlt Foreground Color Register 1*/
503         {S1DREG_LKUP_MODE,              0x00},  /* Look-Up Table Mode Register*/
504         {S1DREG_LKUP_ADDR,              0x00},  /* Look-Up Table Address Register*/
505         {S1DREG_PS_CNF,                 0x00},  /* Power Save Configuration Register*/
506         {S1DREG_PS_STATUS,              0x00},  /* Power Save Status Register*/
507         {S1DREG_CPU2MEM_WDOGT,          0x00},  /* CPU-to-Memory Access Watchdog Timer Register*/
508         {S1DREG_COM_DISP_MODE,          0x01},  /* Display Mode Register, LCD only*/
509 };
510
511 static struct s1d13xxxfb_pdata yl9200_s1dfb_pdata = {
512         .initregs               = yl9200_s1dfb_initregs,
513         .initregssize           = ARRAY_SIZE(yl9200_s1dfb_initregs),
514         .platform_init_video    = yl9200_init_video,
515 };
516
517 #define YL9200_FB_REG_BASE      AT91_CHIPSELECT_7
518 #define YL9200_FB_VMEM_BASE     YL9200_FB_REG_BASE + SZ_2M
519 #define YL9200_FB_VMEM_SIZE     SZ_2M
520
521 static struct resource yl9200_s1dfb_resource[] = {
522         [0] = { /* video mem */
523                 .name   = "s1d13xxxfb memory",
524                 .start  = YL9200_FB_VMEM_BASE,
525                 .end    = YL9200_FB_VMEM_BASE + YL9200_FB_VMEM_SIZE -1,
526                 .flags  = IORESOURCE_MEM,
527         },
528         [1] = { /* video registers */
529                 .name   = "s1d13xxxfb registers",
530                 .start  = YL9200_FB_REG_BASE,
531                 .end    = YL9200_FB_REG_BASE + SZ_512 -1,
532                 .flags  = IORESOURCE_MEM,
533         },
534 };
535
536 static u64 s1dfb_dmamask = DMA_BIT_MASK(32);
537
538 static struct platform_device yl9200_s1dfb_device = {
539         .name           = "s1d13806fb",
540         .id             = -1,
541         .dev    = {
542                 .dma_mask               = &s1dfb_dmamask,
543                 .coherent_dma_mask      = DMA_BIT_MASK(32),
544                 .platform_data          = &yl9200_s1dfb_pdata,
545         },
546         .resource       = yl9200_s1dfb_resource,
547         .num_resources  = ARRAY_SIZE(yl9200_s1dfb_resource),
548 };
549
550 void __init yl9200_add_device_video(void)
551 {
552         platform_device_register(&yl9200_s1dfb_device);
553 }
554 #else
555 void __init yl9200_add_device_video(void) {}
556 #endif
557
558
559 static void __init yl9200_board_init(void)
560 {
561         /* Serial */
562         at91_add_device_serial();
563         /* Ethernet */
564         at91_add_device_eth(&yl9200_eth_data);
565         /* USB Host */
566         at91_add_device_usbh(&yl9200_usbh_data);
567         /* USB Device */
568         at91_add_device_udc(&yl9200_udc_data);
569         /* I2C */
570         at91_add_device_i2c(yl9200_i2c_devices, ARRAY_SIZE(yl9200_i2c_devices));
571         /* MMC */
572         at91_add_device_mmc(0, &yl9200_mmc_data);
573         /* NAND */
574         at91_add_device_nand(&yl9200_nand_data);
575         /* NOR Flash */
576         platform_device_register(&yl9200_flash);
577 #if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
578         /* SPI */
579         at91_add_device_spi(yl9200_spi_devices, ARRAY_SIZE(yl9200_spi_devices));
580         /* Touchscreen */
581         yl9200_add_device_ts();
582 #endif
583         /* LEDs. */
584         at91_gpio_leds(yl9200_leds, ARRAY_SIZE(yl9200_leds));
585         /* Push Buttons */
586         yl9200_add_device_buttons();
587         /* VGA */
588         yl9200_add_device_video();
589 }
590
591 MACHINE_START(YL9200, "uCdragon YL-9200")
592         /* Maintainer: S.Birtles */
593         .timer          = &at91rm9200_timer,
594         .map_io         = at91_map_io,
595         .init_early     = yl9200_init_early,
596         .init_irq       = at91_init_irq_default,
597         .init_machine   = yl9200_board_init,
598 MACHINE_END