2 * linux/arch/arm/mach-at91/board-yl-9200.c
4 * Adapted from various board files in arch/arm/mach-at91
6 * Modifications for YL-9200 platform:
7 * Copyright (C) 2007 S. Birtles
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 #include <linux/types.h>
25 #include <linux/gpio.h>
26 #include <linux/init.h>
28 #include <linux/module.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/platform_device.h>
31 #include <linux/spi/spi.h>
32 #include <linux/spi/ads7846.h>
33 #include <linux/mtd/physmap.h>
34 #include <linux/gpio_keys.h>
35 #include <linux/input.h>
37 #include <asm/setup.h>
38 #include <asm/mach-types.h>
41 #include <asm/mach/arch.h>
42 #include <asm/mach/map.h>
43 #include <asm/mach/irq.h>
45 #include <mach/hardware.h>
46 #include <mach/board.h>
47 #include <mach/at91rm9200_mc.h>
48 #include <mach/at91_ramc.h>
54 static void __init yl9200_init_early(void)
56 /* Set cpu type: PQFP */
57 at91rm9200_set_type(ARCH_REVISON_9200_PQFP);
59 /* Initialize processor: 18.432 MHz crystal */
60 at91_initialize(18432000);
66 static struct gpio_led yl9200_leds[] = {
69 .gpio = AT91_PIN_PB17,
71 .default_trigger = "timer",
75 .gpio = AT91_PIN_PB16,
77 .default_trigger = "heartbeat",
81 .gpio = AT91_PIN_PB15,
94 static struct macb_platform_data __initdata yl9200_eth_data = {
95 .phy_irq_pin = AT91_PIN_PB28,
102 static struct at91_usbh_data __initdata yl9200_usbh_data = {
103 .ports = 1, /* PQFP version of AT91RM9200 */
104 .vbus_pin = {-EINVAL, -EINVAL},
105 .overcurrent_pin= {-EINVAL, -EINVAL},
111 static struct at91_udc_data __initdata yl9200_udc_data = {
112 .pullup_pin = AT91_PIN_PC4,
113 .vbus_pin = AT91_PIN_PC5,
114 .pullup_active_low = 1, /* Active Low due to PNP transistor (pg 7) */
121 static struct at91_mmc_data __initdata yl9200_mmc_data = {
122 .det_pin = AT91_PIN_PB9,
131 static struct mtd_partition __initdata yl9200_nand_partition[] = {
133 .name = "AT91 NAND partition 1, boot",
138 .name = "AT91 NAND partition 2, kernel",
139 .offset = MTDPART_OFS_NXTBLK,
140 .size = (2 * SZ_1M) - SZ_256K
143 .name = "AT91 NAND partition 3, filesystem",
144 .offset = MTDPART_OFS_NXTBLK,
148 .name = "AT91 NAND partition 4, storage",
149 .offset = MTDPART_OFS_NXTBLK,
153 .name = "AT91 NAND partition 5, ext-fs",
154 .offset = MTDPART_OFS_NXTBLK,
159 static struct atmel_nand_data __initdata yl9200_nand_data = {
163 .rdy_pin = AT91_PIN_PC14, /* R/!B (Sheet10) */
164 .enable_pin = AT91_PIN_PC15, /* !CE (Sheet10) */
165 .ecc_mode = NAND_ECC_SOFT,
166 .parts = yl9200_nand_partition,
167 .num_parts = ARRAY_SIZE(yl9200_nand_partition),
173 #define YL9200_FLASH_BASE AT91_CHIPSELECT_0
174 #define YL9200_FLASH_SIZE SZ_16M
176 static struct mtd_partition yl9200_flash_partitions[] = {
178 .name = "Bootloader",
181 .mask_flags = MTD_WRITEABLE, /* force read-only */
185 .offset = MTDPART_OFS_NXTBLK,
186 .size = (2 * SZ_1M) - SZ_256K
189 .name = "Filesystem",
190 .offset = MTDPART_OFS_NXTBLK,
191 .size = MTDPART_SIZ_FULL
195 static struct physmap_flash_data yl9200_flash_data = {
197 .parts = yl9200_flash_partitions,
198 .nr_parts = ARRAY_SIZE(yl9200_flash_partitions),
201 static struct resource yl9200_flash_resources[] = {
203 .start = YL9200_FLASH_BASE,
204 .end = YL9200_FLASH_BASE + YL9200_FLASH_SIZE - 1,
205 .flags = IORESOURCE_MEM,
209 static struct platform_device yl9200_flash = {
210 .name = "physmap-flash",
213 .platform_data = &yl9200_flash_data,
215 .resource = yl9200_flash_resources,
216 .num_resources = ARRAY_SIZE(yl9200_flash_resources),
222 static struct i2c_board_info __initdata yl9200_i2c_devices[] = {
224 I2C_BOARD_INFO("24c128", 0x50),
231 #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
232 static struct gpio_keys_button yl9200_buttons[] = {
234 .gpio = AT91_PIN_PA24,
241 .gpio = AT91_PIN_PB1,
248 .gpio = AT91_PIN_PB2,
255 .gpio = AT91_PIN_PB6,
263 static struct gpio_keys_platform_data yl9200_button_data = {
264 .buttons = yl9200_buttons,
265 .nbuttons = ARRAY_SIZE(yl9200_buttons),
268 static struct platform_device yl9200_button_device = {
273 .platform_data = &yl9200_button_data,
277 static void __init yl9200_add_device_buttons(void)
279 at91_set_gpio_input(AT91_PIN_PA24, 1); /* SW2 */
280 at91_set_deglitch(AT91_PIN_PA24, 1);
281 at91_set_gpio_input(AT91_PIN_PB1, 1); /* SW3 */
282 at91_set_deglitch(AT91_PIN_PB1, 1);
283 at91_set_gpio_input(AT91_PIN_PB2, 1); /* SW4 */
284 at91_set_deglitch(AT91_PIN_PB2, 1);
285 at91_set_gpio_input(AT91_PIN_PB6, 1); /* SW5 */
286 at91_set_deglitch(AT91_PIN_PB6, 1);
288 /* Enable buttons (Sheet 5) */
289 at91_set_gpio_output(AT91_PIN_PB7, 1);
291 platform_device_register(&yl9200_button_device);
294 static void __init yl9200_add_device_buttons(void) {}
300 #if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
301 static int ads7843_pendown_state(void)
303 return !at91_get_gpio_value(AT91_PIN_PB11); /* Touchscreen PENIRQ */
306 static struct ads7846_platform_data ads_info = {
312 .vref_delay_usecs = 100,
314 /* For a 8" touch-screen */
315 // .x_plate_ohms = 603,
316 // .y_plate_ohms = 332,
318 /* For a 10.4" touch-screen */
319 // .x_plate_ohms = 611,
320 // .y_plate_ohms = 325,
325 .pressure_max = 15000, /* generally nonsense on the 7843 */
328 .debounce_tol = (~0),
329 .get_pendown_state = ads7843_pendown_state,
332 static void __init yl9200_add_device_ts(void)
334 at91_set_gpio_input(AT91_PIN_PB11, 1); /* Touchscreen interrupt pin */
335 at91_set_gpio_input(AT91_PIN_PB10, 1); /* Touchscreen BUSY signal - not used! */
338 static void __init yl9200_add_device_ts(void) {}
344 static struct spi_board_info yl9200_spi_devices[] = {
345 #if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
347 .modalias = "ads7846",
349 .max_speed_hz = 5000 * 26,
350 .platform_data = &ads_info,
351 .irq = AT91_PIN_PB11,
355 .modalias = "mcp2510",
357 .max_speed_hz = 25000 * 26,
365 * EPSON S1D13806 FB (discontinued chip)
368 #if defined(CONFIG_FB_S1D13XXX) || defined(CONFIG_FB_S1D13XXX_MODULE)
369 #include <video/s1d13xxxfb.h>
372 static void yl9200_init_video(void)
375 at91_set_A_periph(AT91_PIN_PC6, 0);
377 /* Initialization of the Static Memory Controller for Chip Select 2 */
378 at91_ramc_write(0, AT91_SMC_CSR(2), AT91_SMC_DBW_16 /* 16 bit */
379 | AT91_SMC_WSEN | AT91_SMC_NWS_(0x4) /* wait states */
380 | AT91_SMC_TDF_(0x100) /* float time */
384 static struct s1d13xxxfb_regval yl9200_s1dfb_initregs[] =
386 {S1DREG_MISC, 0x00}, /* Miscellaneous Register*/
387 {S1DREG_COM_DISP_MODE, 0x01}, /* Display Mode Register, LCD only*/
388 {S1DREG_GPIO_CNF0, 0x00}, /* General IO Pins Configuration Register*/
389 {S1DREG_GPIO_CTL0, 0x00}, /* General IO Pins Control Register*/
390 {S1DREG_CLK_CNF, 0x11}, /* Memory Clock Configuration Register*/
391 {S1DREG_LCD_CLK_CNF, 0x10}, /* LCD Pixel Clock Configuration Register*/
392 {S1DREG_CRT_CLK_CNF, 0x12}, /* CRT/TV Pixel Clock Configuration Register*/
393 {S1DREG_MPLUG_CLK_CNF, 0x01}, /* MediaPlug Clock Configuration Register*/
394 {S1DREG_CPU2MEM_WST_SEL, 0x02}, /* CPU To Memory Wait State Select Register*/
395 {S1DREG_MEM_CNF, 0x00}, /* Memory Configuration Register*/
396 {S1DREG_SDRAM_REF_RATE, 0x04}, /* DRAM Refresh Rate Register, MCLK source*/
397 {S1DREG_SDRAM_TC0, 0x12}, /* DRAM Timings Control Register 0*/
398 {S1DREG_SDRAM_TC1, 0x02}, /* DRAM Timings Control Register 1*/
399 {S1DREG_PANEL_TYPE, 0x25}, /* Panel Type Register*/
400 {S1DREG_MOD_RATE, 0x00}, /* MOD Rate Register*/
401 {S1DREG_LCD_DISP_HWIDTH, 0x4F}, /* LCD Horizontal Display Width Register*/
402 {S1DREG_LCD_NDISP_HPER, 0x13}, /* LCD Horizontal Non-Display Period Register*/
403 {S1DREG_TFT_FPLINE_START, 0x01}, /* TFT FPLINE Start Position Register*/
404 {S1DREG_TFT_FPLINE_PWIDTH, 0x0c}, /* TFT FPLINE Pulse Width Register*/
405 {S1DREG_LCD_DISP_VHEIGHT0, 0xDF}, /* LCD Vertical Display Height Register 0*/
406 {S1DREG_LCD_DISP_VHEIGHT1, 0x01}, /* LCD Vertical Display Height Register 1*/
407 {S1DREG_LCD_NDISP_VPER, 0x2c}, /* LCD Vertical Non-Display Period Register*/
408 {S1DREG_TFT_FPFRAME_START, 0x0a}, /* TFT FPFRAME Start Position Register*/
409 {S1DREG_TFT_FPFRAME_PWIDTH, 0x02}, /* TFT FPFRAME Pulse Width Register*/
410 {S1DREG_LCD_DISP_MODE, 0x05}, /* LCD Display Mode Register*/
411 {S1DREG_LCD_MISC, 0x01}, /* LCD Miscellaneous Register*/
412 {S1DREG_LCD_DISP_START0, 0x00}, /* LCD Display Start Address Register 0*/
413 {S1DREG_LCD_DISP_START1, 0x00}, /* LCD Display Start Address Register 1*/
414 {S1DREG_LCD_DISP_START2, 0x00}, /* LCD Display Start Address Register 2*/
415 {S1DREG_LCD_MEM_OFF0, 0x80}, /* LCD Memory Address Offset Register 0*/
416 {S1DREG_LCD_MEM_OFF1, 0x02}, /* LCD Memory Address Offset Register 1*/
417 {S1DREG_LCD_PIX_PAN, 0x03}, /* LCD Pixel Panning Register*/
418 {S1DREG_LCD_DISP_FIFO_HTC, 0x00}, /* LCD Display FIFO High Threshold Control Register*/
419 {S1DREG_LCD_DISP_FIFO_LTC, 0x00}, /* LCD Display FIFO Low Threshold Control Register*/
420 {S1DREG_CRT_DISP_HWIDTH, 0x4F}, /* CRT/TV Horizontal Display Width Register*/
421 {S1DREG_CRT_NDISP_HPER, 0x13}, /* CRT/TV Horizontal Non-Display Period Register*/
422 {S1DREG_CRT_HRTC_START, 0x01}, /* CRT/TV HRTC Start Position Register*/
423 {S1DREG_CRT_HRTC_PWIDTH, 0x0B}, /* CRT/TV HRTC Pulse Width Register*/
424 {S1DREG_CRT_DISP_VHEIGHT0, 0xDF}, /* CRT/TV Vertical Display Height Register 0*/
425 {S1DREG_CRT_DISP_VHEIGHT1, 0x01}, /* CRT/TV Vertical Display Height Register 1*/
426 {S1DREG_CRT_NDISP_VPER, 0x2B}, /* CRT/TV Vertical Non-Display Period Register*/
427 {S1DREG_CRT_VRTC_START, 0x09}, /* CRT/TV VRTC Start Position Register*/
428 {S1DREG_CRT_VRTC_PWIDTH, 0x01}, /* CRT/TV VRTC Pulse Width Register*/
429 {S1DREG_TV_OUT_CTL, 0x18}, /* TV Output Control Register */
430 {S1DREG_CRT_DISP_MODE, 0x05}, /* CRT/TV Display Mode Register, 16BPP*/
431 {S1DREG_CRT_DISP_START0, 0x00}, /* CRT/TV Display Start Address Register 0*/
432 {S1DREG_CRT_DISP_START1, 0x00}, /* CRT/TV Display Start Address Register 1*/
433 {S1DREG_CRT_DISP_START2, 0x00}, /* CRT/TV Display Start Address Register 2*/
434 {S1DREG_CRT_MEM_OFF0, 0x80}, /* CRT/TV Memory Address Offset Register 0*/
435 {S1DREG_CRT_MEM_OFF1, 0x02}, /* CRT/TV Memory Address Offset Register 1*/
436 {S1DREG_CRT_PIX_PAN, 0x00}, /* CRT/TV Pixel Panning Register*/
437 {S1DREG_CRT_DISP_FIFO_HTC, 0x00}, /* CRT/TV Display FIFO High Threshold Control Register*/
438 {S1DREG_CRT_DISP_FIFO_LTC, 0x00}, /* CRT/TV Display FIFO Low Threshold Control Register*/
439 {S1DREG_LCD_CUR_CTL, 0x00}, /* LCD Ink/Cursor Control Register*/
440 {S1DREG_LCD_CUR_START, 0x01}, /* LCD Ink/Cursor Start Address Register*/
441 {S1DREG_LCD_CUR_XPOS0, 0x00}, /* LCD Cursor X Position Register 0*/
442 {S1DREG_LCD_CUR_XPOS1, 0x00}, /* LCD Cursor X Position Register 1*/
443 {S1DREG_LCD_CUR_YPOS0, 0x00}, /* LCD Cursor Y Position Register 0*/
444 {S1DREG_LCD_CUR_YPOS1, 0x00}, /* LCD Cursor Y Position Register 1*/
445 {S1DREG_LCD_CUR_BCTL0, 0x00}, /* LCD Ink/Cursor Blue Color 0 Register*/
446 {S1DREG_LCD_CUR_GCTL0, 0x00}, /* LCD Ink/Cursor Green Color 0 Register*/
447 {S1DREG_LCD_CUR_RCTL0, 0x00}, /* LCD Ink/Cursor Red Color 0 Register*/
448 {S1DREG_LCD_CUR_BCTL1, 0x1F}, /* LCD Ink/Cursor Blue Color 1 Register*/
449 {S1DREG_LCD_CUR_GCTL1, 0x3F}, /* LCD Ink/Cursor Green Color 1 Register*/
450 {S1DREG_LCD_CUR_RCTL1, 0x1F}, /* LCD Ink/Cursor Red Color 1 Register*/
451 {S1DREG_LCD_CUR_FIFO_HTC, 0x00}, /* LCD Ink/Cursor FIFO Threshold Register*/
452 {S1DREG_CRT_CUR_CTL, 0x00}, /* CRT/TV Ink/Cursor Control Register*/
453 {S1DREG_CRT_CUR_START, 0x01}, /* CRT/TV Ink/Cursor Start Address Register*/
454 {S1DREG_CRT_CUR_XPOS0, 0x00}, /* CRT/TV Cursor X Position Register 0*/
455 {S1DREG_CRT_CUR_XPOS1, 0x00}, /* CRT/TV Cursor X Position Register 1*/
456 {S1DREG_CRT_CUR_YPOS0, 0x00}, /* CRT/TV Cursor Y Position Register 0*/
457 {S1DREG_CRT_CUR_YPOS1, 0x00}, /* CRT/TV Cursor Y Position Register 1*/
458 {S1DREG_CRT_CUR_BCTL0, 0x00}, /* CRT/TV Ink/Cursor Blue Color 0 Register*/
459 {S1DREG_CRT_CUR_GCTL0, 0x00}, /* CRT/TV Ink/Cursor Green Color 0 Register*/
460 {S1DREG_CRT_CUR_RCTL0, 0x00}, /* CRT/TV Ink/Cursor Red Color 0 Register*/
461 {S1DREG_CRT_CUR_BCTL1, 0x1F}, /* CRT/TV Ink/Cursor Blue Color 1 Register*/
462 {S1DREG_CRT_CUR_GCTL1, 0x3F}, /* CRT/TV Ink/Cursor Green Color 1 Register*/
463 {S1DREG_CRT_CUR_RCTL1, 0x1F}, /* CRT/TV Ink/Cursor Red Color 1 Register*/
464 {S1DREG_CRT_CUR_FIFO_HTC, 0x00}, /* CRT/TV Ink/Cursor FIFO Threshold Register*/
465 {S1DREG_BBLT_CTL0, 0x00}, /* BitBlt Control Register 0*/
466 {S1DREG_BBLT_CTL1, 0x01}, /* BitBlt Control Register 1*/
467 {S1DREG_BBLT_CC_EXP, 0x00}, /* BitBlt ROP Code/Color Expansion Register*/
468 {S1DREG_BBLT_OP, 0x00}, /* BitBlt Operation Register*/
469 {S1DREG_BBLT_SRC_START0, 0x00}, /* BitBlt Source Start Address Register 0*/
470 {S1DREG_BBLT_SRC_START1, 0x00}, /* BitBlt Source Start Address Register 1*/
471 {S1DREG_BBLT_SRC_START2, 0x00}, /* BitBlt Source Start Address Register 2*/
472 {S1DREG_BBLT_DST_START0, 0x00}, /* BitBlt Destination Start Address Register 0*/
473 {S1DREG_BBLT_DST_START1, 0x00}, /* BitBlt Destination Start Address Register 1*/
474 {S1DREG_BBLT_DST_START2, 0x00}, /* BitBlt Destination Start Address Register 2*/
475 {S1DREG_BBLT_MEM_OFF0, 0x00}, /* BitBlt Memory Address Offset Register 0*/
476 {S1DREG_BBLT_MEM_OFF1, 0x00}, /* BitBlt Memory Address Offset Register 1*/
477 {S1DREG_BBLT_WIDTH0, 0x00}, /* BitBlt Width Register 0*/
478 {S1DREG_BBLT_WIDTH1, 0x00}, /* BitBlt Width Register 1*/
479 {S1DREG_BBLT_HEIGHT0, 0x00}, /* BitBlt Height Register 0*/
480 {S1DREG_BBLT_HEIGHT1, 0x00}, /* BitBlt Height Register 1*/
481 {S1DREG_BBLT_BGC0, 0x00}, /* BitBlt Background Color Register 0*/
482 {S1DREG_BBLT_BGC1, 0x00}, /* BitBlt Background Color Register 1*/
483 {S1DREG_BBLT_FGC0, 0x00}, /* BitBlt Foreground Color Register 0*/
484 {S1DREG_BBLT_FGC1, 0x00}, /* BitBlt Foreground Color Register 1*/
485 {S1DREG_LKUP_MODE, 0x00}, /* Look-Up Table Mode Register*/
486 {S1DREG_LKUP_ADDR, 0x00}, /* Look-Up Table Address Register*/
487 {S1DREG_PS_CNF, 0x00}, /* Power Save Configuration Register*/
488 {S1DREG_PS_STATUS, 0x00}, /* Power Save Status Register*/
489 {S1DREG_CPU2MEM_WDOGT, 0x00}, /* CPU-to-Memory Access Watchdog Timer Register*/
490 {S1DREG_COM_DISP_MODE, 0x01}, /* Display Mode Register, LCD only*/
493 static struct s1d13xxxfb_pdata yl9200_s1dfb_pdata = {
494 .initregs = yl9200_s1dfb_initregs,
495 .initregssize = ARRAY_SIZE(yl9200_s1dfb_initregs),
496 .platform_init_video = yl9200_init_video,
499 #define YL9200_FB_REG_BASE AT91_CHIPSELECT_7
500 #define YL9200_FB_VMEM_BASE YL9200_FB_REG_BASE + SZ_2M
501 #define YL9200_FB_VMEM_SIZE SZ_2M
503 static struct resource yl9200_s1dfb_resource[] = {
504 [0] = { /* video mem */
505 .name = "s1d13xxxfb memory",
506 .start = YL9200_FB_VMEM_BASE,
507 .end = YL9200_FB_VMEM_BASE + YL9200_FB_VMEM_SIZE -1,
508 .flags = IORESOURCE_MEM,
510 [1] = { /* video registers */
511 .name = "s1d13xxxfb registers",
512 .start = YL9200_FB_REG_BASE,
513 .end = YL9200_FB_REG_BASE + SZ_512 -1,
514 .flags = IORESOURCE_MEM,
518 static u64 s1dfb_dmamask = DMA_BIT_MASK(32);
520 static struct platform_device yl9200_s1dfb_device = {
521 .name = "s1d13806fb",
524 .dma_mask = &s1dfb_dmamask,
525 .coherent_dma_mask = DMA_BIT_MASK(32),
526 .platform_data = &yl9200_s1dfb_pdata,
528 .resource = yl9200_s1dfb_resource,
529 .num_resources = ARRAY_SIZE(yl9200_s1dfb_resource),
532 void __init yl9200_add_device_video(void)
534 platform_device_register(&yl9200_s1dfb_device);
537 void __init yl9200_add_device_video(void) {}
541 static void __init yl9200_board_init(void)
543 /* Setup the LEDs D2=PB17 (timer), D3=PB16 (cpu) */
544 at91_init_leds(AT91_PIN_PB16, AT91_PIN_PB17);
547 /* DBGU on ttyS0. (Rx & Tx only) */
548 at91_register_uart(0, 0, 0);
550 /* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
551 at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
552 | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
555 /* USART0 on ttyS2. (Rx & Tx only to JP3) */
556 at91_register_uart(AT91RM9200_ID_US0, 2, 0);
558 /* USART3 on ttyS3. (Rx, Tx, RTS - RS485 interface) */
559 at91_register_uart(AT91RM9200_ID_US3, 3, ATMEL_UART_RTS);
560 at91_add_device_serial();
562 at91_add_device_eth(&yl9200_eth_data);
564 at91_add_device_usbh(&yl9200_usbh_data);
566 at91_add_device_udc(&yl9200_udc_data);
568 at91_add_device_i2c(yl9200_i2c_devices, ARRAY_SIZE(yl9200_i2c_devices));
570 at91_add_device_mmc(0, &yl9200_mmc_data);
572 at91_add_device_nand(&yl9200_nand_data);
574 platform_device_register(&yl9200_flash);
575 #if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
577 at91_add_device_spi(yl9200_spi_devices, ARRAY_SIZE(yl9200_spi_devices));
579 yl9200_add_device_ts();
582 at91_gpio_leds(yl9200_leds, ARRAY_SIZE(yl9200_leds));
584 yl9200_add_device_buttons();
586 yl9200_add_device_video();
589 MACHINE_START(YL9200, "uCdragon YL-9200")
590 /* Maintainer: S.Birtles */
591 .timer = &at91rm9200_timer,
592 .map_io = at91_map_io,
593 .init_early = yl9200_init_early,
594 .init_irq = at91_init_irq_default,
595 .init_machine = yl9200_board_init,