2 * linux/arch/arm/mach-at91/clock.c
4 * Copyright (C) 2005 David Brownell
5 * Copyright (C) 2005 Ivan Kokshaysky
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/init.h>
17 #include <linux/debugfs.h>
18 #include <linux/seq_file.h>
19 #include <linux/list.h>
20 #include <linux/errno.h>
21 #include <linux/err.h>
22 #include <linux/spinlock.h>
23 #include <linux/delay.h>
24 #include <linux/clk.h>
27 #include <mach/hardware.h>
28 #include <mach/at91_pmc.h>
36 * There's a lot more which can be done with clocks, including cpufreq
37 * integration, slow clock mode support (for system suspend), letting
38 * PLLB be used at other rates (on boards that don't need USB), etc.
41 #define clk_is_primary(x) ((x)->type & CLK_TYPE_PRIMARY)
42 #define clk_is_programmable(x) ((x)->type & CLK_TYPE_PROGRAMMABLE)
43 #define clk_is_peripheral(x) ((x)->type & CLK_TYPE_PERIPHERAL)
44 #define clk_is_sys(x) ((x)->type & CLK_TYPE_SYSTEM)
48 * Chips have some kind of clocks : group them by functionality
50 #define cpu_has_utmi() ( cpu_is_at91cap9() \
51 || cpu_is_at91sam9rl() \
52 || cpu_is_at91sam9g45())
54 #define cpu_has_800M_plla() ( cpu_is_at91sam9g20() \
55 || cpu_is_at91sam9g45())
57 #define cpu_has_300M_plla() (cpu_is_at91sam9g10())
59 #define cpu_has_pllb() (!(cpu_is_at91sam9rl() \
60 || cpu_is_at91sam9g45()))
62 #define cpu_has_upll() (cpu_is_at91sam9g45())
64 /* USB host HS & FS */
65 #define cpu_has_uhp() (!cpu_is_at91sam9rl())
67 /* USB device FS only */
68 #define cpu_has_udpfs() (!(cpu_is_at91sam9rl() \
69 || cpu_is_at91sam9g45()))
71 static LIST_HEAD(clocks);
72 static DEFINE_SPINLOCK(clk_lock);
74 static u32 at91_pllb_usb_init;
77 * Four primary clock sources: two crystal oscillators (32K, main), and
78 * two PLLs. PLLA usually runs the master clock; and PLLB must run at
79 * 48 MHz (unless no USB function clocks are needed). The main clock and
80 * both PLLs are turned off to run in "slow clock mode" (system suspend).
82 static struct clk clk32k = {
84 .rate_hz = AT91_SLOW_CLOCK,
85 .users = 1, /* always on */
87 .type = CLK_TYPE_PRIMARY,
89 static struct clk main_clk = {
91 .pmc_mask = AT91_PMC_MOSCS, /* in PMC_SR */
93 .type = CLK_TYPE_PRIMARY,
95 static struct clk plla = {
98 .pmc_mask = AT91_PMC_LOCKA, /* in PMC_SR */
100 .type = CLK_TYPE_PRIMARY | CLK_TYPE_PLL,
103 static void pllb_mode(struct clk *clk, int is_on)
108 is_on = AT91_PMC_LOCKB;
109 value = at91_pllb_usb_init;
113 // REVISIT: Add work-around for AT91RM9200 Errata #26 ?
114 at91_sys_write(AT91_CKGR_PLLBR, value);
118 } while ((at91_sys_read(AT91_PMC_SR) & AT91_PMC_LOCKB) != is_on);
121 static struct clk pllb = {
124 .pmc_mask = AT91_PMC_LOCKB, /* in PMC_SR */
127 .type = CLK_TYPE_PRIMARY | CLK_TYPE_PLL,
130 static void pmc_sys_mode(struct clk *clk, int is_on)
133 at91_sys_write(AT91_PMC_SCER, clk->pmc_mask);
135 at91_sys_write(AT91_PMC_SCDR, clk->pmc_mask);
138 static void pmc_uckr_mode(struct clk *clk, int is_on)
140 unsigned int uckr = at91_sys_read(AT91_CKGR_UCKR);
142 if (cpu_is_at91sam9g45()) {
144 uckr |= AT91_PMC_BIASEN;
146 uckr &= ~AT91_PMC_BIASEN;
150 is_on = AT91_PMC_LOCKU;
151 at91_sys_write(AT91_CKGR_UCKR, uckr | clk->pmc_mask);
153 at91_sys_write(AT91_CKGR_UCKR, uckr & ~(clk->pmc_mask));
157 } while ((at91_sys_read(AT91_PMC_SR) & AT91_PMC_LOCKU) != is_on);
160 /* USB function clocks (PLLB must be 48 MHz) */
161 static struct clk udpck = {
164 .mode = pmc_sys_mode,
166 static struct clk utmi_clk = {
169 .pmc_mask = AT91_PMC_UPLLEN, /* in CKGR_UCKR */
170 .mode = pmc_uckr_mode,
171 .type = CLK_TYPE_PLL,
173 static struct clk uhpck = {
175 /*.parent = ... we choose parent at runtime */
176 .mode = pmc_sys_mode,
181 * The master clock is divided from the CPU clock (by 1-4). It's used for
182 * memory, interfaces to on-chip peripherals, the AIC, and sometimes more
183 * (e.g baud rate generation). It's sourced from one of the primary clocks.
185 static struct clk mck = {
187 .pmc_mask = AT91_PMC_MCKRDY, /* in PMC_SR */
190 static void pmc_periph_mode(struct clk *clk, int is_on)
193 at91_sys_write(AT91_PMC_PCER, clk->pmc_mask);
195 at91_sys_write(AT91_PMC_PCDR, clk->pmc_mask);
198 static struct clk __init *at91_css_to_clk(unsigned long css)
201 case AT91_PMC_CSS_SLOW:
203 case AT91_PMC_CSS_MAIN:
205 case AT91_PMC_CSS_PLLA:
207 case AT91_PMC_CSS_PLLB:
209 /* CSS_PLLB == CSS_UPLL */
211 else if (cpu_has_pllb())
219 * Associate a particular clock with a function (eg, "uart") and device.
220 * The drivers can then request the same 'function' with several different
221 * devices and not care about which clock name to use.
223 void __init at91_clock_associate(const char *id, struct device *dev, const char *func)
225 struct clk *clk = clk_get(NULL, id);
227 if (!dev || !clk || !IS_ERR(clk_get(dev, func)))
230 clk->function = func;
234 /* clocks cannot be de-registered no refcounting necessary */
235 struct clk *clk_get(struct device *dev, const char *id)
239 list_for_each_entry(clk, &clocks, node) {
240 if (strcmp(id, clk->name) == 0)
242 if (clk->function && (dev == clk->dev) && strcmp(id, clk->function) == 0)
246 return ERR_PTR(-ENOENT);
248 EXPORT_SYMBOL(clk_get);
250 void clk_put(struct clk *clk)
253 EXPORT_SYMBOL(clk_put);
255 static void __clk_enable(struct clk *clk)
258 __clk_enable(clk->parent);
259 if (clk->users++ == 0 && clk->mode)
263 int clk_enable(struct clk *clk)
267 spin_lock_irqsave(&clk_lock, flags);
269 spin_unlock_irqrestore(&clk_lock, flags);
272 EXPORT_SYMBOL(clk_enable);
274 static void __clk_disable(struct clk *clk)
276 BUG_ON(clk->users == 0);
277 if (--clk->users == 0 && clk->mode)
280 __clk_disable(clk->parent);
283 void clk_disable(struct clk *clk)
287 spin_lock_irqsave(&clk_lock, flags);
289 spin_unlock_irqrestore(&clk_lock, flags);
291 EXPORT_SYMBOL(clk_disable);
293 unsigned long clk_get_rate(struct clk *clk)
298 spin_lock_irqsave(&clk_lock, flags);
301 if (rate || !clk->parent)
305 spin_unlock_irqrestore(&clk_lock, flags);
308 EXPORT_SYMBOL(clk_get_rate);
310 /*------------------------------------------------------------------------*/
312 #ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
315 * For now, only the programmable clocks support reparenting (MCK could
316 * do this too, with care) or rate changing (the PLLs could do this too,
317 * ditto MCK but that's more for cpufreq). Drivers may reparent to get
318 * a better rate match; we don't.
321 long clk_round_rate(struct clk *clk, unsigned long rate)
325 unsigned long actual;
326 unsigned long prev = ULONG_MAX;
328 if (!clk_is_programmable(clk))
330 spin_lock_irqsave(&clk_lock, flags);
332 actual = clk->parent->rate_hz;
333 for (prescale = 0; prescale < 7; prescale++) {
337 if (actual && actual <= rate) {
338 if ((prev - rate) < (rate - actual)) {
347 spin_unlock_irqrestore(&clk_lock, flags);
348 return (prescale < 7) ? actual : -ENOENT;
350 EXPORT_SYMBOL(clk_round_rate);
352 int clk_set_rate(struct clk *clk, unsigned long rate)
356 unsigned long actual;
358 if (!clk_is_programmable(clk))
362 spin_lock_irqsave(&clk_lock, flags);
364 actual = clk->parent->rate_hz;
365 for (prescale = 0; prescale < 7; prescale++) {
366 if (actual && actual <= rate) {
369 pckr = at91_sys_read(AT91_PMC_PCKR(clk->id));
370 pckr &= AT91_PMC_CSS; /* clock selection */
371 pckr |= prescale << 2;
372 at91_sys_write(AT91_PMC_PCKR(clk->id), pckr);
373 clk->rate_hz = actual;
379 spin_unlock_irqrestore(&clk_lock, flags);
380 return (prescale < 7) ? actual : -ENOENT;
382 EXPORT_SYMBOL(clk_set_rate);
384 struct clk *clk_get_parent(struct clk *clk)
388 EXPORT_SYMBOL(clk_get_parent);
390 int clk_set_parent(struct clk *clk, struct clk *parent)
396 if (!clk_is_primary(parent) || !clk_is_programmable(clk))
399 if (cpu_is_at91sam9rl() && parent->id == AT91_PMC_CSS_PLLB)
402 spin_lock_irqsave(&clk_lock, flags);
404 clk->rate_hz = parent->rate_hz;
405 clk->parent = parent;
406 at91_sys_write(AT91_PMC_PCKR(clk->id), parent->id);
408 spin_unlock_irqrestore(&clk_lock, flags);
411 EXPORT_SYMBOL(clk_set_parent);
413 /* establish PCK0..PCKN parentage and rate */
414 static void __init init_programmable_clock(struct clk *clk)
419 pckr = at91_sys_read(AT91_PMC_PCKR(clk->id));
420 parent = at91_css_to_clk(pckr & AT91_PMC_CSS);
421 clk->parent = parent;
422 clk->rate_hz = parent->rate_hz / (1 << ((pckr & AT91_PMC_PRES) >> 2));
425 #endif /* CONFIG_AT91_PROGRAMMABLE_CLOCKS */
427 /*------------------------------------------------------------------------*/
429 #ifdef CONFIG_DEBUG_FS
431 static int at91_clk_show(struct seq_file *s, void *unused)
433 u32 scsr, pcsr, uckr = 0, sr;
436 seq_printf(s, "SCSR = %8x\n", scsr = at91_sys_read(AT91_PMC_SCSR));
437 seq_printf(s, "PCSR = %8x\n", pcsr = at91_sys_read(AT91_PMC_PCSR));
438 seq_printf(s, "MOR = %8x\n", at91_sys_read(AT91_CKGR_MOR));
439 seq_printf(s, "MCFR = %8x\n", at91_sys_read(AT91_CKGR_MCFR));
440 seq_printf(s, "PLLA = %8x\n", at91_sys_read(AT91_CKGR_PLLAR));
442 seq_printf(s, "PLLB = %8x\n", at91_sys_read(AT91_CKGR_PLLBR));
444 seq_printf(s, "UCKR = %8x\n", uckr = at91_sys_read(AT91_CKGR_UCKR));
445 seq_printf(s, "MCKR = %8x\n", at91_sys_read(AT91_PMC_MCKR));
447 seq_printf(s, "USB = %8x\n", at91_sys_read(AT91_PMC_USB));
448 seq_printf(s, "SR = %8x\n", sr = at91_sys_read(AT91_PMC_SR));
452 list_for_each_entry(clk, &clocks, node) {
455 if (clk->mode == pmc_sys_mode)
456 state = (scsr & clk->pmc_mask) ? "on" : "off";
457 else if (clk->mode == pmc_periph_mode)
458 state = (pcsr & clk->pmc_mask) ? "on" : "off";
459 else if (clk->mode == pmc_uckr_mode)
460 state = (uckr & clk->pmc_mask) ? "on" : "off";
461 else if (clk->pmc_mask)
462 state = (sr & clk->pmc_mask) ? "on" : "off";
463 else if (clk == &clk32k || clk == &main_clk)
468 seq_printf(s, "%-10s users=%2d %-3s %9ld Hz %s\n",
469 clk->name, clk->users, state, clk_get_rate(clk),
470 clk->parent ? clk->parent->name : "");
475 static int at91_clk_open(struct inode *inode, struct file *file)
477 return single_open(file, at91_clk_show, NULL);
480 static const struct file_operations at91_clk_operations = {
481 .open = at91_clk_open,
484 .release = single_release,
487 static int __init at91_clk_debugfs_init(void)
489 /* /sys/kernel/debug/at91_clk */
490 (void) debugfs_create_file("at91_clk", S_IFREG | S_IRUGO, NULL, NULL, &at91_clk_operations);
494 postcore_initcall(at91_clk_debugfs_init);
498 /*------------------------------------------------------------------------*/
500 /* Register a new clock */
501 int __init clk_register(struct clk *clk)
503 if (clk_is_peripheral(clk)) {
506 clk->mode = pmc_periph_mode;
507 list_add_tail(&clk->node, &clocks);
509 else if (clk_is_sys(clk)) {
511 clk->mode = pmc_sys_mode;
513 list_add_tail(&clk->node, &clocks);
515 #ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
516 else if (clk_is_programmable(clk)) {
517 clk->mode = pmc_sys_mode;
518 init_programmable_clock(clk);
519 list_add_tail(&clk->node, &clocks);
527 /*------------------------------------------------------------------------*/
529 static u32 __init at91_pll_rate(struct clk *pll, u32 freq, u32 reg)
534 mul = (reg >> 16) & 0x7ff;
544 static u32 __init at91_usb_rate(struct clk *pll, u32 freq, u32 reg)
546 if (pll == &pllb && (reg & AT91_PMC_USB96M))
552 static unsigned __init at91_pll_calc(unsigned main_freq, unsigned out_freq)
554 unsigned i, div = 0, mul = 0, diff = 1 << 30;
555 unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00;
557 /* PLL output max 240 MHz (or 180 MHz per errata) */
558 if (out_freq > 240000000)
561 for (i = 1; i < 256; i++) {
563 unsigned input, mul1;
566 * PLL input between 1MHz and 32MHz per spec, but lower
567 * frequences seem necessary in some cases so allow 100K.
568 * Warning: some newer products need 2MHz min.
570 input = main_freq / i;
571 if (cpu_is_at91sam9g20() && input < 2000000)
575 if (input > 32000000)
578 mul1 = out_freq / input;
579 if (cpu_is_at91sam9g20() && mul > 63)
586 diff1 = out_freq - input * mul1;
597 if (i == 256 && diff > (out_freq >> 5))
599 return ret | ((mul - 1) << 16) | div;
604 static struct clk *const standard_pmc_clocks[] __initdata = {
605 /* four primary clocks */
614 /* PLLB generated USB full speed clock init */
615 static void __init at91_pllb_usbfs_clock_init(unsigned long main_clock)
618 * USB clock init: choose 48 MHz PLLB value,
619 * disable 48MHz clock during usb peripheral suspend.
621 * REVISIT: assumes MCK doesn't derive from PLLB!
623 uhpck.parent = &pllb;
625 at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | AT91_PMC_USB96M;
626 pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init);
627 if (cpu_is_at91rm9200()) {
628 uhpck.pmc_mask = AT91RM9200_PMC_UHP;
629 udpck.pmc_mask = AT91RM9200_PMC_UDP;
630 at91_sys_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP);
631 } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() ||
632 cpu_is_at91sam9263() || cpu_is_at91sam9g20() ||
633 cpu_is_at91sam9g10() || cpu_is_at572d940hf()) {
634 uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
635 udpck.pmc_mask = AT91SAM926x_PMC_UDP;
636 } else if (cpu_is_at91cap9()) {
637 uhpck.pmc_mask = AT91CAP9_PMC_UHP;
639 at91_sys_write(AT91_CKGR_PLLBR, 0);
641 udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
642 uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
645 /* UPLL generated USB full speed clock init */
646 static void __init at91_upll_usbfs_clock_init(unsigned long main_clock)
649 * USB clock init: choose 480 MHz from UPLL,
651 unsigned int usbr = AT91_PMC_USBS_UPLL;
653 /* Setup divider by 10 to reach 48 MHz */
654 usbr |= ((10 - 1) << 8) & AT91_PMC_OHCIUSBDIV;
656 at91_sys_write(AT91_PMC_USB, usbr);
658 /* Now set uhpck values */
659 uhpck.parent = &utmi_clk;
660 uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
661 uhpck.rate_hz = utmi_clk.parent->rate_hz;
662 uhpck.rate_hz /= 1 + ((at91_sys_read(AT91_PMC_USB) & AT91_PMC_OHCIUSBDIV) >> 8);
665 int __init at91_clock_init(unsigned long main_clock)
667 unsigned tmp, freq, mckr;
669 int pll_overclock = false;
672 * When the bootloader initialized the main oscillator correctly,
673 * there's no problem using the cycle counter. But if it didn't,
674 * or when using oscillator bypass mode, we must be told the speed
679 tmp = at91_sys_read(AT91_CKGR_MCFR);
680 } while (!(tmp & AT91_PMC_MAINRDY));
681 main_clock = (tmp & AT91_PMC_MAINF) * (AT91_SLOW_CLOCK / 16);
683 main_clk.rate_hz = main_clock;
685 /* report if PLLA is more than mildly overclocked */
686 plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_sys_read(AT91_CKGR_PLLAR));
687 if (cpu_has_300M_plla()) {
688 if (plla.rate_hz > 300000000)
689 pll_overclock = true;
690 } else if (cpu_has_800M_plla()) {
691 if (plla.rate_hz > 800000000)
692 pll_overclock = true;
694 if (plla.rate_hz > 209000000)
695 pll_overclock = true;
698 pr_info("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000);
700 if (cpu_is_at91sam9g45()) {
701 mckr = at91_sys_read(AT91_PMC_MCKR);
702 plla.rate_hz /= (1 << ((mckr & AT91_PMC_PLLADIV2) >> 12)); /* plla divisor by 2 */
705 if (!cpu_has_pllb() && cpu_has_upll()) {
706 /* setup UTMI clock as the fourth primary clock
707 * (instead of pllb) */
708 utmi_clk.type |= CLK_TYPE_PRIMARY;
716 if (cpu_has_utmi()) {
718 * multiplier is hard-wired to 40
719 * (obtain the USB High Speed 480 MHz when input is 12 MHz)
721 utmi_clk.rate_hz = 40 * utmi_clk.parent->rate_hz;
728 at91_pllb_usbfs_clock_init(main_clock);
730 /* assumes that we choose UPLL for USB and not PLLA */
731 at91_upll_usbfs_clock_init(main_clock);
734 * MCK and CPU derive from one of those primary clocks.
735 * For now, assume this parentage won't change.
737 mckr = at91_sys_read(AT91_PMC_MCKR);
738 mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS);
739 freq = mck.parent->rate_hz;
740 freq /= (1 << ((mckr & AT91_PMC_PRES) >> 2)); /* prescale */
741 if (cpu_is_at91rm9200()) {
742 mck.rate_hz = freq / (1 + ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
743 } else if (cpu_is_at91sam9g20()) {
744 mck.rate_hz = (mckr & AT91_PMC_MDIV) ?
745 freq / ((mckr & AT91_PMC_MDIV) >> 7) : freq; /* mdiv ; (x >> 7) = ((x >> 8) * 2) */
746 if (mckr & AT91_PMC_PDIV)
747 freq /= 2; /* processor clock division */
748 } else if (cpu_is_at91sam9g45()) {
749 mck.rate_hz = (mckr & AT91_PMC_MDIV) == AT91SAM9_PMC_MDIV_3 ?
750 freq / 3 : freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
752 mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
755 /* Register the PMC's standard clocks */
756 for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++)
757 list_add_tail(&standard_pmc_clocks[i]->node, &clocks);
760 list_add_tail(&pllb.node, &clocks);
763 list_add_tail(&uhpck.node, &clocks);
766 list_add_tail(&udpck.node, &clocks);
769 list_add_tail(&utmi_clk.node, &clocks);
771 /* MCK and CPU clock are "always on" */
774 printk("Clocks: CPU %u MHz, master %u MHz, main %u.%03u MHz\n",
775 freq / 1000000, (unsigned) mck.rate_hz / 1000000,
776 (unsigned) main_clock / 1000000,
777 ((unsigned) main_clock % 1000000) / 1000);
783 * Several unused clocks may be active. Turn them off.
785 static int __init at91_clock_reset(void)
787 unsigned long pcdr = 0;
788 unsigned long scdr = 0;
791 list_for_each_entry(clk, &clocks, node) {
795 if (clk->mode == pmc_periph_mode)
796 pcdr |= clk->pmc_mask;
798 if (clk->mode == pmc_sys_mode)
799 scdr |= clk->pmc_mask;
801 pr_debug("Clocks: disable unused %s\n", clk->name);
804 at91_sys_write(AT91_PMC_PCDR, pcdr);
805 at91_sys_write(AT91_PMC_SCDR, scdr);
809 late_initcall(at91_clock_reset);