2 * linux/arch/arm/mach-at91/gpio.c
4 * Copyright (C) 2005 HP Labs
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
12 #include <linux/clk.h>
13 #include <linux/errno.h>
14 #include <linux/gpio.h>
15 #include <linux/interrupt.h>
16 #include <linux/irq.h>
17 #include <linux/debugfs.h>
18 #include <linux/seq_file.h>
19 #include <linux/kernel.h>
20 #include <linux/list.h>
21 #include <linux/module.h>
24 #include <mach/hardware.h>
25 #include <mach/at91_pio.h>
29 struct at91_gpio_chip {
30 struct gpio_chip chip;
31 struct at91_gpio_chip *next; /* Bank sharing same clock */
32 struct at91_gpio_bank *bank; /* Bank definition */
33 void __iomem *regbase; /* Base of register bank */
34 struct clk *clock; /* associated clock */
37 #define to_at91_gpio_chip(c) container_of(c, struct at91_gpio_chip, chip)
39 static void at91_gpiolib_dbg_show(struct seq_file *s, struct gpio_chip *chip);
40 static void at91_gpiolib_set(struct gpio_chip *chip, unsigned offset, int val);
41 static int at91_gpiolib_get(struct gpio_chip *chip, unsigned offset);
42 static int at91_gpiolib_direction_output(struct gpio_chip *chip,
43 unsigned offset, int val);
44 static int at91_gpiolib_direction_input(struct gpio_chip *chip,
47 #define AT91_GPIO_CHIP(name, base_gpio, nr_gpio) \
51 .direction_input = at91_gpiolib_direction_input, \
52 .direction_output = at91_gpiolib_direction_output, \
53 .get = at91_gpiolib_get, \
54 .set = at91_gpiolib_set, \
55 .dbg_show = at91_gpiolib_dbg_show, \
61 static struct at91_gpio_chip gpio_chip[] = {
62 AT91_GPIO_CHIP("pioA", 0x00 + PIN_BASE, 32),
63 AT91_GPIO_CHIP("pioB", 0x20 + PIN_BASE, 32),
64 AT91_GPIO_CHIP("pioC", 0x40 + PIN_BASE, 32),
65 AT91_GPIO_CHIP("pioD", 0x60 + PIN_BASE, 32),
66 AT91_GPIO_CHIP("pioE", 0x80 + PIN_BASE, 32),
69 static int gpio_banks;
71 static inline void __iomem *pin_to_controller(unsigned pin)
75 if (likely(pin < gpio_banks))
76 return gpio_chip[pin].regbase;
81 static inline unsigned pin_to_mask(unsigned pin)
84 return 1 << (pin % 32);
88 /*--------------------------------------------------------------------------*/
90 /* Not all hardware capabilities are exposed through these calls; they
91 * only encapsulate the most common features and modes. (So if you
92 * want to change signals in groups, do it directly.)
94 * Bootloaders will usually handle some of the pin multiplexing setup.
95 * The intent is certainly that by the time Linux is fully booted, all
96 * pins should have been fully initialized. These setup calls should
97 * only be used by board setup routines, or possibly in driver probe().
99 * For bootloaders doing all that setup, these calls could be inlined
100 * as NOPs so Linux won't duplicate any setup code
105 * mux the pin to the "GPIO" peripheral role.
107 int __init_or_module at91_set_GPIO_periph(unsigned pin, int use_pullup)
109 void __iomem *pio = pin_to_controller(pin);
110 unsigned mask = pin_to_mask(pin);
114 __raw_writel(mask, pio + PIO_IDR);
115 __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
116 __raw_writel(mask, pio + PIO_PER);
119 EXPORT_SYMBOL(at91_set_GPIO_periph);
123 * mux the pin to the "A" internal peripheral role.
125 int __init_or_module at91_set_A_periph(unsigned pin, int use_pullup)
127 void __iomem *pio = pin_to_controller(pin);
128 unsigned mask = pin_to_mask(pin);
133 __raw_writel(mask, pio + PIO_IDR);
134 __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
135 __raw_writel(mask, pio + PIO_ASR);
136 __raw_writel(mask, pio + PIO_PDR);
139 EXPORT_SYMBOL(at91_set_A_periph);
143 * mux the pin to the "B" internal peripheral role.
145 int __init_or_module at91_set_B_periph(unsigned pin, int use_pullup)
147 void __iomem *pio = pin_to_controller(pin);
148 unsigned mask = pin_to_mask(pin);
153 __raw_writel(mask, pio + PIO_IDR);
154 __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
155 __raw_writel(mask, pio + PIO_BSR);
156 __raw_writel(mask, pio + PIO_PDR);
159 EXPORT_SYMBOL(at91_set_B_periph);
163 * mux the pin to the gpio controller (instead of "A" or "B" peripheral), and
164 * configure it for an input.
166 int __init_or_module at91_set_gpio_input(unsigned pin, int use_pullup)
168 void __iomem *pio = pin_to_controller(pin);
169 unsigned mask = pin_to_mask(pin);
174 __raw_writel(mask, pio + PIO_IDR);
175 __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
176 __raw_writel(mask, pio + PIO_ODR);
177 __raw_writel(mask, pio + PIO_PER);
180 EXPORT_SYMBOL(at91_set_gpio_input);
184 * mux the pin to the gpio controller (instead of "A" or "B" peripheral),
185 * and configure it for an output.
187 int __init_or_module at91_set_gpio_output(unsigned pin, int value)
189 void __iomem *pio = pin_to_controller(pin);
190 unsigned mask = pin_to_mask(pin);
195 __raw_writel(mask, pio + PIO_IDR);
196 __raw_writel(mask, pio + PIO_PUDR);
197 __raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
198 __raw_writel(mask, pio + PIO_OER);
199 __raw_writel(mask, pio + PIO_PER);
202 EXPORT_SYMBOL(at91_set_gpio_output);
206 * enable/disable the glitch filter; mostly used with IRQ handling.
208 int __init_or_module at91_set_deglitch(unsigned pin, int is_on)
210 void __iomem *pio = pin_to_controller(pin);
211 unsigned mask = pin_to_mask(pin);
215 __raw_writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR));
218 EXPORT_SYMBOL(at91_set_deglitch);
221 * enable/disable the multi-driver; This is only valid for output and
222 * allows the output pin to run as an open collector output.
224 int __init_or_module at91_set_multi_drive(unsigned pin, int is_on)
226 void __iomem *pio = pin_to_controller(pin);
227 unsigned mask = pin_to_mask(pin);
232 __raw_writel(mask, pio + (is_on ? PIO_MDER : PIO_MDDR));
235 EXPORT_SYMBOL(at91_set_multi_drive);
238 * assuming the pin is muxed as a gpio output, set its value.
240 int at91_set_gpio_value(unsigned pin, int value)
242 void __iomem *pio = pin_to_controller(pin);
243 unsigned mask = pin_to_mask(pin);
247 __raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
250 EXPORT_SYMBOL(at91_set_gpio_value);
254 * read the pin's value (works even if it's not muxed as a gpio).
256 int at91_get_gpio_value(unsigned pin)
258 void __iomem *pio = pin_to_controller(pin);
259 unsigned mask = pin_to_mask(pin);
264 pdsr = __raw_readl(pio + PIO_PDSR);
265 return (pdsr & mask) != 0;
267 EXPORT_SYMBOL(at91_get_gpio_value);
269 /*--------------------------------------------------------------------------*/
273 static u32 wakeups[MAX_GPIO_BANKS];
274 static u32 backups[MAX_GPIO_BANKS];
276 static int gpio_irq_set_wake(struct irq_data *d, unsigned state)
278 unsigned mask = pin_to_mask(d->irq);
279 unsigned bank = (d->irq - PIN_BASE) / 32;
281 if (unlikely(bank >= MAX_GPIO_BANKS))
285 wakeups[bank] |= mask;
287 wakeups[bank] &= ~mask;
289 irq_set_irq_wake(gpio_chip[bank].bank->id, state);
294 void at91_gpio_suspend(void)
298 for (i = 0; i < gpio_banks; i++) {
299 void __iomem *pio = gpio_chip[i].regbase;
301 backups[i] = __raw_readl(pio + PIO_IMR);
302 __raw_writel(backups[i], pio + PIO_IDR);
303 __raw_writel(wakeups[i], pio + PIO_IER);
306 clk_disable(gpio_chip[i].clock);
308 #ifdef CONFIG_PM_DEBUG
309 printk(KERN_DEBUG "GPIO-%c may wake for %08x\n", 'A'+i, wakeups[i]);
315 void at91_gpio_resume(void)
319 for (i = 0; i < gpio_banks; i++) {
320 void __iomem *pio = gpio_chip[i].regbase;
323 clk_enable(gpio_chip[i].clock);
325 __raw_writel(wakeups[i], pio + PIO_IDR);
326 __raw_writel(backups[i], pio + PIO_IER);
331 #define gpio_irq_set_wake NULL
335 /* Several AIC controller irqs are dispatched through this GPIO handler.
336 * To use any AT91_PIN_* as an externally triggered IRQ, first call
337 * at91_set_gpio_input() then maybe enable its glitch filter.
338 * Then just request_irq() with the pin ID; it works like any ARM IRQ
339 * handler, though it always triggers on rising and falling edges.
341 * Alternatively, certain pins may be used directly as IRQ0..IRQ6 after
342 * configuring them with at91_set_a_periph() or at91_set_b_periph().
343 * IRQ0..IRQ6 should be configurable, e.g. level vs edge triggering.
346 static void gpio_irq_mask(struct irq_data *d)
348 void __iomem *pio = pin_to_controller(d->irq);
349 unsigned mask = pin_to_mask(d->irq);
352 __raw_writel(mask, pio + PIO_IDR);
355 static void gpio_irq_unmask(struct irq_data *d)
357 void __iomem *pio = pin_to_controller(d->irq);
358 unsigned mask = pin_to_mask(d->irq);
361 __raw_writel(mask, pio + PIO_IER);
364 static int gpio_irq_type(struct irq_data *d, unsigned type)
368 case IRQ_TYPE_EDGE_BOTH:
375 static struct irq_chip gpio_irqchip = {
377 .irq_disable = gpio_irq_mask,
378 .irq_mask = gpio_irq_mask,
379 .irq_unmask = gpio_irq_unmask,
380 .irq_set_type = gpio_irq_type,
381 .irq_set_wake = gpio_irq_set_wake,
384 static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
387 struct irq_data *idata = irq_desc_get_irq_data(desc);
388 struct irq_chip *chip = irq_data_get_irq_chip(idata);
389 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(idata);
390 void __iomem *pio = at91_gpio->regbase;
393 /* temporarily mask (level sensitive) parent IRQ */
394 chip->irq_ack(idata);
396 /* Reading ISR acks pending (edge triggered) GPIO interrupts.
397 * When there none are pending, we're finished unless we need
398 * to process multiple banks (like ID_PIOCDE on sam9263).
400 isr = __raw_readl(pio + PIO_ISR) & __raw_readl(pio + PIO_IMR);
402 if (!at91_gpio->next)
404 at91_gpio = at91_gpio->next;
405 pio = at91_gpio->regbase;
409 pin = at91_gpio->chip.base;
413 generic_handle_irq(pin);
418 chip->irq_unmask(idata);
419 /* now it may re-trigger */
422 /*--------------------------------------------------------------------------*/
424 #ifdef CONFIG_DEBUG_FS
426 static int at91_gpio_show(struct seq_file *s, void *unused)
431 seq_printf(s, "Pin\t");
432 for (bank = 0; bank < gpio_banks; bank++) {
433 seq_printf(s, "PIO%c\t", 'A' + bank);
435 seq_printf(s, "\n\n");
437 /* print pin status */
438 for (j = 0; j < 32; j++) {
439 seq_printf(s, "%i:\t", j);
441 for (bank = 0; bank < gpio_banks; bank++) {
442 unsigned pin = PIN_BASE + (32 * bank) + j;
443 void __iomem *pio = pin_to_controller(pin);
444 unsigned mask = pin_to_mask(pin);
446 if (__raw_readl(pio + PIO_PSR) & mask)
447 seq_printf(s, "GPIO:%s", __raw_readl(pio + PIO_PDSR) & mask ? "1" : "0");
449 seq_printf(s, "%s", __raw_readl(pio + PIO_ABSR) & mask ? "B" : "A");
460 static int at91_gpio_open(struct inode *inode, struct file *file)
462 return single_open(file, at91_gpio_show, NULL);
465 static const struct file_operations at91_gpio_operations = {
466 .open = at91_gpio_open,
469 .release = single_release,
472 static int __init at91_gpio_debugfs_init(void)
474 /* /sys/kernel/debug/at91_gpio */
475 (void) debugfs_create_file("at91_gpio", S_IFREG | S_IRUGO, NULL, NULL, &at91_gpio_operations);
478 postcore_initcall(at91_gpio_debugfs_init);
482 /*--------------------------------------------------------------------------*/
485 * This lock class tells lockdep that GPIO irqs are in a different
486 * category than their parents, so it won't report false recursion.
488 static struct lock_class_key gpio_lock_class;
491 * Called from the processor-specific init to enable GPIO interrupt support.
493 void __init at91_gpio_irq_setup(void)
496 struct at91_gpio_chip *this, *prev;
498 for (pioc = 0, pin = PIN_BASE, this = gpio_chip, prev = NULL;
500 prev = this, this++) {
501 unsigned id = this->bank->id;
504 __raw_writel(~0, this->regbase + PIO_IDR);
506 for (i = 0, pin = this->chip.base; i < 32; i++, pin++) {
507 irq_set_lockdep_class(pin, &gpio_lock_class);
510 * Can use the "simple" and not "edge" handler since it's
511 * shorter, and the AIC handles interrupts sanely.
513 irq_set_chip_and_handler(pin, &gpio_irqchip,
515 set_irq_flags(pin, IRQF_VALID);
518 /* The toplevel handler handles one bank of GPIOs, except
519 * AT91SAM9263_ID_PIOCDE handles three... PIOC is first in
520 * the list, so we only set up that handler.
522 if (prev && prev->next == this)
525 irq_set_chip_data(id, this);
526 irq_set_chained_handler(id, gpio_irq_handler);
528 pr_info("AT91: %d gpio irqs in %d banks\n", pin - PIN_BASE, gpio_banks);
531 /* gpiolib support */
532 static int at91_gpiolib_direction_input(struct gpio_chip *chip,
535 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
536 void __iomem *pio = at91_gpio->regbase;
537 unsigned mask = 1 << offset;
539 __raw_writel(mask, pio + PIO_ODR);
543 static int at91_gpiolib_direction_output(struct gpio_chip *chip,
544 unsigned offset, int val)
546 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
547 void __iomem *pio = at91_gpio->regbase;
548 unsigned mask = 1 << offset;
550 __raw_writel(mask, pio + (val ? PIO_SODR : PIO_CODR));
551 __raw_writel(mask, pio + PIO_OER);
555 static int at91_gpiolib_get(struct gpio_chip *chip, unsigned offset)
557 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
558 void __iomem *pio = at91_gpio->regbase;
559 unsigned mask = 1 << offset;
562 pdsr = __raw_readl(pio + PIO_PDSR);
563 return (pdsr & mask) != 0;
566 static void at91_gpiolib_set(struct gpio_chip *chip, unsigned offset, int val)
568 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
569 void __iomem *pio = at91_gpio->regbase;
570 unsigned mask = 1 << offset;
572 __raw_writel(mask, pio + (val ? PIO_SODR : PIO_CODR));
575 static void at91_gpiolib_dbg_show(struct seq_file *s, struct gpio_chip *chip)
579 for (i = 0; i < chip->ngpio; i++) {
580 unsigned pin = chip->base + i;
581 void __iomem *pio = pin_to_controller(pin);
582 unsigned mask = pin_to_mask(pin);
583 const char *gpio_label;
585 gpio_label = gpiochip_is_requested(chip, i);
587 seq_printf(s, "[%s] GPIO%s%d: ",
588 gpio_label, chip->label, i);
589 if (__raw_readl(pio + PIO_PSR) & mask)
590 seq_printf(s, "[gpio] %s\n",
591 at91_get_gpio_value(pin) ?
594 seq_printf(s, "[periph %s]\n",
595 __raw_readl(pio + PIO_ABSR) &
602 * Called from the processor-specific init to enable GPIO pin support.
604 void __init at91_gpio_init(struct at91_gpio_bank *data, int nr_banks)
607 struct at91_gpio_chip *at91_gpio, *last = NULL;
609 BUG_ON(nr_banks > MAX_GPIO_BANKS);
611 gpio_banks = nr_banks;
613 for (i = 0; i < nr_banks; i++) {
614 at91_gpio = &gpio_chip[i];
616 at91_gpio->bank = &data[i];
617 at91_gpio->chip.base = PIN_BASE + i * 32;
619 at91_gpio->regbase = ioremap(at91_gpio->bank->regbase, 512);
620 if (!at91_gpio->regbase) {
621 pr_err("at91_gpio.%d, failed to map registers, ignoring.\n", i);
625 at91_gpio->clock = clk_get_sys(NULL, at91_gpio->chip.label);
626 if (!at91_gpio->clock) {
627 pr_err("at91_gpio.%d, failed to get clock, ignoring.\n", i);
631 /* enable PIO controller's clock */
632 clk_enable(at91_gpio->clock);
634 /* AT91SAM9263_ID_PIOCDE groups PIOC, PIOD, PIOE */
635 if (last && last->bank->id == at91_gpio->bank->id)
636 last->next = at91_gpio;
639 gpiochip_add(&at91_gpio->chip);