2 * arch/arm/mach-at91/pm.c
3 * AT91 Power Management
5 * Copyright (C) 2005 David Brownell
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
13 #include <linux/genalloc.h>
15 #include <linux/of_address.h>
17 #include <linux/of_platform.h>
18 #include <linux/suspend.h>
20 #include <linux/clk/at91_pmc.h>
22 #include <asm/cacheflush.h>
23 #include <asm/fncpy.h>
24 #include <asm/system_misc.h>
30 * FIXME: this is needed to communicate between the pinctrl driver and
31 * the PM implementation in the machine. Possibly part of the PM
32 * implementation should be moved down into the pinctrl driver and get
33 * called as part of the generic suspend/resume path.
35 #ifdef CONFIG_PINCTRL_AT91
36 extern void at91_pinctrl_gpio_suspend(void);
37 extern void at91_pinctrl_gpio_resume(void);
40 static struct at91_pm_data pm_data;
42 #define at91_ramc_read(id, field) \
43 __raw_readl(pm_data.ramc[id] + field)
45 #define at91_ramc_write(id, field, value) \
46 __raw_writel(value, pm_data.ramc[id] + field)
48 static int at91_pm_valid_state(suspend_state_t state)
52 case PM_SUSPEND_STANDBY:
62 static suspend_state_t target_state;
65 * Called after processes are frozen, but before we shutdown devices.
67 static int at91_pm_begin(suspend_state_t state)
74 * Verify that all the clocks are correct before entering
77 static int at91_pm_verify_clocks(void)
82 scsr = readl(pm_data.pmc + AT91_PMC_SCSR);
84 /* USB must not be using PLLB */
85 if ((scsr & pm_data.uhp_udp_mask) != 0) {
86 pr_err("AT91: PM - Suspend-to-RAM with USB still active\n");
90 /* PCK0..PCK3 must be disabled, or configured to use clk32k */
91 for (i = 0; i < 4; i++) {
94 if ((scsr & (AT91_PMC_PCK0 << i)) == 0)
96 css = readl(pm_data.pmc + AT91_PMC_PCKR(i)) & AT91_PMC_CSS;
97 if (css != AT91_PMC_CSS_SLOW) {
98 pr_err("AT91: PM - Suspend-to-RAM with PCK%d src %d\n", i, css);
107 * Call this from platform driver suspend() to see how deeply to suspend.
108 * For example, some controllers (like OHCI) need one of the PLL clocks
109 * in order to act as a wakeup source, and those are not available when
110 * going into slow clock mode.
112 * REVISIT: generalize as clk_will_be_available(clk)? Other platforms have
113 * the very same problem (but not using at91 main_clk), and it'd be better
114 * to add one generic API rather than lots of platform-specific ones.
116 int at91_suspend_entering_slow_clock(void)
118 return (target_state == PM_SUSPEND_MEM);
120 EXPORT_SYMBOL(at91_suspend_entering_slow_clock);
122 static void (*at91_suspend_sram_fn)(struct at91_pm_data *);
123 extern void at91_pm_suspend_in_sram(struct at91_pm_data *pm_data);
124 extern u32 at91_pm_suspend_in_sram_sz;
126 static void at91_pm_suspend(suspend_state_t state)
128 pm_data.mode = (state == PM_SUSPEND_MEM) ? AT91_PM_SLOW_CLOCK : 0;
133 at91_suspend_sram_fn(&pm_data);
138 static int at91_pm_enter(suspend_state_t state)
140 #ifdef CONFIG_PINCTRL_AT91
141 at91_pinctrl_gpio_suspend();
145 * Suspend-to-RAM is like STANDBY plus slow clock mode, so
146 * drivers must suspend more deeply, the master clock switches
147 * to the clk32k and turns off the main oscillator
151 * Ensure that clocks are in a valid state.
153 if (!at91_pm_verify_clocks())
156 at91_pm_suspend(state);
161 * STANDBY mode has *all* drivers suspended; ignores irqs not
162 * marked as 'wakeup' event sources; and reduces DRAM power.
163 * But otherwise it's identical to PM_SUSPEND_ON: cpu idle, and
164 * nothing fancy done with main or cpu clocks.
166 case PM_SUSPEND_STANDBY:
167 at91_pm_suspend(state);
175 pr_debug("AT91: PM - bogus suspend state %d\n", state);
180 target_state = PM_SUSPEND_ON;
182 #ifdef CONFIG_PINCTRL_AT91
183 at91_pinctrl_gpio_resume();
189 * Called right prior to thawing processes.
191 static void at91_pm_end(void)
193 target_state = PM_SUSPEND_ON;
197 static const struct platform_suspend_ops at91_pm_ops = {
198 .valid = at91_pm_valid_state,
199 .begin = at91_pm_begin,
200 .enter = at91_pm_enter,
204 static struct platform_device at91_cpuidle_device = {
205 .name = "cpuidle-at91",
208 static void at91_pm_set_standby(void (*at91_standby)(void))
211 at91_cpuidle_device.dev.platform_data = at91_standby;
215 * The AT91RM9200 goes into self-refresh mode with this command, and will
216 * terminate self-refresh automatically on the next SDRAM access.
218 * Self-refresh mode is exited as soon as a memory access is made, but we don't
219 * know for sure when that happens. However, we need to restore the low-power
220 * mode if it was enabled before going idle. Restoring low-power mode while
221 * still in self-refresh is "not recommended", but seems to work.
223 static void at91rm9200_standby(void)
225 u32 lpr = at91_ramc_read(0, AT91_MC_SDRAMC_LPR);
230 "1: mcr p15, 0, %0, c7, c10, 4\n\t"
231 " str %0, [%1, %2]\n\t"
232 " str %3, [%1, %4]\n\t"
233 " mcr p15, 0, %0, c7, c0, 4\n\t"
236 : "r" (0), "r" (pm_data.ramc[0]), "r" (AT91_MC_SDRAMC_LPR),
237 "r" (1), "r" (AT91_MC_SDRAMC_SRR),
241 /* We manage both DDRAM/SDRAM controllers, we need more than one value to
244 static void at91_ddr_standby(void)
246 /* Those two values allow us to delay self-refresh activation
249 u32 saved_lpr0, saved_lpr1 = 0;
251 if (pm_data.ramc[1]) {
252 saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR);
253 lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB;
254 lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
257 saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
258 lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
259 lpr0 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
261 /* self-refresh mode now */
262 at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
264 at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1);
268 at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
270 at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1);
273 static void sama5d3_ddr_standby(void)
278 saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
279 lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
280 lpr0 |= AT91_DDRSDRC_LPCB_POWER_DOWN;
282 at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
286 at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
289 /* We manage both DDRAM/SDRAM controllers, we need more than one value to
292 static void at91sam9_sdram_standby(void)
295 u32 saved_lpr0, saved_lpr1 = 0;
297 if (pm_data.ramc[1]) {
298 saved_lpr1 = at91_ramc_read(1, AT91_SDRAMC_LPR);
299 lpr1 = saved_lpr1 & ~AT91_SDRAMC_LPCB;
300 lpr1 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
303 saved_lpr0 = at91_ramc_read(0, AT91_SDRAMC_LPR);
304 lpr0 = saved_lpr0 & ~AT91_SDRAMC_LPCB;
305 lpr0 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
307 /* self-refresh mode now */
308 at91_ramc_write(0, AT91_SDRAMC_LPR, lpr0);
310 at91_ramc_write(1, AT91_SDRAMC_LPR, lpr1);
314 at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr0);
316 at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1);
319 static const struct of_device_id const ramc_ids[] __initconst = {
320 { .compatible = "atmel,at91rm9200-sdramc", .data = at91rm9200_standby },
321 { .compatible = "atmel,at91sam9260-sdramc", .data = at91sam9_sdram_standby },
322 { .compatible = "atmel,at91sam9g45-ddramc", .data = at91_ddr_standby },
323 { .compatible = "atmel,sama5d3-ddramc", .data = sama5d3_ddr_standby },
327 static __init void at91_dt_ramc(void)
329 struct device_node *np;
330 const struct of_device_id *of_id;
332 const void *standby = NULL;
334 for_each_matching_node_and_match(np, ramc_ids, &of_id) {
335 pm_data.ramc[idx] = of_iomap(np, 0);
336 if (!pm_data.ramc[idx])
337 panic(pr_fmt("unable to map ramc[%d] cpu registers\n"), idx);
340 standby = of_id->data;
346 panic(pr_fmt("unable to find compatible ram controller node in dtb\n"));
349 pr_warn("ramc no standby function available\n");
353 at91_pm_set_standby(standby);
356 static void at91rm9200_idle(void)
359 * Disable the processor clock. The processor will be automatically
360 * re-enabled by an interrupt or by a reset.
362 writel(AT91_PMC_PCK, pm_data.pmc + AT91_PMC_SCDR);
365 static void at91sam9_idle(void)
367 writel(AT91_PMC_PCK, pm_data.pmc + AT91_PMC_SCDR);
371 static void __init at91_pm_sram_init(void)
373 struct gen_pool *sram_pool;
374 phys_addr_t sram_pbase;
375 unsigned long sram_base;
376 struct device_node *node;
377 struct platform_device *pdev = NULL;
379 for_each_compatible_node(node, NULL, "mmio-sram") {
380 pdev = of_find_device_by_node(node);
388 pr_warn("%s: failed to find sram device!\n", __func__);
392 sram_pool = gen_pool_get(&pdev->dev, NULL);
394 pr_warn("%s: sram pool unavailable!\n", __func__);
398 sram_base = gen_pool_alloc(sram_pool, at91_pm_suspend_in_sram_sz);
400 pr_warn("%s: unable to alloc sram!\n", __func__);
404 sram_pbase = gen_pool_virt_to_phys(sram_pool, sram_base);
405 at91_suspend_sram_fn = __arm_ioremap_exec(sram_pbase,
406 at91_pm_suspend_in_sram_sz, false);
407 if (!at91_suspend_sram_fn) {
408 pr_warn("SRAM: Could not map\n");
412 /* Copy the pm suspend handler to SRAM */
413 at91_suspend_sram_fn = fncpy(at91_suspend_sram_fn,
414 &at91_pm_suspend_in_sram, at91_pm_suspend_in_sram_sz);
417 static const struct of_device_id atmel_pmc_ids[] __initconst = {
418 { .compatible = "atmel,at91rm9200-pmc" },
419 { .compatible = "atmel,at91sam9260-pmc" },
420 { .compatible = "atmel,at91sam9g45-pmc" },
421 { .compatible = "atmel,at91sam9n12-pmc" },
422 { .compatible = "atmel,at91sam9x5-pmc" },
423 { .compatible = "atmel,sama5d3-pmc" },
424 { .compatible = "atmel,sama5d2-pmc" },
428 static void __init at91_pm_init(void (*pm_idle)(void))
430 struct device_node *pmc_np;
432 if (at91_cpuidle_device.dev.platform_data)
433 platform_device_register(&at91_cpuidle_device);
435 pmc_np = of_find_matching_node(NULL, atmel_pmc_ids);
436 pm_data.pmc = of_iomap(pmc_np, 0);
438 pr_err("AT91: PM not supported, PMC not found\n");
443 arm_pm_idle = pm_idle;
447 if (at91_suspend_sram_fn)
448 suspend_set_ops(&at91_pm_ops);
450 pr_info("AT91: PM not supported, due to no SRAM allocated\n");
453 void __init at91rm9200_pm_init(void)
458 * AT91RM9200 SDRAM low-power mode cannot be used with self-refresh.
460 at91_ramc_write(0, AT91_MC_SDRAMC_LPR, 0);
462 pm_data.uhp_udp_mask = AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP;
463 pm_data.memctrl = AT91_MEMCTRL_MC;
465 at91_pm_init(at91rm9200_idle);
468 void __init at91sam9260_pm_init(void)
471 pm_data.memctrl = AT91_MEMCTRL_SDRAMC;
472 pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP;
473 at91_pm_init(at91sam9_idle);
476 void __init at91sam9g45_pm_init(void)
479 pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP;
480 pm_data.memctrl = AT91_MEMCTRL_DDRSDR;
481 at91_pm_init(at91sam9_idle);
484 void __init at91sam9x5_pm_init(void)
487 pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP;
488 pm_data.memctrl = AT91_MEMCTRL_DDRSDR;
489 at91_pm_init(at91sam9_idle);
492 void __init sama5_pm_init(void)
495 pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP;
496 pm_data.memctrl = AT91_MEMCTRL_DDRSDR;