2 * AT91 Power Management
4 * Copyright (C) 2005 David Brownell
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 #ifndef __ARCH_ARM_MACH_AT91_PM
12 #define __ARCH_ARM_MACH_AT91_PM
14 #include <asm/proc-fns.h>
16 #include <mach/at91_ramc.h>
17 #include <mach/at91rm9200_sdramc.h>
20 extern void at91_pm_set_standby(void (*at91_standby)(void));
22 static inline void at91_pm_set_standby(void (*at91_standby)(void)) { }
26 * The AT91RM9200 goes into self-refresh mode with this command, and will
27 * terminate self-refresh automatically on the next SDRAM access.
29 * Self-refresh mode is exited as soon as a memory access is made, but we don't
30 * know for sure when that happens. However, we need to restore the low-power
31 * mode if it was enabled before going idle. Restoring low-power mode while
32 * still in self-refresh is "not recommended", but seems to work.
35 static inline void at91rm9200_standby(void)
37 u32 lpr = at91_ramc_read(0, AT91RM9200_SDRAMC_LPR);
42 "1: mcr p15, 0, %0, c7, c10, 4\n\t"
43 " str %0, [%1, %2]\n\t"
44 " str %3, [%1, %4]\n\t"
45 " mcr p15, 0, %0, c7, c0, 4\n\t"
48 : "r" (0), "r" (AT91_BASE_SYS), "r" (AT91RM9200_SDRAMC_LPR),
49 "r" (1), "r" (AT91RM9200_SDRAMC_SRR),
53 /* We manage both DDRAM/SDRAM controllers, we need more than one value to
56 static inline void at91_ddr_standby(void)
58 /* Those two values allow us to delay self-refresh activation
61 u32 saved_lpr0, saved_lpr1 = 0;
63 if (at91_ramc_base[1]) {
64 saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR);
65 lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB;
66 lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
69 saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
70 lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
71 lpr0 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
73 /* self-refresh mode now */
74 at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
75 if (at91_ramc_base[1])
76 at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1);
80 at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
81 if (at91_ramc_base[1])
82 at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1);
85 /* We manage both DDRAM/SDRAM controllers, we need more than one value to
88 static inline void at91sam9_sdram_standby(void)
91 u32 saved_lpr0, saved_lpr1 = 0;
93 if (at91_ramc_base[1]) {
94 saved_lpr1 = at91_ramc_read(1, AT91_SDRAMC_LPR);
95 lpr1 = saved_lpr1 & ~AT91_SDRAMC_LPCB;
96 lpr1 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
99 saved_lpr0 = at91_ramc_read(0, AT91_SDRAMC_LPR);
100 lpr0 = saved_lpr0 & ~AT91_SDRAMC_LPCB;
101 lpr0 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
103 /* self-refresh mode now */
104 at91_ramc_write(0, AT91_SDRAMC_LPR, lpr0);
105 if (at91_ramc_base[1])
106 at91_ramc_write(1, AT91_SDRAMC_LPR, lpr1);
110 at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr0);
111 if (at91_ramc_base[1])
112 at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1);