2 * Copyright (C) 2007 Atmel Corporation.
3 * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
8 #include <linux/module.h>
12 #include <asm/mach/map.h>
14 #include <mach/hardware.h>
16 #include <mach/at91_dbgu.h>
17 #include <mach/at91_pmc.h>
22 struct at91_init_soc __initdata at91_boot_soc;
24 struct at91_socinfo at91_soc_initdata;
25 EXPORT_SYMBOL(at91_soc_initdata);
27 void __init at91rm9200_set_type(int type)
29 if (type == ARCH_REVISON_9200_PQFP)
30 at91_soc_initdata.subtype = AT91_SOC_RM9200_BGA;
32 at91_soc_initdata.subtype = AT91_SOC_RM9200_PQFP;
35 void __init at91_init_irq_default(void)
37 at91_init_interrupts(at91_boot_soc.default_irq_priority);
40 void __init at91_init_interrupts(unsigned int *priority)
42 /* Initialize the AIC interrupt controller */
43 at91_aic_init(priority);
45 /* Enable GPIO interrupts */
46 at91_gpio_irq_setup();
49 static struct map_desc sram_desc[2] __initdata;
51 void __init at91_init_sram(int bank, unsigned long base, unsigned int length)
53 struct map_desc *desc = &sram_desc[bank];
55 desc->virtual = AT91_IO_VIRT_BASE - length;
57 desc->virtual -= sram_desc[bank - 1].length;
59 desc->pfn = __phys_to_pfn(base);
60 desc->length = length;
61 desc->type = MT_DEVICE;
63 pr_info("AT91: sram at 0x%lx of 0x%x mapped at 0x%lx\n",
64 base, length, desc->virtual);
66 iotable_init(desc, 1);
69 static struct map_desc at91_io_desc __initdata = {
70 .virtual = AT91_VA_BASE_SYS,
71 .pfn = __phys_to_pfn(AT91_BASE_SYS),
76 #define AT91_DBGU0 0xfffff200
77 #define AT91_DBGU1 0xffffee00
79 static void __init soc_detect(u32 dbgu_base)
83 cidr = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_CIDR);
84 socid = cidr & ~AT91_CIDR_VERSION;
87 case ARCH_ID_AT91CAP9: {
88 #ifdef CONFIG_AT91_PMC_UNIT
89 u32 pmc_ver = at91_sys_read(AT91_PMC_VER);
91 if (pmc_ver == ARCH_REVISION_CAP9_B)
92 at91_soc_initdata.subtype = AT91_SOC_CAP9_REV_B;
93 else if (pmc_ver == ARCH_REVISION_CAP9_C)
94 at91_soc_initdata.subtype = AT91_SOC_CAP9_REV_C;
96 at91_soc_initdata.type = AT91_SOC_CAP9;
97 at91_boot_soc = at91cap9_soc;
101 case ARCH_ID_AT91RM9200:
102 at91_soc_initdata.type = AT91_SOC_RM9200;
103 at91_boot_soc = at91rm9200_soc;
106 case ARCH_ID_AT91SAM9260:
107 at91_soc_initdata.type = AT91_SOC_SAM9260;
108 at91_boot_soc = at91sam9260_soc;
111 case ARCH_ID_AT91SAM9261:
112 at91_soc_initdata.type = AT91_SOC_SAM9261;
113 at91_boot_soc = at91sam9261_soc;
116 case ARCH_ID_AT91SAM9263:
117 at91_soc_initdata.type = AT91_SOC_SAM9263;
118 at91_boot_soc = at91sam9263_soc;
121 case ARCH_ID_AT91SAM9G20:
122 at91_soc_initdata.type = AT91_SOC_SAM9G20;
123 at91_boot_soc = at91sam9260_soc;
126 case ARCH_ID_AT91SAM9G45:
127 at91_soc_initdata.type = AT91_SOC_SAM9G45;
128 if (cidr == ARCH_ID_AT91SAM9G45ES)
129 at91_soc_initdata.subtype = AT91_SOC_SAM9G45ES;
130 at91_boot_soc = at91sam9g45_soc;
133 case ARCH_ID_AT91SAM9RL64:
134 at91_soc_initdata.type = AT91_SOC_SAM9RL;
135 at91_boot_soc = at91sam9rl_soc;
138 case ARCH_ID_AT91SAM9X5:
139 at91_soc_initdata.type = AT91_SOC_SAM9X5;
140 at91_boot_soc = at91sam9x5_soc;
145 if ((cidr & ~AT91_CIDR_EXT) == ARCH_ID_AT91SAM9G10) {
146 at91_soc_initdata.type = AT91_SOC_SAM9G10;
147 at91_boot_soc = at91sam9261_soc;
150 else if ((cidr & AT91_CIDR_ARCH) == ARCH_FAMILY_AT91SAM9XE) {
151 at91_soc_initdata.type = AT91_SOC_SAM9260;
152 at91_soc_initdata.subtype = AT91_SOC_SAM9XE;
153 at91_boot_soc = at91sam9260_soc;
156 if (!at91_soc_is_detected())
159 at91_soc_initdata.cidr = cidr;
161 /* sub version of soc */
162 at91_soc_initdata.exid = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_EXID);
164 if (at91_soc_initdata.type == AT91_SOC_SAM9G45) {
165 switch (at91_soc_initdata.exid) {
166 case ARCH_EXID_AT91SAM9M10:
167 at91_soc_initdata.subtype = AT91_SOC_SAM9M10;
169 case ARCH_EXID_AT91SAM9G46:
170 at91_soc_initdata.subtype = AT91_SOC_SAM9G46;
172 case ARCH_EXID_AT91SAM9M11:
173 at91_soc_initdata.subtype = AT91_SOC_SAM9M11;
178 if (at91_soc_initdata.type == AT91_SOC_SAM9X5) {
179 switch (at91_soc_initdata.exid) {
180 case ARCH_EXID_AT91SAM9G15:
181 at91_soc_initdata.subtype = AT91_SOC_SAM9G15;
183 case ARCH_EXID_AT91SAM9G35:
184 at91_soc_initdata.subtype = AT91_SOC_SAM9G35;
186 case ARCH_EXID_AT91SAM9X35:
187 at91_soc_initdata.subtype = AT91_SOC_SAM9X35;
189 case ARCH_EXID_AT91SAM9G25:
190 at91_soc_initdata.subtype = AT91_SOC_SAM9G25;
192 case ARCH_EXID_AT91SAM9X25:
193 at91_soc_initdata.subtype = AT91_SOC_SAM9X25;
199 static const char *soc_name[] = {
200 [AT91_SOC_RM9200] = "at91rm9200",
201 [AT91_SOC_CAP9] = "at91cap9",
202 [AT91_SOC_SAM9260] = "at91sam9260",
203 [AT91_SOC_SAM9261] = "at91sam9261",
204 [AT91_SOC_SAM9263] = "at91sam9263",
205 [AT91_SOC_SAM9G10] = "at91sam9g10",
206 [AT91_SOC_SAM9G20] = "at91sam9g20",
207 [AT91_SOC_SAM9G45] = "at91sam9g45",
208 [AT91_SOC_SAM9RL] = "at91sam9rl",
209 [AT91_SOC_SAM9X5] = "at91sam9x5",
210 [AT91_SOC_NONE] = "Unknown"
213 const char *at91_get_soc_type(struct at91_socinfo *c)
215 return soc_name[c->type];
217 EXPORT_SYMBOL(at91_get_soc_type);
219 static const char *soc_subtype_name[] = {
220 [AT91_SOC_RM9200_BGA] = "at91rm9200 BGA",
221 [AT91_SOC_RM9200_PQFP] = "at91rm9200 PQFP",
222 [AT91_SOC_CAP9_REV_B] = "at91cap9 revB",
223 [AT91_SOC_CAP9_REV_C] = "at91cap9 revC",
224 [AT91_SOC_SAM9XE] = "at91sam9xe",
225 [AT91_SOC_SAM9G45ES] = "at91sam9g45es",
226 [AT91_SOC_SAM9M10] = "at91sam9m10",
227 [AT91_SOC_SAM9G46] = "at91sam9g46",
228 [AT91_SOC_SAM9M11] = "at91sam9m11",
229 [AT91_SOC_SAM9G15] = "at91sam9g15",
230 [AT91_SOC_SAM9G35] = "at91sam9g35",
231 [AT91_SOC_SAM9X35] = "at91sam9x35",
232 [AT91_SOC_SAM9G25] = "at91sam9g25",
233 [AT91_SOC_SAM9X25] = "at91sam9x25",
234 [AT91_SOC_SUBTYPE_NONE] = "Unknown"
237 const char *at91_get_soc_subtype(struct at91_socinfo *c)
239 return soc_subtype_name[c->subtype];
241 EXPORT_SYMBOL(at91_get_soc_subtype);
243 void __init at91_map_io(void)
245 /* Map peripherals */
246 iotable_init(&at91_io_desc, 1);
248 at91_soc_initdata.type = AT91_SOC_NONE;
249 at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
251 soc_detect(AT91_DBGU0);
252 if (!at91_soc_is_detected())
253 soc_detect(AT91_DBGU1);
255 if (!at91_soc_is_detected())
256 panic("AT91: Impossible to detect the SOC type");
258 pr_info("AT91: Detected soc type: %s\n",
259 at91_get_soc_type(&at91_soc_initdata));
260 pr_info("AT91: Detected soc subtype: %s\n",
261 at91_get_soc_subtype(&at91_soc_initdata));
263 if (!at91_soc_is_enabled())
264 panic("AT91: Soc not enabled");
266 if (at91_boot_soc.map_io)
267 at91_boot_soc.map_io();
270 void __init at91_initialize(unsigned long main_clock)
272 /* Init clock subsystem */
273 at91_clock_init(main_clock);
275 /* Register the processor-specific clocks */
276 at91_boot_soc.register_clocks();
278 at91_boot_soc.init();