2 * linux/arch/arm/mach-clps711x/core.c
4 * Core support for the CLPS711x-based machines.
6 * Copyright (C) 2001,2011 Deep Blue Solutions Ltd
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 #include <linux/init.h>
24 #include <linux/sizes.h>
25 #include <linux/interrupt.h>
26 #include <linux/irq.h>
27 #include <linux/clk.h>
28 #include <linux/clkdev.h>
29 #include <linux/clockchips.h>
30 #include <linux/clk-provider.h>
32 #include <asm/mach/map.h>
33 #include <asm/mach/time.h>
34 #include <asm/system_misc.h>
36 #include <mach/hardware.h>
38 static struct clk *clk_pll, *clk_bus, *clk_uart, *clk_timerl, *clk_timerh,
42 * This maps the generic CLPS711x registers
44 static struct map_desc clps711x_io_desc[] __initdata = {
46 .virtual = (unsigned long)CLPS711X_VIRT_BASE,
47 .pfn = __phys_to_pfn(CLPS711X_PHYS_BASE),
53 void __init clps711x_map_io(void)
55 iotable_init(clps711x_io_desc, ARRAY_SIZE(clps711x_io_desc));
58 static void int1_mask(struct irq_data *d)
62 intmr1 = clps_readl(INTMR1);
63 intmr1 &= ~(1 << d->irq);
64 clps_writel(intmr1, INTMR1);
67 static void int1_ack(struct irq_data *d)
71 static void int1_eoi(struct irq_data *d)
74 case IRQ_CSINT: clps_writel(0, COEOI); break;
75 case IRQ_TC1OI: clps_writel(0, TC1EOI); break;
76 case IRQ_TC2OI: clps_writel(0, TC2EOI); break;
77 case IRQ_RTCMI: clps_writel(0, RTCEOI); break;
78 case IRQ_TINT: clps_writel(0, TEOI); break;
79 case IRQ_UMSINT: clps_writel(0, UMSEOI); break;
83 static void int1_unmask(struct irq_data *d)
87 intmr1 = clps_readl(INTMR1);
88 intmr1 |= 1 << d->irq;
89 clps_writel(intmr1, INTMR1);
92 static struct irq_chip int1_chip = {
93 .name = "Interrupt Vector 1 ",
96 .irq_mask = int1_mask,
97 .irq_unmask = int1_unmask,
100 static void int2_mask(struct irq_data *d)
104 intmr2 = clps_readl(INTMR2);
105 intmr2 &= ~(1 << (d->irq - 16));
106 clps_writel(intmr2, INTMR2);
109 static void int2_ack(struct irq_data *d)
113 static void int2_eoi(struct irq_data *d)
116 case IRQ_KBDINT: clps_writel(0, KBDEOI); break;
120 static void int2_unmask(struct irq_data *d)
124 intmr2 = clps_readl(INTMR2);
125 intmr2 |= 1 << (d->irq - 16);
126 clps_writel(intmr2, INTMR2);
129 static struct irq_chip int2_chip = {
130 .name = "Interrupt Vector 2 ",
133 .irq_mask = int2_mask,
134 .irq_unmask = int2_unmask,
137 struct clps711x_irqdesc {
139 struct irq_chip *chip;
140 irq_flow_handler_t handle;
143 static struct clps711x_irqdesc clps711x_irqdescs[] __initdata = {
144 { IRQ_CSINT, &int1_chip, handle_fasteoi_irq, },
145 { IRQ_EINT1, &int1_chip, handle_level_irq, },
146 { IRQ_EINT2, &int1_chip, handle_level_irq, },
147 { IRQ_EINT3, &int1_chip, handle_level_irq, },
148 { IRQ_TC1OI, &int1_chip, handle_fasteoi_irq, },
149 { IRQ_TC2OI, &int1_chip, handle_fasteoi_irq, },
150 { IRQ_RTCMI, &int1_chip, handle_fasteoi_irq, },
151 { IRQ_TINT, &int1_chip, handle_fasteoi_irq, },
152 { IRQ_UTXINT1, &int1_chip, handle_level_irq, },
153 { IRQ_URXINT1, &int1_chip, handle_level_irq, },
154 { IRQ_UMSINT, &int1_chip, handle_fasteoi_irq, },
155 { IRQ_SSEOTI, &int1_chip, handle_level_irq, },
156 { IRQ_KBDINT, &int2_chip, handle_fasteoi_irq, },
157 { IRQ_SS2RX, &int2_chip, handle_level_irq, },
158 { IRQ_SS2TX, &int2_chip, handle_level_irq, },
159 { IRQ_UTXINT2, &int2_chip, handle_level_irq, },
160 { IRQ_URXINT2, &int2_chip, handle_level_irq, },
163 void __init clps711x_init_irq(void)
167 /* Disable interrupts */
168 clps_writel(0, INTMR1);
169 clps_writel(0, INTMR2);
170 clps_writel(0, INTMR3);
172 /* Clear down any pending interrupts */
173 clps_writel(0, BLEOI);
174 clps_writel(0, MCEOI);
175 clps_writel(0, COEOI);
176 clps_writel(0, TC1EOI);
177 clps_writel(0, TC2EOI);
178 clps_writel(0, RTCEOI);
179 clps_writel(0, TEOI);
180 clps_writel(0, UMSEOI);
181 clps_writel(0, KBDEOI);
182 clps_writel(0, SRXEOF);
183 clps_writel(0xffffffff, DAISR);
185 for (i = 0; i < ARRAY_SIZE(clps711x_irqdescs); i++) {
186 irq_set_chip_and_handler(clps711x_irqdescs[i].nr,
187 clps711x_irqdescs[i].chip,
188 clps711x_irqdescs[i].handle);
189 set_irq_flags(clps711x_irqdescs[i].nr,
190 IRQF_VALID | IRQF_PROBE);
194 static void clps711x_clockevent_set_mode(enum clock_event_mode mode,
195 struct clock_event_device *evt)
199 static struct clock_event_device clockevent_clps711x = {
200 .name = "CLPS711x Clockevents",
202 .features = CLOCK_EVT_FEAT_PERIODIC,
203 .set_mode = clps711x_clockevent_set_mode,
206 static irqreturn_t clps711x_timer_interrupt(int irq, void *dev_id)
208 clockevent_clps711x.event_handler(&clockevent_clps711x);
213 static struct irqaction clps711x_timer_irq = {
214 .name = "CLPS711x Timer Tick",
215 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
216 .handler = clps711x_timer_interrupt,
219 static void add_fixed_clk(struct clk *clk, const char *name, int rate)
221 clk = clk_register_fixed_rate(NULL, name, NULL, CLK_IS_ROOT, rate);
222 clk_register_clkdev(clk, name, NULL);
225 static void __init clps711x_timer_init(void)
227 int osc, ext, pll, cpu, bus, timl, timh, uart, spi;
233 tmp = clps_readl(PLLR) >> 24;
235 pll = (osc * tmp) / 2;
237 pll = 73728000; /* Default value */
239 tmp = clps_readl(SYSFLG2);
240 if (tmp & SYSFLG2_CKMODE) {
255 if (tmp & SYSFLG2_CKMODE) {
256 tmp = clps_readl(SYSCON2);
257 if (tmp & SYSCON2_OSTB)
266 /* All clocks are fixed */
267 add_fixed_clk(clk_pll, "pll", pll);
268 add_fixed_clk(clk_bus, "bus", bus);
269 add_fixed_clk(clk_uart, "uart", uart);
270 add_fixed_clk(clk_timerl, "timer_lf", timl);
271 add_fixed_clk(clk_timerh, "timer_hf", timh);
272 add_fixed_clk(clk_tint, "tint", 64);
273 add_fixed_clk(clk_spi, "spi", spi);
275 pr_info("CPU frequency set at %i Hz.\n", cpu);
277 clps_writew(DIV_ROUND_CLOSEST(timh, HZ), TC2D);
279 tmp = clps_readl(SYSCON1);
280 tmp |= SYSCON1_TC2S | SYSCON1_TC2M;
281 clps_writel(tmp, SYSCON1);
283 clockevents_config_and_register(&clockevent_clps711x, timh, 1, 0xffff);
285 setup_irq(IRQ_TC2OI, &clps711x_timer_irq);
288 struct sys_timer clps711x_timer = {
289 .init = clps711x_timer_init,
292 void clps711x_restart(char mode, const char *cmd)
297 static void clps711x_idle(void)
299 clps_writel(1, HALT);
300 __asm__ __volatile__(
305 static int __init clps711x_idle_init(void)
307 arm_pm_idle = clps711x_idle;
311 arch_initcall(clps711x_idle_init);