2 * linux/arch/arm/mach-clps711x/core.c
4 * Core support for the CLPS711x-based machines.
6 * Copyright (C) 2001,2011 Deep Blue Solutions Ltd
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 #include <linux/init.h>
24 #include <linux/interrupt.h>
25 #include <linux/irq.h>
26 #include <linux/clk.h>
27 #include <linux/clkdev.h>
28 #include <linux/clk-provider.h>
30 #include <asm/sizes.h>
31 #include <asm/mach/map.h>
32 #include <asm/mach/time.h>
33 #include <asm/system_misc.h>
35 #include <mach/hardware.h>
37 static struct clk *clk_pll, *clk_bus, *clk_uart, *clk_timerl, *clk_timerh,
39 static unsigned long latch;
42 * This maps the generic CLPS711x registers
44 static struct map_desc clps711x_io_desc[] __initdata = {
46 .virtual = (unsigned long)CLPS711X_VIRT_BASE,
47 .pfn = __phys_to_pfn(CLPS711X_PHYS_BASE),
53 void __init clps711x_map_io(void)
55 iotable_init(clps711x_io_desc, ARRAY_SIZE(clps711x_io_desc));
58 static void int1_mask(struct irq_data *d)
62 intmr1 = clps_readl(INTMR1);
63 intmr1 &= ~(1 << d->irq);
64 clps_writel(intmr1, INTMR1);
67 static void int1_ack(struct irq_data *d)
70 case IRQ_CSINT: clps_writel(0, COEOI); break;
71 case IRQ_TC1OI: clps_writel(0, TC1EOI); break;
72 case IRQ_TC2OI: clps_writel(0, TC2EOI); break;
73 case IRQ_RTCMI: clps_writel(0, RTCEOI); break;
74 case IRQ_TINT: clps_writel(0, TEOI); break;
75 case IRQ_UMSINT: clps_writel(0, UMSEOI); break;
79 static void int1_unmask(struct irq_data *d)
83 intmr1 = clps_readl(INTMR1);
84 intmr1 |= 1 << d->irq;
85 clps_writel(intmr1, INTMR1);
88 static struct irq_chip int1_chip = {
90 .irq_mask = int1_mask,
91 .irq_unmask = int1_unmask,
94 static void int2_mask(struct irq_data *d)
98 intmr2 = clps_readl(INTMR2);
99 intmr2 &= ~(1 << (d->irq - 16));
100 clps_writel(intmr2, INTMR2);
103 static void int2_ack(struct irq_data *d)
106 case IRQ_KBDINT: clps_writel(0, KBDEOI); break;
110 static void int2_unmask(struct irq_data *d)
114 intmr2 = clps_readl(INTMR2);
115 intmr2 |= 1 << (d->irq - 16);
116 clps_writel(intmr2, INTMR2);
119 static struct irq_chip int2_chip = {
121 .irq_mask = int2_mask,
122 .irq_unmask = int2_unmask,
125 void __init clps711x_init_irq(void)
129 for (i = 0; i < NR_IRQS; i++) {
130 if (INT1_IRQS & (1 << i)) {
131 irq_set_chip_and_handler(i, &int1_chip,
133 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
135 if (INT2_IRQS & (1 << i)) {
136 irq_set_chip_and_handler(i, &int2_chip,
138 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
145 clps_writel(0, INTMR1);
146 clps_writel(0, INTMR2);
149 * Clear down any pending interrupts
151 clps_writel(0, COEOI);
152 clps_writel(0, TC1EOI);
153 clps_writel(0, TC2EOI);
154 clps_writel(0, RTCEOI);
155 clps_writel(0, TEOI);
156 clps_writel(0, UMSEOI);
157 clps_writel(0, SYNCIO);
158 clps_writel(0, KBDEOI);
162 * gettimeoffset() returns time since last timer tick, in usecs.
164 * 'LATCH' is hwclock ticks (see CLOCK_TICK_RATE in timex.h) per jiffy.
165 * 'tick' is usecs per jiffy.
167 static unsigned long clps711x_gettimeoffset(void)
169 unsigned long hwticks;
170 hwticks = latch - (clps_readl(TC2D) & 0xffff);
171 return (hwticks * (tick_nsec / 1000)) / latch;
175 * IRQ handler for the timer
177 static irqreturn_t p720t_timer_interrupt(int irq, void *dev_id)
183 static struct irqaction clps711x_timer_irq = {
184 .name = "CLPS711x Timer Tick",
185 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
186 .handler = p720t_timer_interrupt,
189 static void add_fixed_clk(struct clk *clk, const char *name, int rate)
191 clk = clk_register_fixed_rate(NULL, name, NULL, CLK_IS_ROOT, rate);
192 clk_register_clkdev(clk, name, NULL);
195 static void __init clps711x_timer_init(void)
197 int osc, ext, pll, cpu, bus, timl, timh, uart, spi;
203 tmp = clps_readl(PLLR) >> 24;
205 pll = (osc * tmp) / 2;
207 pll = 73728000; /* Default value */
209 tmp = clps_readl(SYSFLG2);
210 if (tmp & SYSFLG2_CKMODE) {
225 if (tmp & SYSFLG2_CKMODE) {
226 tmp = clps_readl(SYSCON2);
227 if (tmp & SYSCON2_OSTB)
236 /* All clocks are fixed */
237 add_fixed_clk(clk_pll, "pll", pll);
238 add_fixed_clk(clk_bus, "bus", bus);
239 add_fixed_clk(clk_uart, "uart", uart);
240 add_fixed_clk(clk_timerl, "timer_lf", timl);
241 add_fixed_clk(clk_timerh, "timer_hf", timh);
242 add_fixed_clk(clk_tint, "tint", 64);
243 add_fixed_clk(clk_spi, "spi", spi);
245 pr_info("CPU frequency set at %i Hz.\n", cpu);
247 latch = (timh + HZ / 2) / HZ;
249 tmp = clps_readl(SYSCON1);
250 tmp |= SYSCON1_TC2S | SYSCON1_TC2M;
251 clps_writel(tmp, SYSCON1);
253 clps_writel(latch - 1, TC2D);
255 setup_irq(IRQ_TC2OI, &clps711x_timer_irq);
258 struct sys_timer clps711x_timer = {
259 .init = clps711x_timer_init,
260 .offset = clps711x_gettimeoffset,
263 void clps711x_restart(char mode, const char *cmd)
268 static void clps711x_idle(void)
270 clps_writel(1, HALT);
271 __asm__ __volatile__(
276 static int __init clps711x_idle_init(void)
278 arm_pm_idle = clps711x_idle;
282 arch_initcall(clps711x_idle_init);