2 * Critical Link MityOMAP-L138 SoM
4 * Copyright (C) 2010 Critical Link LLC - http://www.criticallink.com
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of
8 * any kind, whether express or implied.
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/console.h>
14 #include <linux/platform_device.h>
15 #include <linux/mtd/partitions.h>
16 #include <linux/regulator/machine.h>
17 #include <linux/i2c.h>
18 #include <linux/i2c/at24.h>
19 #include <linux/etherdevice.h>
20 #include <linux/spi/spi.h>
21 #include <linux/spi/flash.h>
23 #include <asm/mach-types.h>
24 #include <asm/mach/arch.h>
25 #include <mach/common.h>
26 #include <mach/cp_intc.h>
27 #include <mach/da8xx.h>
28 #include <mach/nand.h>
32 #define MITYOMAPL138_PHY_ID "0:03"
34 #define FACTORY_CONFIG_MAGIC 0x012C0138
35 #define FACTORY_CONFIG_VERSION 0x00010001
37 /* Data Held in On-Board I2C device */
38 struct factory_config {
48 static struct factory_config factory_config;
51 const char *part_no; /* part number string of interest */
52 int max_freq; /* khz */
55 static struct part_no_info mityomapl138_pn_info[] = {
86 #ifdef CONFIG_CPU_FREQ
87 static void mityomapl138_cpufreq_init(const char *partnum)
91 for (i = 0; partnum && i < ARRAY_SIZE(mityomapl138_pn_info); i++) {
93 * the part number has additional characters beyond what is
94 * stored in the table. This information is not needed for
95 * determining the speed grade, and would require several
96 * more table entries. Only check the first N characters
99 if (!strncmp(partnum, mityomapl138_pn_info[i].part_no,
100 strlen(mityomapl138_pn_info[i].part_no))) {
101 da850_max_speed = mityomapl138_pn_info[i].max_freq;
106 ret = da850_register_cpufreq("pll0_sysclk3");
108 pr_warning("cpufreq registration failed: %d\n", ret);
111 static void mityomapl138_cpufreq_init(const char *partnum) { }
114 static void read_factory_config(struct memory_accessor *a, void *context)
117 const char *partnum = NULL;
118 struct davinci_soc_info *soc_info = &davinci_soc_info;
120 ret = a->read(a, (char *)&factory_config, 0, sizeof(factory_config));
121 if (ret != sizeof(struct factory_config)) {
122 pr_warning("MityOMAPL138: Read Factory Config Failed: %d\n",
127 if (factory_config.magic != FACTORY_CONFIG_MAGIC) {
128 pr_warning("MityOMAPL138: Factory Config Magic Wrong (%X)\n",
129 factory_config.magic);
133 if (factory_config.version != FACTORY_CONFIG_VERSION) {
134 pr_warning("MityOMAPL138: Factory Config Version Wrong (%X)\n",
135 factory_config.version);
139 pr_info("MityOMAPL138: Found MAC = %pM\n", factory_config.mac);
140 if (is_valid_ether_addr(factory_config.mac))
141 memcpy(soc_info->emac_pdata->mac_addr,
142 factory_config.mac, ETH_ALEN);
144 pr_warning("MityOMAPL138: Invalid MAC found "
145 "in factory config block\n");
147 partnum = factory_config.partnum;
148 pr_info("MityOMAPL138: Part Number = %s\n", partnum);
151 /* default maximum speed is valid for all platforms */
152 mityomapl138_cpufreq_init(partnum);
155 static struct at24_platform_data mityomapl138_fd_chip = {
158 .flags = AT24_FLAG_READONLY | AT24_FLAG_IRUGO,
159 .setup = read_factory_config,
163 static struct davinci_i2c_platform_data mityomap_i2c_0_pdata = {
164 .bus_freq = 100, /* kHz */
165 .bus_delay = 0, /* usec */
168 /* TPS65023 voltage regulator support */
170 static struct regulator_consumer_supply tps65023_dcdc1_consumers[] = {
177 static struct regulator_consumer_supply tps65023_dcdc2_consumers[] = {
179 .supply = "usb0_vdda18",
182 .supply = "usb1_vdda18",
185 .supply = "ddr_dvdd18",
188 .supply = "sata_vddr",
193 static struct regulator_consumer_supply tps65023_dcdc3_consumers[] = {
195 .supply = "sata_vdd",
198 .supply = "usb_cvdd",
201 .supply = "pll0_vdda",
204 .supply = "pll1_vdda",
208 /* 1.8V Aux LDO, not used */
209 static struct regulator_consumer_supply tps65023_ldo1_consumers[] = {
211 .supply = "1.8v_aux",
215 /* FPGA VCC Aux (2.5 or 3.3) LDO */
216 static struct regulator_consumer_supply tps65023_ldo2_consumers[] = {
222 static struct regulator_init_data tps65023_regulator_data[] = {
228 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
229 REGULATOR_CHANGE_STATUS,
232 .num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc1_consumers),
233 .consumer_supplies = tps65023_dcdc1_consumers,
240 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
243 .num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc2_consumers),
244 .consumer_supplies = tps65023_dcdc2_consumers,
251 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
254 .num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc3_consumers),
255 .consumer_supplies = tps65023_dcdc3_consumers,
262 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
265 .num_consumer_supplies = ARRAY_SIZE(tps65023_ldo1_consumers),
266 .consumer_supplies = tps65023_ldo1_consumers,
273 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
274 REGULATOR_CHANGE_STATUS,
277 .num_consumer_supplies = ARRAY_SIZE(tps65023_ldo2_consumers),
278 .consumer_supplies = tps65023_ldo2_consumers,
282 static struct i2c_board_info __initdata mityomap_tps65023_info[] = {
284 I2C_BOARD_INFO("tps65023", 0x48),
285 .platform_data = &tps65023_regulator_data[0],
288 I2C_BOARD_INFO("24c02", 0x50),
289 .platform_data = &mityomapl138_fd_chip,
293 static int __init pmic_tps65023_init(void)
295 return i2c_register_board_info(1, mityomap_tps65023_info,
296 ARRAY_SIZE(mityomap_tps65023_info));
301 * SPI1_CS0: 8M Flash ST-M25P64-VME6G
303 static struct mtd_partition spi_flash_partitions[] = {
308 .mask_flags = MTD_WRITEABLE,
312 .offset = MTDPART_OFS_APPEND,
314 .mask_flags = MTD_WRITEABLE,
317 .name = "u-boot-env",
318 .offset = MTDPART_OFS_APPEND,
320 .mask_flags = MTD_WRITEABLE,
323 .name = "periph-config",
324 .offset = MTDPART_OFS_APPEND,
326 .mask_flags = MTD_WRITEABLE,
330 .offset = MTDPART_OFS_APPEND,
331 .size = SZ_256K + SZ_64K,
335 .offset = MTDPART_OFS_APPEND,
336 .size = SZ_2M + SZ_1M,
340 .offset = MTDPART_OFS_APPEND,
345 .offset = MTDPART_OFS_APPEND,
346 .size = MTDPART_SIZ_FULL,
350 static struct flash_platform_data mityomapl138_spi_flash_data = {
352 .parts = spi_flash_partitions,
353 .nr_parts = ARRAY_SIZE(spi_flash_partitions),
357 static struct davinci_spi_config spi_eprom_config = {
358 .io_type = SPI_IO_TYPE_DMA,
363 static struct spi_board_info mityomapl138_spi_flash_info[] = {
365 .modalias = "m25p80",
366 .platform_data = &mityomapl138_spi_flash_data,
367 .controller_data = &spi_eprom_config,
369 .max_speed_hz = 30000000,
376 * MityDSP-L138 includes a 256 MByte large-page NAND flash
379 static struct mtd_partition mityomapl138_nandflash_partition[] = {
384 .mask_flags = 0, /* MTD_WRITEABLE, */
388 .offset = MTDPART_OFS_APPEND,
389 .size = MTDPART_SIZ_FULL,
394 static struct davinci_nand_pdata mityomapl138_nandflash_data = {
395 .parts = mityomapl138_nandflash_partition,
396 .nr_parts = ARRAY_SIZE(mityomapl138_nandflash_partition),
397 .ecc_mode = NAND_ECC_HW,
398 .options = NAND_USE_FLASH_BBT | NAND_BUSWIDTH_16,
399 .ecc_bits = 1, /* 4 bit mode is not supported with 16 bit NAND */
402 static struct resource mityomapl138_nandflash_resource[] = {
404 .start = DA8XX_AEMIF_CS3_BASE,
405 .end = DA8XX_AEMIF_CS3_BASE + SZ_512K + 2 * SZ_1K - 1,
406 .flags = IORESOURCE_MEM,
409 .start = DA8XX_AEMIF_CTL_BASE,
410 .end = DA8XX_AEMIF_CTL_BASE + SZ_32K - 1,
411 .flags = IORESOURCE_MEM,
415 static struct platform_device mityomapl138_nandflash_device = {
416 .name = "davinci_nand",
419 .platform_data = &mityomapl138_nandflash_data,
421 .num_resources = ARRAY_SIZE(mityomapl138_nandflash_resource),
422 .resource = mityomapl138_nandflash_resource,
425 static struct platform_device *mityomapl138_devices[] __initdata = {
426 &mityomapl138_nandflash_device,
429 static void __init mityomapl138_setup_nand(void)
431 platform_add_devices(mityomapl138_devices,
432 ARRAY_SIZE(mityomapl138_devices));
435 static struct davinci_uart_config mityomapl138_uart_config __initdata = {
436 .enabled_uarts = 0x7,
439 static const short mityomap_mii_pins[] = {
440 DA850_MII_TXEN, DA850_MII_TXCLK, DA850_MII_COL, DA850_MII_TXD_3,
441 DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER,
442 DA850_MII_CRS, DA850_MII_RXCLK, DA850_MII_RXDV, DA850_MII_RXD_3,
443 DA850_MII_RXD_2, DA850_MII_RXD_1, DA850_MII_RXD_0, DA850_MDIO_CLK,
448 static const short mityomap_rmii_pins[] = {
449 DA850_RMII_TXD_0, DA850_RMII_TXD_1, DA850_RMII_TXEN,
450 DA850_RMII_CRS_DV, DA850_RMII_RXD_0, DA850_RMII_RXD_1,
451 DA850_RMII_RXER, DA850_RMII_MHZ_50_CLK, DA850_MDIO_CLK,
456 static void __init mityomapl138_config_emac(void)
458 void __iomem *cfg_chip3_base;
461 struct davinci_soc_info *soc_info = &davinci_soc_info;
463 soc_info->emac_pdata->rmii_en = 0; /* hardcoded for now */
465 cfg_chip3_base = DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG);
466 val = __raw_readl(cfg_chip3_base);
468 if (soc_info->emac_pdata->rmii_en) {
470 ret = davinci_cfg_reg_list(mityomap_rmii_pins);
471 pr_info("RMII PHY configured\n");
474 ret = davinci_cfg_reg_list(mityomap_mii_pins);
475 pr_info("MII PHY configured\n");
479 pr_warning("mii/rmii mux setup failed: %d\n", ret);
483 /* configure the CFGCHIP3 register for RMII or MII */
484 __raw_writel(val, cfg_chip3_base);
486 soc_info->emac_pdata->phy_id = MITYOMAPL138_PHY_ID;
488 ret = da8xx_register_emac();
490 pr_warning("emac registration failed: %d\n", ret);
493 static struct davinci_pm_config da850_pm_pdata = {
497 static struct platform_device da850_pm_device = {
498 .name = "pm-davinci",
500 .platform_data = &da850_pm_pdata,
505 static void __init mityomapl138_init(void)
509 /* for now, no special EDMA channels are reserved */
510 ret = da850_register_edma(NULL);
512 pr_warning("edma registration failed: %d\n", ret);
514 ret = da8xx_register_watchdog();
516 pr_warning("watchdog registration failed: %d\n", ret);
518 davinci_serial_init(&mityomapl138_uart_config);
520 ret = da8xx_register_i2c(0, &mityomap_i2c_0_pdata);
522 pr_warning("i2c0 registration failed: %d\n", ret);
524 ret = pmic_tps65023_init();
526 pr_warning("TPS65023 PMIC init failed: %d\n", ret);
528 mityomapl138_setup_nand();
530 ret = da8xx_register_spi(1, mityomapl138_spi_flash_info,
531 ARRAY_SIZE(mityomapl138_spi_flash_info));
533 pr_warning("spi 1 registration failed: %d\n", ret);
535 mityomapl138_config_emac();
537 ret = da8xx_register_rtc();
539 pr_warning("rtc setup failed: %d\n", ret);
541 ret = da8xx_register_cpuidle();
543 pr_warning("cpuidle registration failed: %d\n", ret);
545 ret = da850_register_pm(&da850_pm_device);
547 pr_warning("da850_evm_init: suspend registration failed: %d\n",
551 #ifdef CONFIG_SERIAL_8250_CONSOLE
552 static int __init mityomapl138_console_init(void)
554 if (!machine_is_mityomapl138())
557 return add_preferred_console("ttyS", 1, "115200");
559 console_initcall(mityomapl138_console_init);
562 static void __init mityomapl138_map_io(void)
567 MACHINE_START(MITYOMAPL138, "MityDSP-L138/MityARM-1808")
568 .boot_params = (DA8XX_DDR_BASE + 0x100),
569 .map_io = mityomapl138_map_io,
570 .init_irq = cp_intc_init,
571 .timer = &davinci_timer,
572 .init_machine = mityomapl138_init,