2 * Critical Link MityOMAP-L138 SoM
4 * Copyright (C) 2010 Critical Link LLC - http://www.criticallink.com
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of
8 * any kind, whether express or implied.
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/console.h>
14 #include <linux/platform_device.h>
15 #include <linux/mtd/partitions.h>
16 #include <linux/regulator/machine.h>
17 #include <linux/i2c.h>
18 #include <linux/platform_data/at24.h>
19 #include <linux/etherdevice.h>
20 #include <linux/spi/spi.h>
21 #include <linux/spi/flash.h>
24 #include <asm/mach-types.h>
25 #include <asm/mach/arch.h>
26 #include <mach/common.h>
27 #include <mach/cp_intc.h>
28 #include <mach/da8xx.h>
29 #include <linux/platform_data/mtd-davinci.h>
31 #include <linux/platform_data/spi-davinci.h>
33 #define MITYOMAPL138_PHY_ID ""
35 #define FACTORY_CONFIG_MAGIC 0x012C0138
36 #define FACTORY_CONFIG_VERSION 0x00010001
38 /* Data Held in On-Board I2C device */
39 struct factory_config {
49 static struct factory_config factory_config;
52 const char *part_no; /* part number string of interest */
53 int max_freq; /* khz */
56 static struct part_no_info mityomapl138_pn_info[] = {
87 #ifdef CONFIG_CPU_FREQ
88 static void mityomapl138_cpufreq_init(const char *partnum)
92 for (i = 0; partnum && i < ARRAY_SIZE(mityomapl138_pn_info); i++) {
94 * the part number has additional characters beyond what is
95 * stored in the table. This information is not needed for
96 * determining the speed grade, and would require several
97 * more table entries. Only check the first N characters
100 if (!strncmp(partnum, mityomapl138_pn_info[i].part_no,
101 strlen(mityomapl138_pn_info[i].part_no))) {
102 da850_max_speed = mityomapl138_pn_info[i].max_freq;
107 ret = da850_register_cpufreq("pll0_sysclk3");
109 pr_warning("cpufreq registration failed: %d\n", ret);
112 static void mityomapl138_cpufreq_init(const char *partnum) { }
115 static void read_factory_config(struct memory_accessor *a, void *context)
118 const char *partnum = NULL;
119 struct davinci_soc_info *soc_info = &davinci_soc_info;
121 ret = a->read(a, (char *)&factory_config, 0, sizeof(factory_config));
122 if (ret != sizeof(struct factory_config)) {
123 pr_warning("MityOMAPL138: Read Factory Config Failed: %d\n",
128 if (factory_config.magic != FACTORY_CONFIG_MAGIC) {
129 pr_warning("MityOMAPL138: Factory Config Magic Wrong (%X)\n",
130 factory_config.magic);
134 if (factory_config.version != FACTORY_CONFIG_VERSION) {
135 pr_warning("MityOMAPL138: Factory Config Version Wrong (%X)\n",
136 factory_config.version);
140 pr_info("MityOMAPL138: Found MAC = %pM\n", factory_config.mac);
141 if (is_valid_ether_addr(factory_config.mac))
142 memcpy(soc_info->emac_pdata->mac_addr,
143 factory_config.mac, ETH_ALEN);
145 pr_warning("MityOMAPL138: Invalid MAC found "
146 "in factory config block\n");
148 partnum = factory_config.partnum;
149 pr_info("MityOMAPL138: Part Number = %s\n", partnum);
152 /* default maximum speed is valid for all platforms */
153 mityomapl138_cpufreq_init(partnum);
156 static struct at24_platform_data mityomapl138_fd_chip = {
159 .flags = AT24_FLAG_READONLY | AT24_FLAG_IRUGO,
160 .setup = read_factory_config,
164 static struct davinci_i2c_platform_data mityomap_i2c_0_pdata = {
165 .bus_freq = 100, /* kHz */
166 .bus_delay = 0, /* usec */
169 /* TPS65023 voltage regulator support */
171 static struct regulator_consumer_supply tps65023_dcdc1_consumers[] = {
178 static struct regulator_consumer_supply tps65023_dcdc2_consumers[] = {
180 .supply = "usb0_vdda18",
183 .supply = "usb1_vdda18",
186 .supply = "ddr_dvdd18",
189 .supply = "sata_vddr",
194 static struct regulator_consumer_supply tps65023_dcdc3_consumers[] = {
196 .supply = "sata_vdd",
199 .supply = "usb_cvdd",
202 .supply = "pll0_vdda",
205 .supply = "pll1_vdda",
209 /* 1.8V Aux LDO, not used */
210 static struct regulator_consumer_supply tps65023_ldo1_consumers[] = {
212 .supply = "1.8v_aux",
216 /* FPGA VCC Aux (2.5 or 3.3) LDO */
217 static struct regulator_consumer_supply tps65023_ldo2_consumers[] = {
223 static struct regulator_init_data tps65023_regulator_data[] = {
229 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
230 REGULATOR_CHANGE_STATUS,
233 .num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc1_consumers),
234 .consumer_supplies = tps65023_dcdc1_consumers,
241 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
244 .num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc2_consumers),
245 .consumer_supplies = tps65023_dcdc2_consumers,
252 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
255 .num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc3_consumers),
256 .consumer_supplies = tps65023_dcdc3_consumers,
263 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
266 .num_consumer_supplies = ARRAY_SIZE(tps65023_ldo1_consumers),
267 .consumer_supplies = tps65023_ldo1_consumers,
274 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
275 REGULATOR_CHANGE_STATUS,
278 .num_consumer_supplies = ARRAY_SIZE(tps65023_ldo2_consumers),
279 .consumer_supplies = tps65023_ldo2_consumers,
283 static struct i2c_board_info __initdata mityomap_tps65023_info[] = {
285 I2C_BOARD_INFO("tps65023", 0x48),
286 .platform_data = &tps65023_regulator_data[0],
289 I2C_BOARD_INFO("24c02", 0x50),
290 .platform_data = &mityomapl138_fd_chip,
294 static int __init pmic_tps65023_init(void)
296 return i2c_register_board_info(1, mityomap_tps65023_info,
297 ARRAY_SIZE(mityomap_tps65023_info));
302 * SPI1_CS0: 8M Flash ST-M25P64-VME6G
304 static struct mtd_partition spi_flash_partitions[] = {
309 .mask_flags = MTD_WRITEABLE,
313 .offset = MTDPART_OFS_APPEND,
315 .mask_flags = MTD_WRITEABLE,
318 .name = "u-boot-env",
319 .offset = MTDPART_OFS_APPEND,
321 .mask_flags = MTD_WRITEABLE,
324 .name = "periph-config",
325 .offset = MTDPART_OFS_APPEND,
327 .mask_flags = MTD_WRITEABLE,
331 .offset = MTDPART_OFS_APPEND,
332 .size = SZ_256K + SZ_64K,
336 .offset = MTDPART_OFS_APPEND,
337 .size = SZ_2M + SZ_1M,
341 .offset = MTDPART_OFS_APPEND,
346 .offset = MTDPART_OFS_APPEND,
347 .size = MTDPART_SIZ_FULL,
351 static struct flash_platform_data mityomapl138_spi_flash_data = {
353 .parts = spi_flash_partitions,
354 .nr_parts = ARRAY_SIZE(spi_flash_partitions),
358 static struct davinci_spi_config spi_eprom_config = {
359 .io_type = SPI_IO_TYPE_DMA,
364 static struct spi_board_info mityomapl138_spi_flash_info[] = {
366 .modalias = "m25p80",
367 .platform_data = &mityomapl138_spi_flash_data,
368 .controller_data = &spi_eprom_config,
370 .max_speed_hz = 30000000,
377 * MityDSP-L138 includes a 256 MByte large-page NAND flash
380 static struct mtd_partition mityomapl138_nandflash_partition[] = {
385 .mask_flags = 0, /* MTD_WRITEABLE, */
389 .offset = MTDPART_OFS_APPEND,
390 .size = MTDPART_SIZ_FULL,
395 static struct davinci_nand_pdata mityomapl138_nandflash_data = {
396 .parts = mityomapl138_nandflash_partition,
397 .nr_parts = ARRAY_SIZE(mityomapl138_nandflash_partition),
398 .ecc_mode = NAND_ECC_HW,
399 .bbt_options = NAND_BBT_USE_FLASH,
400 .options = NAND_BUSWIDTH_16,
401 .ecc_bits = 1, /* 4 bit mode is not supported with 16 bit NAND */
404 static struct resource mityomapl138_nandflash_resource[] = {
406 .start = DA8XX_AEMIF_CS3_BASE,
407 .end = DA8XX_AEMIF_CS3_BASE + SZ_512K + 2 * SZ_1K - 1,
408 .flags = IORESOURCE_MEM,
411 .start = DA8XX_AEMIF_CTL_BASE,
412 .end = DA8XX_AEMIF_CTL_BASE + SZ_32K - 1,
413 .flags = IORESOURCE_MEM,
417 static struct platform_device mityomapl138_nandflash_device = {
418 .name = "davinci_nand",
421 .platform_data = &mityomapl138_nandflash_data,
423 .num_resources = ARRAY_SIZE(mityomapl138_nandflash_resource),
424 .resource = mityomapl138_nandflash_resource,
427 static struct platform_device *mityomapl138_devices[] __initdata = {
428 &mityomapl138_nandflash_device,
431 static void __init mityomapl138_setup_nand(void)
433 platform_add_devices(mityomapl138_devices,
434 ARRAY_SIZE(mityomapl138_devices));
437 static const short mityomap_mii_pins[] = {
438 DA850_MII_TXEN, DA850_MII_TXCLK, DA850_MII_COL, DA850_MII_TXD_3,
439 DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER,
440 DA850_MII_CRS, DA850_MII_RXCLK, DA850_MII_RXDV, DA850_MII_RXD_3,
441 DA850_MII_RXD_2, DA850_MII_RXD_1, DA850_MII_RXD_0, DA850_MDIO_CLK,
446 static const short mityomap_rmii_pins[] = {
447 DA850_RMII_TXD_0, DA850_RMII_TXD_1, DA850_RMII_TXEN,
448 DA850_RMII_CRS_DV, DA850_RMII_RXD_0, DA850_RMII_RXD_1,
449 DA850_RMII_RXER, DA850_RMII_MHZ_50_CLK, DA850_MDIO_CLK,
454 static void __init mityomapl138_config_emac(void)
456 void __iomem *cfg_chip3_base;
459 struct davinci_soc_info *soc_info = &davinci_soc_info;
461 soc_info->emac_pdata->rmii_en = 0; /* hardcoded for now */
463 cfg_chip3_base = DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG);
464 val = __raw_readl(cfg_chip3_base);
466 if (soc_info->emac_pdata->rmii_en) {
468 ret = davinci_cfg_reg_list(mityomap_rmii_pins);
469 pr_info("RMII PHY configured\n");
472 ret = davinci_cfg_reg_list(mityomap_mii_pins);
473 pr_info("MII PHY configured\n");
477 pr_warning("mii/rmii mux setup failed: %d\n", ret);
481 /* configure the CFGCHIP3 register for RMII or MII */
482 __raw_writel(val, cfg_chip3_base);
484 soc_info->emac_pdata->phy_id = MITYOMAPL138_PHY_ID;
486 ret = da8xx_register_emac();
488 pr_warning("emac registration failed: %d\n", ret);
491 static struct davinci_pm_config da850_pm_pdata = {
495 static struct platform_device da850_pm_device = {
496 .name = "pm-davinci",
498 .platform_data = &da850_pm_pdata,
503 static void __init mityomapl138_init(void)
507 /* for now, no special EDMA channels are reserved */
508 ret = da850_register_edma(NULL);
510 pr_warning("edma registration failed: %d\n", ret);
512 ret = da8xx_register_watchdog();
514 pr_warning("watchdog registration failed: %d\n", ret);
516 davinci_serial_init(da8xx_serial_device);
518 ret = da8xx_register_i2c(0, &mityomap_i2c_0_pdata);
520 pr_warning("i2c0 registration failed: %d\n", ret);
522 ret = pmic_tps65023_init();
524 pr_warning("TPS65023 PMIC init failed: %d\n", ret);
526 mityomapl138_setup_nand();
528 ret = spi_register_board_info(mityomapl138_spi_flash_info,
529 ARRAY_SIZE(mityomapl138_spi_flash_info));
531 pr_warn("spi info registration failed: %d\n", ret);
533 ret = da8xx_register_spi_bus(1,
534 ARRAY_SIZE(mityomapl138_spi_flash_info));
536 pr_warning("spi 1 registration failed: %d\n", ret);
538 mityomapl138_config_emac();
540 ret = da8xx_register_rtc();
542 pr_warning("rtc setup failed: %d\n", ret);
544 ret = da8xx_register_cpuidle();
546 pr_warning("cpuidle registration failed: %d\n", ret);
548 ret = da850_register_pm(&da850_pm_device);
550 pr_warning("da850_evm_init: suspend registration failed: %d\n",
554 #ifdef CONFIG_SERIAL_8250_CONSOLE
555 static int __init mityomapl138_console_init(void)
557 if (!machine_is_mityomapl138())
560 return add_preferred_console("ttyS", 1, "115200");
562 console_initcall(mityomapl138_console_init);
565 static void __init mityomapl138_map_io(void)
570 MACHINE_START(MITYOMAPL138, "MityDSP-L138/MityARM-1808")
571 .atag_offset = 0x100,
572 .map_io = mityomapl138_map_io,
573 .init_irq = cp_intc_init,
574 .init_time = davinci_timer_init,
575 .init_machine = mityomapl138_init,
576 .init_late = davinci_init_late,
577 .dma_zone_size = SZ_128M,
578 .restart = da8xx_restart,