2 * Clock and PLL control for DaVinci devices
4 * Copyright (C) 2006-2007 Texas Instruments.
5 * Copyright (C) 2008-2009 Deep Root Systems, LLC
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/init.h>
16 #include <linux/errno.h>
17 #include <linux/clk.h>
18 #include <linux/err.h>
19 #include <linux/mutex.h>
21 #include <linux/delay.h>
23 #include <mach/hardware.h>
25 #include <mach/clock.h>
27 #include <mach/cputype.h>
30 static LIST_HEAD(clocks);
31 static DEFINE_MUTEX(clocks_mutex);
32 static DEFINE_SPINLOCK(clockfw_lock);
34 static unsigned psc_domain(struct clk *clk)
36 return (clk->flags & PSC_DSP)
37 ? DAVINCI_GPSC_DSPDOMAIN
38 : DAVINCI_GPSC_ARMDOMAIN;
41 static void __clk_enable(struct clk *clk)
44 __clk_enable(clk->parent);
45 if (clk->usecount++ == 0 && (clk->flags & CLK_PSC))
46 davinci_psc_config(psc_domain(clk), clk->gpsc, clk->lpsc,
50 static void __clk_disable(struct clk *clk)
52 if (WARN_ON(clk->usecount == 0))
54 if (--clk->usecount == 0 && !(clk->flags & CLK_PLL) &&
55 (clk->flags & CLK_PSC))
56 davinci_psc_config(psc_domain(clk), clk->gpsc, clk->lpsc,
57 (clk->flags & PSC_SWRSTDISABLE) ?
58 PSC_STATE_SWRSTDISABLE : PSC_STATE_DISABLE);
60 __clk_disable(clk->parent);
63 int clk_enable(struct clk *clk)
67 if (clk == NULL || IS_ERR(clk))
70 spin_lock_irqsave(&clockfw_lock, flags);
72 spin_unlock_irqrestore(&clockfw_lock, flags);
76 EXPORT_SYMBOL(clk_enable);
78 void clk_disable(struct clk *clk)
82 if (clk == NULL || IS_ERR(clk))
85 spin_lock_irqsave(&clockfw_lock, flags);
87 spin_unlock_irqrestore(&clockfw_lock, flags);
89 EXPORT_SYMBOL(clk_disable);
91 unsigned long clk_get_rate(struct clk *clk)
93 if (clk == NULL || IS_ERR(clk))
98 EXPORT_SYMBOL(clk_get_rate);
100 long clk_round_rate(struct clk *clk, unsigned long rate)
102 if (clk == NULL || IS_ERR(clk))
106 return clk->round_rate(clk, rate);
110 EXPORT_SYMBOL(clk_round_rate);
112 /* Propagate rate to children */
113 static void propagate_rate(struct clk *root)
117 list_for_each_entry(clk, &root->children, childnode) {
119 clk->rate = clk->recalc(clk);
124 int clk_set_rate(struct clk *clk, unsigned long rate)
129 if (clk == NULL || IS_ERR(clk))
133 ret = clk->set_rate(clk, rate);
135 spin_lock_irqsave(&clockfw_lock, flags);
138 clk->rate = clk->recalc(clk);
141 spin_unlock_irqrestore(&clockfw_lock, flags);
145 EXPORT_SYMBOL(clk_set_rate);
147 int clk_set_parent(struct clk *clk, struct clk *parent)
151 if (clk == NULL || IS_ERR(clk))
154 /* Cannot change parent on enabled clock */
155 if (WARN_ON(clk->usecount))
158 mutex_lock(&clocks_mutex);
159 clk->parent = parent;
160 list_del_init(&clk->childnode);
161 list_add(&clk->childnode, &clk->parent->children);
162 mutex_unlock(&clocks_mutex);
164 spin_lock_irqsave(&clockfw_lock, flags);
166 clk->rate = clk->recalc(clk);
168 spin_unlock_irqrestore(&clockfw_lock, flags);
172 EXPORT_SYMBOL(clk_set_parent);
174 int clk_register(struct clk *clk)
176 if (clk == NULL || IS_ERR(clk))
179 if (WARN(clk->parent && !clk->parent->rate,
180 "CLK: %s parent %s has no rate!\n",
181 clk->name, clk->parent->name))
184 INIT_LIST_HEAD(&clk->children);
186 mutex_lock(&clocks_mutex);
187 list_add_tail(&clk->node, &clocks);
189 list_add_tail(&clk->childnode, &clk->parent->children);
190 mutex_unlock(&clocks_mutex);
192 /* If rate is already set, use it */
196 /* Else, see if there is a way to calculate it */
198 clk->rate = clk->recalc(clk);
200 /* Otherwise, default to parent rate */
201 else if (clk->parent)
202 clk->rate = clk->parent->rate;
206 EXPORT_SYMBOL(clk_register);
208 void clk_unregister(struct clk *clk)
210 if (clk == NULL || IS_ERR(clk))
213 mutex_lock(&clocks_mutex);
214 list_del(&clk->node);
215 list_del(&clk->childnode);
216 mutex_unlock(&clocks_mutex);
218 EXPORT_SYMBOL(clk_unregister);
220 #ifdef CONFIG_DAVINCI_RESET_CLOCKS
222 * Disable any unused clocks left on by the bootloader
224 static int __init clk_disable_unused(void)
228 spin_lock_irq(&clockfw_lock);
229 list_for_each_entry(ck, &clocks, node) {
230 if (ck->usecount > 0)
232 if (!(ck->flags & CLK_PSC))
235 /* ignore if in Disabled or SwRstDisable states */
236 if (!davinci_psc_is_clk_active(ck->gpsc, ck->lpsc))
239 pr_debug("Clocks: disable unused %s\n", ck->name);
241 davinci_psc_config(psc_domain(ck), ck->gpsc, ck->lpsc,
242 (ck->flags & PSC_SWRSTDISABLE) ?
243 PSC_STATE_SWRSTDISABLE : PSC_STATE_DISABLE);
245 spin_unlock_irq(&clockfw_lock);
249 late_initcall(clk_disable_unused);
252 static unsigned long clk_sysclk_recalc(struct clk *clk)
255 struct pll_data *pll;
256 unsigned long rate = clk->rate;
258 /* If this is the PLL base clock, no more calculations needed */
262 if (WARN_ON(!clk->parent))
265 rate = clk->parent->rate;
267 /* Otherwise, the parent must be a PLL */
268 if (WARN_ON(!clk->parent->pll_data))
271 pll = clk->parent->pll_data;
273 /* If pre-PLL, source clock is before the multiplier and divider(s) */
274 if (clk->flags & PRE_PLL)
275 rate = pll->input_rate;
280 v = __raw_readl(pll->base + clk->div_reg);
282 plldiv = (v & pll->div_ratio_mask) + 1;
290 int davinci_set_sysclk_rate(struct clk *clk, unsigned long rate)
293 struct pll_data *pll;
297 /* If this is the PLL base clock, wrong function to call */
301 /* There must be a parent... */
302 if (WARN_ON(!clk->parent))
305 /* ... the parent must be a PLL... */
306 if (WARN_ON(!clk->parent->pll_data))
309 /* ... and this clock must have a divider. */
310 if (WARN_ON(!clk->div_reg))
313 pll = clk->parent->pll_data;
315 input = clk->parent->rate;
317 /* If pre-PLL, source clock is before the multiplier and divider(s) */
318 if (clk->flags & PRE_PLL)
319 input = pll->input_rate;
323 * Can afford to provide an output little higher than requested
324 * only if maximum rate supported by hardware on this sysclk
328 ratio = DIV_ROUND_CLOSEST(input, rate);
329 if (input / ratio > clk->maxrate)
334 ratio = DIV_ROUND_UP(input, rate);
339 if (ratio > pll->div_ratio_mask)
343 v = __raw_readl(pll->base + PLLSTAT);
344 } while (v & PLLSTAT_GOSTAT);
346 v = __raw_readl(pll->base + clk->div_reg);
347 v &= ~pll->div_ratio_mask;
348 v |= ratio | PLLDIV_EN;
349 __raw_writel(v, pll->base + clk->div_reg);
351 v = __raw_readl(pll->base + PLLCMD);
353 __raw_writel(v, pll->base + PLLCMD);
356 v = __raw_readl(pll->base + PLLSTAT);
357 } while (v & PLLSTAT_GOSTAT);
361 EXPORT_SYMBOL(davinci_set_sysclk_rate);
363 static unsigned long clk_leafclk_recalc(struct clk *clk)
365 if (WARN_ON(!clk->parent))
368 return clk->parent->rate;
371 static unsigned long clk_pllclk_recalc(struct clk *clk)
373 u32 ctrl, mult = 1, prediv = 1, postdiv = 1;
375 struct pll_data *pll = clk->pll_data;
376 unsigned long rate = clk->rate;
378 ctrl = __raw_readl(pll->base + PLLCTL);
379 rate = pll->input_rate = clk->parent->rate;
381 if (ctrl & PLLCTL_PLLEN) {
383 mult = __raw_readl(pll->base + PLLM);
384 if (cpu_is_davinci_dm365())
385 mult = 2 * (mult & PLLM_PLLM_MASK);
387 mult = (mult & PLLM_PLLM_MASK) + 1;
391 if (pll->flags & PLL_HAS_PREDIV) {
392 prediv = __raw_readl(pll->base + PREDIV);
393 if (prediv & PLLDIV_EN)
394 prediv = (prediv & pll->div_ratio_mask) + 1;
399 /* pre-divider is fixed, but (some?) chips won't report that */
400 if (cpu_is_davinci_dm355() && pll->num == 1)
403 if (pll->flags & PLL_HAS_POSTDIV) {
404 postdiv = __raw_readl(pll->base + POSTDIV);
405 if (postdiv & PLLDIV_EN)
406 postdiv = (postdiv & pll->div_ratio_mask) + 1;
417 pr_debug("PLL%d: input = %lu MHz [ ",
418 pll->num, clk->parent->rate / 1000000);
422 pr_debug("/ %d ", prediv);
424 pr_debug("* %d ", mult);
426 pr_debug("/ %d ", postdiv);
427 pr_debug("] --> %lu MHz output.\n", rate / 1000000);
433 * davinci_set_pllrate - set the output rate of a given PLL.
435 * Note: Currently tested to work with OMAP-L138 only.
437 * @pll: pll whose rate needs to be changed.
438 * @prediv: The pre divider value. Passing 0 disables the pre-divider.
439 * @pllm: The multiplier value. Passing 0 leads to multiply-by-one.
440 * @postdiv: The post divider value. Passing 0 disables the post-divider.
442 int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv,
443 unsigned int mult, unsigned int postdiv)
446 unsigned int locktime;
449 if (pll->base == NULL)
453 * PLL lock time required per OMAP-L138 datasheet is
454 * (2000 * prediv)/sqrt(pllm) OSCIN cycles. We approximate sqrt(pllm)
455 * as 4 and OSCIN cycle as 25 MHz.
458 locktime = ((2000 * prediv) / 100);
459 prediv = (prediv - 1) | PLLDIV_EN;
461 locktime = PLL_LOCK_TIME;
464 postdiv = (postdiv - 1) | PLLDIV_EN;
468 /* Protect against simultaneous calls to PLL setting seqeunce */
469 spin_lock_irqsave(&clockfw_lock, flags);
471 ctrl = __raw_readl(pll->base + PLLCTL);
473 /* Switch the PLL to bypass mode */
474 ctrl &= ~(PLLCTL_PLLENSRC | PLLCTL_PLLEN);
475 __raw_writel(ctrl, pll->base + PLLCTL);
477 udelay(PLL_BYPASS_TIME);
479 /* Reset and enable PLL */
480 ctrl &= ~(PLLCTL_PLLRST | PLLCTL_PLLDIS);
481 __raw_writel(ctrl, pll->base + PLLCTL);
483 if (pll->flags & PLL_HAS_PREDIV)
484 __raw_writel(prediv, pll->base + PREDIV);
486 __raw_writel(mult, pll->base + PLLM);
488 if (pll->flags & PLL_HAS_POSTDIV)
489 __raw_writel(postdiv, pll->base + POSTDIV);
491 udelay(PLL_RESET_TIME);
493 /* Bring PLL out of reset */
494 ctrl |= PLLCTL_PLLRST;
495 __raw_writel(ctrl, pll->base + PLLCTL);
499 /* Remove PLL from bypass mode */
500 ctrl |= PLLCTL_PLLEN;
501 __raw_writel(ctrl, pll->base + PLLCTL);
503 spin_unlock_irqrestore(&clockfw_lock, flags);
507 EXPORT_SYMBOL(davinci_set_pllrate);
509 int __init davinci_clk_init(struct clk_lookup *clocks)
511 struct clk_lookup *c;
513 size_t num_clocks = 0;
515 for (c = clocks; c->clk; c++) {
520 /* Check if clock is a PLL */
522 clk->recalc = clk_pllclk_recalc;
524 /* Else, if it is a PLL-derived clock */
525 else if (clk->flags & CLK_PLL)
526 clk->recalc = clk_sysclk_recalc;
528 /* Otherwise, it is a leaf clock (PSC clock) */
529 else if (clk->parent)
530 clk->recalc = clk_leafclk_recalc;
534 struct pll_data *pll = clk->pll_data;
536 if (!pll->div_ratio_mask)
537 pll->div_ratio_mask = PLLDIV_RATIO_MASK;
539 if (pll->phys_base && !pll->base) {
540 pll->base = ioremap(pll->phys_base, SZ_4K);
546 clk->rate = clk->recalc(clk);
549 clk->flags |= CLK_PSC;
554 /* Turn on clocks that Linux doesn't otherwise manage */
555 if (clk->flags & ALWAYS_ENABLED)
559 clkdev_add_table(clocks, num_clocks);
564 #ifdef CONFIG_DEBUG_FS
566 #include <linux/debugfs.h>
567 #include <linux/seq_file.h>
569 #define CLKNAME_MAX 10 /* longest clock name */
574 dump_clock(struct seq_file *s, unsigned nest, struct clk *parent)
577 char buf[CLKNAME_MAX + NEST_DELTA * NEST_MAX];
581 if (parent->flags & CLK_PLL)
583 else if (parent->flags & CLK_PSC)
588 /* <nest spaces> name <pad to end> */
589 memset(buf, ' ', sizeof(buf) - 1);
590 buf[sizeof(buf) - 1] = 0;
591 i = strlen(parent->name);
592 memcpy(buf + nest, parent->name,
593 min(i, (unsigned)(sizeof(buf) - 1 - nest)));
595 seq_printf(s, "%s users=%2d %-3s %9ld Hz\n",
596 buf, parent->usecount, state, clk_get_rate(parent));
597 /* REVISIT show device associations too */
599 /* cost is now small, but not linear... */
600 list_for_each_entry(clk, &parent->children, childnode) {
601 dump_clock(s, nest + NEST_DELTA, clk);
605 static int davinci_ck_show(struct seq_file *m, void *v)
610 * Show clock tree; We trust nonzero usecounts equate to PSC enables...
612 mutex_lock(&clocks_mutex);
613 list_for_each_entry(clk, &clocks, node)
615 dump_clock(m, 0, clk);
616 mutex_unlock(&clocks_mutex);
621 static int davinci_ck_open(struct inode *inode, struct file *file)
623 return single_open(file, davinci_ck_show, NULL);
626 static const struct file_operations davinci_ck_operations = {
627 .open = davinci_ck_open,
630 .release = single_release,
633 static int __init davinci_clk_debugfs_init(void)
635 debugfs_create_file("davinci_clocks", S_IFREG | S_IRUGO, NULL, NULL,
636 &davinci_ck_operations);
640 device_initcall(davinci_clk_debugfs_init);
641 #endif /* CONFIG_DEBUG_FS */