2 * TI DA850/OMAP-L138 chip specific setup
4 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
6 * Derived from: arch/arm/mach-davinci/da830.c
7 * Original Copyrights follow:
9 * 2009 (c) MontaVista Software, Inc. This file is licensed under
10 * the terms of the GNU General Public License version 2. This program
11 * is licensed "as is" without any warranty of any kind, whether express
14 #include <linux/clkdev.h>
15 #include <linux/gpio.h>
16 #include <linux/init.h>
17 #include <linux/clk.h>
18 #include <linux/platform_device.h>
19 #include <linux/cpufreq.h>
20 #include <linux/regulator/consumer.h>
21 #include <linux/platform_data/gpio-davinci.h>
23 #include <asm/mach/map.h>
26 #include <mach/irqs.h>
27 #include <mach/cputype.h>
28 #include <mach/common.h>
29 #include <mach/time.h>
30 #include <mach/da8xx.h>
31 #include <mach/cpufreq.h>
37 #define DA850_PLL1_BASE 0x01e1a000
38 #define DA850_TIMER64P2_BASE 0x01f0c000
39 #define DA850_TIMER64P3_BASE 0x01f0d000
41 #define DA850_REF_FREQ 24000000
43 #define CFGCHIP3_ASYNC3_CLKSRC BIT(4)
44 #define CFGCHIP3_PLL1_MASTER_LOCK BIT(5)
45 #define CFGCHIP0_PLL_MASTER_LOCK BIT(4)
47 static int da850_set_armrate(struct clk *clk, unsigned long rate);
48 static int da850_round_armrate(struct clk *clk, unsigned long rate);
49 static int da850_set_pll0rate(struct clk *clk, unsigned long armrate);
51 static struct pll_data pll0_data = {
53 .phys_base = DA8XX_PLL0_BASE,
54 .flags = PLL_HAS_PREDIV | PLL_HAS_POSTDIV,
57 static struct clk ref_clk = {
59 .rate = DA850_REF_FREQ,
60 .set_rate = davinci_simple_set_rate,
63 static struct clk pll0_clk = {
66 .pll_data = &pll0_data,
68 .set_rate = da850_set_pll0rate,
71 static struct clk pll0_aux_clk = {
72 .name = "pll0_aux_clk",
74 .flags = CLK_PLL | PRE_PLL,
77 static struct clk pll0_sysclk1 = {
78 .name = "pll0_sysclk1",
84 static struct clk pll0_sysclk2 = {
85 .name = "pll0_sysclk2",
91 static struct clk pll0_sysclk3 = {
92 .name = "pll0_sysclk3",
96 .set_rate = davinci_set_sysclk_rate,
100 static struct clk pll0_sysclk4 = {
101 .name = "pll0_sysclk4",
107 static struct clk pll0_sysclk5 = {
108 .name = "pll0_sysclk5",
114 static struct clk pll0_sysclk6 = {
115 .name = "pll0_sysclk6",
121 static struct clk pll0_sysclk7 = {
122 .name = "pll0_sysclk7",
128 static struct pll_data pll1_data = {
130 .phys_base = DA850_PLL1_BASE,
131 .flags = PLL_HAS_POSTDIV,
134 static struct clk pll1_clk = {
137 .pll_data = &pll1_data,
141 static struct clk pll1_aux_clk = {
142 .name = "pll1_aux_clk",
144 .flags = CLK_PLL | PRE_PLL,
147 static struct clk pll1_sysclk2 = {
148 .name = "pll1_sysclk2",
154 static struct clk pll1_sysclk3 = {
155 .name = "pll1_sysclk3",
161 static int da850_async3_set_parent(struct clk *clk, struct clk *parent)
165 val = readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
167 if (parent == &pll0_sysclk2) {
168 val &= ~CFGCHIP3_ASYNC3_CLKSRC;
169 } else if (parent == &pll1_sysclk2) {
170 val |= CFGCHIP3_ASYNC3_CLKSRC;
172 pr_err("Bad parent on async3 clock mux\n");
176 writel(val, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
181 static struct clk async3_clk = {
183 .parent = &pll1_sysclk2,
184 .set_parent = da850_async3_set_parent,
187 static struct clk i2c0_clk = {
189 .parent = &pll0_aux_clk,
192 static struct clk timerp64_0_clk = {
194 .parent = &pll0_aux_clk,
197 static struct clk timerp64_1_clk = {
199 .parent = &pll0_aux_clk,
202 static struct clk arm_rom_clk = {
204 .parent = &pll0_sysclk2,
205 .lpsc = DA8XX_LPSC0_ARM_RAM_ROM,
206 .flags = ALWAYS_ENABLED,
209 static struct clk tpcc0_clk = {
211 .parent = &pll0_sysclk2,
212 .lpsc = DA8XX_LPSC0_TPCC,
213 .flags = ALWAYS_ENABLED | CLK_PSC,
216 static struct clk tptc0_clk = {
218 .parent = &pll0_sysclk2,
219 .lpsc = DA8XX_LPSC0_TPTC0,
220 .flags = ALWAYS_ENABLED,
223 static struct clk tptc1_clk = {
225 .parent = &pll0_sysclk2,
226 .lpsc = DA8XX_LPSC0_TPTC1,
227 .flags = ALWAYS_ENABLED,
230 static struct clk tpcc1_clk = {
232 .parent = &pll0_sysclk2,
233 .lpsc = DA850_LPSC1_TPCC1,
235 .flags = CLK_PSC | ALWAYS_ENABLED,
238 static struct clk tptc2_clk = {
240 .parent = &pll0_sysclk2,
241 .lpsc = DA850_LPSC1_TPTC2,
243 .flags = ALWAYS_ENABLED,
246 static struct clk pruss_clk = {
248 .parent = &pll0_sysclk2,
249 .lpsc = DA8XX_LPSC0_PRUSS,
252 static struct clk uart0_clk = {
254 .parent = &pll0_sysclk2,
255 .lpsc = DA8XX_LPSC0_UART0,
258 static struct clk uart1_clk = {
260 .parent = &async3_clk,
261 .lpsc = DA8XX_LPSC1_UART1,
265 static struct clk uart2_clk = {
267 .parent = &async3_clk,
268 .lpsc = DA8XX_LPSC1_UART2,
272 static struct clk aintc_clk = {
274 .parent = &pll0_sysclk4,
275 .lpsc = DA8XX_LPSC0_AINTC,
276 .flags = ALWAYS_ENABLED,
279 static struct clk gpio_clk = {
281 .parent = &pll0_sysclk4,
282 .lpsc = DA8XX_LPSC1_GPIO,
286 static struct clk i2c1_clk = {
288 .parent = &pll0_sysclk4,
289 .lpsc = DA8XX_LPSC1_I2C,
293 static struct clk emif3_clk = {
295 .parent = &pll0_sysclk5,
296 .lpsc = DA8XX_LPSC1_EMIF3C,
298 .flags = ALWAYS_ENABLED,
301 static struct clk arm_clk = {
303 .parent = &pll0_sysclk6,
304 .lpsc = DA8XX_LPSC0_ARM,
305 .flags = ALWAYS_ENABLED,
306 .set_rate = da850_set_armrate,
307 .round_rate = da850_round_armrate,
310 static struct clk rmii_clk = {
312 .parent = &pll0_sysclk7,
315 static struct clk emac_clk = {
317 .parent = &pll0_sysclk4,
318 .lpsc = DA8XX_LPSC1_CPGMAC,
322 static struct clk mcasp_clk = {
324 .parent = &async3_clk,
325 .lpsc = DA8XX_LPSC1_McASP0,
329 static struct clk mcbsp0_clk = {
331 .parent = &async3_clk,
332 .lpsc = DA850_LPSC1_McBSP0,
336 static struct clk mcbsp1_clk = {
338 .parent = &async3_clk,
339 .lpsc = DA850_LPSC1_McBSP1,
343 static struct clk lcdc_clk = {
345 .parent = &pll0_sysclk2,
346 .lpsc = DA8XX_LPSC1_LCDC,
350 static struct clk mmcsd0_clk = {
352 .parent = &pll0_sysclk2,
353 .lpsc = DA8XX_LPSC0_MMC_SD,
356 static struct clk mmcsd1_clk = {
358 .parent = &pll0_sysclk2,
359 .lpsc = DA850_LPSC1_MMC_SD1,
363 static struct clk aemif_clk = {
365 .parent = &pll0_sysclk3,
366 .lpsc = DA8XX_LPSC0_EMIF25,
367 .flags = ALWAYS_ENABLED,
370 static struct clk usb11_clk = {
372 .parent = &pll0_sysclk4,
373 .lpsc = DA8XX_LPSC1_USB11,
377 static struct clk usb20_clk = {
379 .parent = &pll0_sysclk2,
380 .lpsc = DA8XX_LPSC1_USB20,
384 static struct clk spi0_clk = {
386 .parent = &pll0_sysclk2,
387 .lpsc = DA8XX_LPSC0_SPI0,
390 static struct clk spi1_clk = {
392 .parent = &async3_clk,
393 .lpsc = DA8XX_LPSC1_SPI1,
397 static struct clk vpif_clk = {
399 .parent = &pll0_sysclk2,
400 .lpsc = DA850_LPSC1_VPIF,
404 static struct clk sata_clk = {
406 .parent = &pll0_sysclk2,
407 .lpsc = DA850_LPSC1_SATA,
412 static struct clk dsp_clk = {
414 .parent = &pll0_sysclk1,
415 .domain = DAVINCI_GPSC_DSPDOMAIN,
416 .lpsc = DA8XX_LPSC0_GEM,
417 .flags = PSC_LRST | PSC_FORCE,
420 static struct clk ehrpwm_clk = {
422 .parent = &async3_clk,
423 .lpsc = DA8XX_LPSC1_PWM,
427 #define DA8XX_EHRPWM_TBCLKSYNC BIT(12)
429 static void ehrpwm_tblck_enable(struct clk *clk)
433 val = readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP1_REG));
434 val |= DA8XX_EHRPWM_TBCLKSYNC;
435 writel(val, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP1_REG));
438 static void ehrpwm_tblck_disable(struct clk *clk)
442 val = readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP1_REG));
443 val &= ~DA8XX_EHRPWM_TBCLKSYNC;
444 writel(val, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP1_REG));
447 static struct clk ehrpwm_tbclk = {
448 .name = "ehrpwm_tbclk",
449 .parent = &ehrpwm_clk,
450 .clk_enable = ehrpwm_tblck_enable,
451 .clk_disable = ehrpwm_tblck_disable,
454 static struct clk ecap_clk = {
456 .parent = &async3_clk,
457 .lpsc = DA8XX_LPSC1_ECAP,
461 static struct clk_lookup da850_clks[] = {
462 CLK(NULL, "ref", &ref_clk),
463 CLK(NULL, "pll0", &pll0_clk),
464 CLK(NULL, "pll0_aux", &pll0_aux_clk),
465 CLK(NULL, "pll0_sysclk1", &pll0_sysclk1),
466 CLK(NULL, "pll0_sysclk2", &pll0_sysclk2),
467 CLK(NULL, "pll0_sysclk3", &pll0_sysclk3),
468 CLK(NULL, "pll0_sysclk4", &pll0_sysclk4),
469 CLK(NULL, "pll0_sysclk5", &pll0_sysclk5),
470 CLK(NULL, "pll0_sysclk6", &pll0_sysclk6),
471 CLK(NULL, "pll0_sysclk7", &pll0_sysclk7),
472 CLK(NULL, "pll1", &pll1_clk),
473 CLK(NULL, "pll1_aux", &pll1_aux_clk),
474 CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
475 CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
476 CLK(NULL, "async3", &async3_clk),
477 CLK("i2c_davinci.1", NULL, &i2c0_clk),
478 CLK(NULL, "timer0", &timerp64_0_clk),
479 CLK("davinci-wdt", NULL, &timerp64_1_clk),
480 CLK(NULL, "arm_rom", &arm_rom_clk),
481 CLK(NULL, "tpcc0", &tpcc0_clk),
482 CLK(NULL, "tptc0", &tptc0_clk),
483 CLK(NULL, "tptc1", &tptc1_clk),
484 CLK(NULL, "tpcc1", &tpcc1_clk),
485 CLK(NULL, "tptc2", &tptc2_clk),
486 CLK("pruss_uio", "pruss", &pruss_clk),
487 CLK("serial8250.0", NULL, &uart0_clk),
488 CLK("serial8250.1", NULL, &uart1_clk),
489 CLK("serial8250.2", NULL, &uart2_clk),
490 CLK(NULL, "aintc", &aintc_clk),
491 CLK(NULL, "gpio", &gpio_clk),
492 CLK("i2c_davinci.2", NULL, &i2c1_clk),
493 CLK(NULL, "emif3", &emif3_clk),
494 CLK(NULL, "arm", &arm_clk),
495 CLK(NULL, "rmii", &rmii_clk),
496 CLK("davinci_emac.1", NULL, &emac_clk),
497 CLK("davinci_mdio.0", "fck", &emac_clk),
498 CLK("davinci-mcasp.0", NULL, &mcasp_clk),
499 CLK("davinci-mcbsp.0", NULL, &mcbsp0_clk),
500 CLK("davinci-mcbsp.1", NULL, &mcbsp1_clk),
501 CLK("da8xx_lcdc.0", "fck", &lcdc_clk),
502 CLK("da830-mmc.0", NULL, &mmcsd0_clk),
503 CLK("da830-mmc.1", NULL, &mmcsd1_clk),
504 CLK("ti-aemif", NULL, &aemif_clk),
505 CLK(NULL, "aemif", &aemif_clk),
506 CLK("ohci", "usb11", &usb11_clk),
507 CLK("musb-da8xx", "usb20", &usb20_clk),
508 CLK("spi_davinci.0", NULL, &spi0_clk),
509 CLK("spi_davinci.1", NULL, &spi1_clk),
510 CLK("vpif", NULL, &vpif_clk),
511 CLK("ahci_da850", NULL, &sata_clk),
512 CLK("davinci-rproc.0", NULL, &dsp_clk),
513 CLK("ehrpwm", "fck", &ehrpwm_clk),
514 CLK("ehrpwm", "tbclk", &ehrpwm_tbclk),
515 CLK("ecap", "fck", &ecap_clk),
516 CLK(NULL, NULL, NULL),
520 * Device specific mux setup
522 * soc description mux mode mode mux dbg
523 * reg offset mask mode
525 static const struct mux_config da850_pins[] = {
526 #ifdef CONFIG_DAVINCI_MUX
528 MUX_CFG(DA850, NUART0_CTS, 3, 24, 15, 2, false)
529 MUX_CFG(DA850, NUART0_RTS, 3, 28, 15, 2, false)
530 MUX_CFG(DA850, UART0_RXD, 3, 16, 15, 2, false)
531 MUX_CFG(DA850, UART0_TXD, 3, 20, 15, 2, false)
533 MUX_CFG(DA850, UART1_RXD, 4, 24, 15, 2, false)
534 MUX_CFG(DA850, UART1_TXD, 4, 28, 15, 2, false)
536 MUX_CFG(DA850, UART2_RXD, 4, 16, 15, 2, false)
537 MUX_CFG(DA850, UART2_TXD, 4, 20, 15, 2, false)
539 MUX_CFG(DA850, I2C1_SCL, 4, 16, 15, 4, false)
540 MUX_CFG(DA850, I2C1_SDA, 4, 20, 15, 4, false)
542 MUX_CFG(DA850, I2C0_SDA, 4, 12, 15, 2, false)
543 MUX_CFG(DA850, I2C0_SCL, 4, 8, 15, 2, false)
545 MUX_CFG(DA850, MII_TXEN, 2, 4, 15, 8, false)
546 MUX_CFG(DA850, MII_TXCLK, 2, 8, 15, 8, false)
547 MUX_CFG(DA850, MII_COL, 2, 12, 15, 8, false)
548 MUX_CFG(DA850, MII_TXD_3, 2, 16, 15, 8, false)
549 MUX_CFG(DA850, MII_TXD_2, 2, 20, 15, 8, false)
550 MUX_CFG(DA850, MII_TXD_1, 2, 24, 15, 8, false)
551 MUX_CFG(DA850, MII_TXD_0, 2, 28, 15, 8, false)
552 MUX_CFG(DA850, MII_RXCLK, 3, 0, 15, 8, false)
553 MUX_CFG(DA850, MII_RXDV, 3, 4, 15, 8, false)
554 MUX_CFG(DA850, MII_RXER, 3, 8, 15, 8, false)
555 MUX_CFG(DA850, MII_CRS, 3, 12, 15, 8, false)
556 MUX_CFG(DA850, MII_RXD_3, 3, 16, 15, 8, false)
557 MUX_CFG(DA850, MII_RXD_2, 3, 20, 15, 8, false)
558 MUX_CFG(DA850, MII_RXD_1, 3, 24, 15, 8, false)
559 MUX_CFG(DA850, MII_RXD_0, 3, 28, 15, 8, false)
560 MUX_CFG(DA850, MDIO_CLK, 4, 0, 15, 8, false)
561 MUX_CFG(DA850, MDIO_D, 4, 4, 15, 8, false)
562 MUX_CFG(DA850, RMII_TXD_0, 14, 12, 15, 8, false)
563 MUX_CFG(DA850, RMII_TXD_1, 14, 8, 15, 8, false)
564 MUX_CFG(DA850, RMII_TXEN, 14, 16, 15, 8, false)
565 MUX_CFG(DA850, RMII_CRS_DV, 15, 4, 15, 8, false)
566 MUX_CFG(DA850, RMII_RXD_0, 14, 24, 15, 8, false)
567 MUX_CFG(DA850, RMII_RXD_1, 14, 20, 15, 8, false)
568 MUX_CFG(DA850, RMII_RXER, 14, 28, 15, 8, false)
569 MUX_CFG(DA850, RMII_MHZ_50_CLK, 15, 0, 15, 0, false)
571 MUX_CFG(DA850, ACLKR, 0, 0, 15, 1, false)
572 MUX_CFG(DA850, ACLKX, 0, 4, 15, 1, false)
573 MUX_CFG(DA850, AFSR, 0, 8, 15, 1, false)
574 MUX_CFG(DA850, AFSX, 0, 12, 15, 1, false)
575 MUX_CFG(DA850, AHCLKR, 0, 16, 15, 1, false)
576 MUX_CFG(DA850, AHCLKX, 0, 20, 15, 1, false)
577 MUX_CFG(DA850, AMUTE, 0, 24, 15, 1, false)
578 MUX_CFG(DA850, AXR_15, 1, 0, 15, 1, false)
579 MUX_CFG(DA850, AXR_14, 1, 4, 15, 1, false)
580 MUX_CFG(DA850, AXR_13, 1, 8, 15, 1, false)
581 MUX_CFG(DA850, AXR_12, 1, 12, 15, 1, false)
582 MUX_CFG(DA850, AXR_11, 1, 16, 15, 1, false)
583 MUX_CFG(DA850, AXR_10, 1, 20, 15, 1, false)
584 MUX_CFG(DA850, AXR_9, 1, 24, 15, 1, false)
585 MUX_CFG(DA850, AXR_8, 1, 28, 15, 1, false)
586 MUX_CFG(DA850, AXR_7, 2, 0, 15, 1, false)
587 MUX_CFG(DA850, AXR_6, 2, 4, 15, 1, false)
588 MUX_CFG(DA850, AXR_5, 2, 8, 15, 1, false)
589 MUX_CFG(DA850, AXR_4, 2, 12, 15, 1, false)
590 MUX_CFG(DA850, AXR_3, 2, 16, 15, 1, false)
591 MUX_CFG(DA850, AXR_2, 2, 20, 15, 1, false)
592 MUX_CFG(DA850, AXR_1, 2, 24, 15, 1, false)
593 MUX_CFG(DA850, AXR_0, 2, 28, 15, 1, false)
595 MUX_CFG(DA850, LCD_D_7, 16, 8, 15, 2, false)
596 MUX_CFG(DA850, LCD_D_6, 16, 12, 15, 2, false)
597 MUX_CFG(DA850, LCD_D_5, 16, 16, 15, 2, false)
598 MUX_CFG(DA850, LCD_D_4, 16, 20, 15, 2, false)
599 MUX_CFG(DA850, LCD_D_3, 16, 24, 15, 2, false)
600 MUX_CFG(DA850, LCD_D_2, 16, 28, 15, 2, false)
601 MUX_CFG(DA850, LCD_D_1, 17, 0, 15, 2, false)
602 MUX_CFG(DA850, LCD_D_0, 17, 4, 15, 2, false)
603 MUX_CFG(DA850, LCD_D_15, 17, 8, 15, 2, false)
604 MUX_CFG(DA850, LCD_D_14, 17, 12, 15, 2, false)
605 MUX_CFG(DA850, LCD_D_13, 17, 16, 15, 2, false)
606 MUX_CFG(DA850, LCD_D_12, 17, 20, 15, 2, false)
607 MUX_CFG(DA850, LCD_D_11, 17, 24, 15, 2, false)
608 MUX_CFG(DA850, LCD_D_10, 17, 28, 15, 2, false)
609 MUX_CFG(DA850, LCD_D_9, 18, 0, 15, 2, false)
610 MUX_CFG(DA850, LCD_D_8, 18, 4, 15, 2, false)
611 MUX_CFG(DA850, LCD_PCLK, 18, 24, 15, 2, false)
612 MUX_CFG(DA850, LCD_HSYNC, 19, 0, 15, 2, false)
613 MUX_CFG(DA850, LCD_VSYNC, 19, 4, 15, 2, false)
614 MUX_CFG(DA850, NLCD_AC_ENB_CS, 19, 24, 15, 2, false)
615 /* MMC/SD0 function */
616 MUX_CFG(DA850, MMCSD0_DAT_0, 10, 8, 15, 2, false)
617 MUX_CFG(DA850, MMCSD0_DAT_1, 10, 12, 15, 2, false)
618 MUX_CFG(DA850, MMCSD0_DAT_2, 10, 16, 15, 2, false)
619 MUX_CFG(DA850, MMCSD0_DAT_3, 10, 20, 15, 2, false)
620 MUX_CFG(DA850, MMCSD0_CLK, 10, 0, 15, 2, false)
621 MUX_CFG(DA850, MMCSD0_CMD, 10, 4, 15, 2, false)
622 /* MMC/SD1 function */
623 MUX_CFG(DA850, MMCSD1_DAT_0, 18, 8, 15, 2, false)
624 MUX_CFG(DA850, MMCSD1_DAT_1, 19, 16, 15, 2, false)
625 MUX_CFG(DA850, MMCSD1_DAT_2, 19, 12, 15, 2, false)
626 MUX_CFG(DA850, MMCSD1_DAT_3, 19, 8, 15, 2, false)
627 MUX_CFG(DA850, MMCSD1_CLK, 18, 12, 15, 2, false)
628 MUX_CFG(DA850, MMCSD1_CMD, 18, 16, 15, 2, false)
629 /* EMIF2.5/EMIFA function */
630 MUX_CFG(DA850, EMA_D_7, 9, 0, 15, 1, false)
631 MUX_CFG(DA850, EMA_D_6, 9, 4, 15, 1, false)
632 MUX_CFG(DA850, EMA_D_5, 9, 8, 15, 1, false)
633 MUX_CFG(DA850, EMA_D_4, 9, 12, 15, 1, false)
634 MUX_CFG(DA850, EMA_D_3, 9, 16, 15, 1, false)
635 MUX_CFG(DA850, EMA_D_2, 9, 20, 15, 1, false)
636 MUX_CFG(DA850, EMA_D_1, 9, 24, 15, 1, false)
637 MUX_CFG(DA850, EMA_D_0, 9, 28, 15, 1, false)
638 MUX_CFG(DA850, EMA_A_1, 12, 24, 15, 1, false)
639 MUX_CFG(DA850, EMA_A_2, 12, 20, 15, 1, false)
640 MUX_CFG(DA850, NEMA_CS_3, 7, 4, 15, 1, false)
641 MUX_CFG(DA850, NEMA_CS_4, 7, 8, 15, 1, false)
642 MUX_CFG(DA850, NEMA_WE, 7, 16, 15, 1, false)
643 MUX_CFG(DA850, NEMA_OE, 7, 20, 15, 1, false)
644 MUX_CFG(DA850, EMA_A_0, 12, 28, 15, 1, false)
645 MUX_CFG(DA850, EMA_A_3, 12, 16, 15, 1, false)
646 MUX_CFG(DA850, EMA_A_4, 12, 12, 15, 1, false)
647 MUX_CFG(DA850, EMA_A_5, 12, 8, 15, 1, false)
648 MUX_CFG(DA850, EMA_A_6, 12, 4, 15, 1, false)
649 MUX_CFG(DA850, EMA_A_7, 12, 0, 15, 1, false)
650 MUX_CFG(DA850, EMA_A_8, 11, 28, 15, 1, false)
651 MUX_CFG(DA850, EMA_A_9, 11, 24, 15, 1, false)
652 MUX_CFG(DA850, EMA_A_10, 11, 20, 15, 1, false)
653 MUX_CFG(DA850, EMA_A_11, 11, 16, 15, 1, false)
654 MUX_CFG(DA850, EMA_A_12, 11, 12, 15, 1, false)
655 MUX_CFG(DA850, EMA_A_13, 11, 8, 15, 1, false)
656 MUX_CFG(DA850, EMA_A_14, 11, 4, 15, 1, false)
657 MUX_CFG(DA850, EMA_A_15, 11, 0, 15, 1, false)
658 MUX_CFG(DA850, EMA_A_16, 10, 28, 15, 1, false)
659 MUX_CFG(DA850, EMA_A_17, 10, 24, 15, 1, false)
660 MUX_CFG(DA850, EMA_A_18, 10, 20, 15, 1, false)
661 MUX_CFG(DA850, EMA_A_19, 10, 16, 15, 1, false)
662 MUX_CFG(DA850, EMA_A_20, 10, 12, 15, 1, false)
663 MUX_CFG(DA850, EMA_A_21, 10, 8, 15, 1, false)
664 MUX_CFG(DA850, EMA_A_22, 10, 4, 15, 1, false)
665 MUX_CFG(DA850, EMA_A_23, 10, 0, 15, 1, false)
666 MUX_CFG(DA850, EMA_D_8, 8, 28, 15, 1, false)
667 MUX_CFG(DA850, EMA_D_9, 8, 24, 15, 1, false)
668 MUX_CFG(DA850, EMA_D_10, 8, 20, 15, 1, false)
669 MUX_CFG(DA850, EMA_D_11, 8, 16, 15, 1, false)
670 MUX_CFG(DA850, EMA_D_12, 8, 12, 15, 1, false)
671 MUX_CFG(DA850, EMA_D_13, 8, 8, 15, 1, false)
672 MUX_CFG(DA850, EMA_D_14, 8, 4, 15, 1, false)
673 MUX_CFG(DA850, EMA_D_15, 8, 0, 15, 1, false)
674 MUX_CFG(DA850, EMA_BA_1, 5, 24, 15, 1, false)
675 MUX_CFG(DA850, EMA_CLK, 6, 0, 15, 1, false)
676 MUX_CFG(DA850, EMA_WAIT_1, 6, 24, 15, 1, false)
677 MUX_CFG(DA850, NEMA_CS_2, 7, 0, 15, 1, false)
679 MUX_CFG(DA850, GPIO2_4, 6, 12, 15, 8, false)
680 MUX_CFG(DA850, GPIO2_6, 6, 4, 15, 8, false)
681 MUX_CFG(DA850, GPIO2_8, 5, 28, 15, 8, false)
682 MUX_CFG(DA850, GPIO2_15, 5, 0, 15, 8, false)
683 MUX_CFG(DA850, GPIO3_12, 7, 12, 15, 8, false)
684 MUX_CFG(DA850, GPIO3_13, 7, 8, 15, 8, false)
685 MUX_CFG(DA850, GPIO4_0, 10, 28, 15, 8, false)
686 MUX_CFG(DA850, GPIO4_1, 10, 24, 15, 8, false)
687 MUX_CFG(DA850, GPIO6_9, 13, 24, 15, 8, false)
688 MUX_CFG(DA850, GPIO6_10, 13, 20, 15, 8, false)
689 MUX_CFG(DA850, GPIO6_13, 13, 8, 15, 8, false)
690 MUX_CFG(DA850, RTC_ALARM, 0, 28, 15, 2, false)
692 MUX_CFG(DA850, VPIF_DIN0, 15, 4, 15, 1, false)
693 MUX_CFG(DA850, VPIF_DIN1, 15, 0, 15, 1, false)
694 MUX_CFG(DA850, VPIF_DIN2, 14, 28, 15, 1, false)
695 MUX_CFG(DA850, VPIF_DIN3, 14, 24, 15, 1, false)
696 MUX_CFG(DA850, VPIF_DIN4, 14, 20, 15, 1, false)
697 MUX_CFG(DA850, VPIF_DIN5, 14, 16, 15, 1, false)
698 MUX_CFG(DA850, VPIF_DIN6, 14, 12, 15, 1, false)
699 MUX_CFG(DA850, VPIF_DIN7, 14, 8, 15, 1, false)
700 MUX_CFG(DA850, VPIF_DIN8, 16, 4, 15, 1, false)
701 MUX_CFG(DA850, VPIF_DIN9, 16, 0, 15, 1, false)
702 MUX_CFG(DA850, VPIF_DIN10, 15, 28, 15, 1, false)
703 MUX_CFG(DA850, VPIF_DIN11, 15, 24, 15, 1, false)
704 MUX_CFG(DA850, VPIF_DIN12, 15, 20, 15, 1, false)
705 MUX_CFG(DA850, VPIF_DIN13, 15, 16, 15, 1, false)
706 MUX_CFG(DA850, VPIF_DIN14, 15, 12, 15, 1, false)
707 MUX_CFG(DA850, VPIF_DIN15, 15, 8, 15, 1, false)
708 MUX_CFG(DA850, VPIF_CLKIN0, 14, 0, 15, 1, false)
709 MUX_CFG(DA850, VPIF_CLKIN1, 14, 4, 15, 1, false)
710 MUX_CFG(DA850, VPIF_CLKIN2, 19, 8, 15, 1, false)
711 MUX_CFG(DA850, VPIF_CLKIN3, 19, 16, 15, 1, false)
713 MUX_CFG(DA850, VPIF_DOUT0, 17, 4, 15, 1, false)
714 MUX_CFG(DA850, VPIF_DOUT1, 17, 0, 15, 1, false)
715 MUX_CFG(DA850, VPIF_DOUT2, 16, 28, 15, 1, false)
716 MUX_CFG(DA850, VPIF_DOUT3, 16, 24, 15, 1, false)
717 MUX_CFG(DA850, VPIF_DOUT4, 16, 20, 15, 1, false)
718 MUX_CFG(DA850, VPIF_DOUT5, 16, 16, 15, 1, false)
719 MUX_CFG(DA850, VPIF_DOUT6, 16, 12, 15, 1, false)
720 MUX_CFG(DA850, VPIF_DOUT7, 16, 8, 15, 1, false)
721 MUX_CFG(DA850, VPIF_DOUT8, 18, 4, 15, 1, false)
722 MUX_CFG(DA850, VPIF_DOUT9, 18, 0, 15, 1, false)
723 MUX_CFG(DA850, VPIF_DOUT10, 17, 28, 15, 1, false)
724 MUX_CFG(DA850, VPIF_DOUT11, 17, 24, 15, 1, false)
725 MUX_CFG(DA850, VPIF_DOUT12, 17, 20, 15, 1, false)
726 MUX_CFG(DA850, VPIF_DOUT13, 17, 16, 15, 1, false)
727 MUX_CFG(DA850, VPIF_DOUT14, 17, 12, 15, 1, false)
728 MUX_CFG(DA850, VPIF_DOUT15, 17, 8, 15, 1, false)
729 MUX_CFG(DA850, VPIF_CLKO2, 19, 12, 15, 1, false)
730 MUX_CFG(DA850, VPIF_CLKO3, 19, 20, 15, 1, false)
734 const short da850_i2c0_pins[] __initconst = {
735 DA850_I2C0_SDA, DA850_I2C0_SCL,
739 const short da850_i2c1_pins[] __initconst = {
740 DA850_I2C1_SCL, DA850_I2C1_SDA,
744 const short da850_lcdcntl_pins[] __initconst = {
745 DA850_LCD_D_0, DA850_LCD_D_1, DA850_LCD_D_2, DA850_LCD_D_3,
746 DA850_LCD_D_4, DA850_LCD_D_5, DA850_LCD_D_6, DA850_LCD_D_7,
747 DA850_LCD_D_8, DA850_LCD_D_9, DA850_LCD_D_10, DA850_LCD_D_11,
748 DA850_LCD_D_12, DA850_LCD_D_13, DA850_LCD_D_14, DA850_LCD_D_15,
749 DA850_LCD_PCLK, DA850_LCD_HSYNC, DA850_LCD_VSYNC, DA850_NLCD_AC_ENB_CS,
753 const short da850_vpif_capture_pins[] __initconst = {
754 DA850_VPIF_DIN0, DA850_VPIF_DIN1, DA850_VPIF_DIN2, DA850_VPIF_DIN3,
755 DA850_VPIF_DIN4, DA850_VPIF_DIN5, DA850_VPIF_DIN6, DA850_VPIF_DIN7,
756 DA850_VPIF_DIN8, DA850_VPIF_DIN9, DA850_VPIF_DIN10, DA850_VPIF_DIN11,
757 DA850_VPIF_DIN12, DA850_VPIF_DIN13, DA850_VPIF_DIN14, DA850_VPIF_DIN15,
758 DA850_VPIF_CLKIN0, DA850_VPIF_CLKIN1, DA850_VPIF_CLKIN2,
763 const short da850_vpif_display_pins[] __initconst = {
764 DA850_VPIF_DOUT0, DA850_VPIF_DOUT1, DA850_VPIF_DOUT2, DA850_VPIF_DOUT3,
765 DA850_VPIF_DOUT4, DA850_VPIF_DOUT5, DA850_VPIF_DOUT6, DA850_VPIF_DOUT7,
766 DA850_VPIF_DOUT8, DA850_VPIF_DOUT9, DA850_VPIF_DOUT10,
767 DA850_VPIF_DOUT11, DA850_VPIF_DOUT12, DA850_VPIF_DOUT13,
768 DA850_VPIF_DOUT14, DA850_VPIF_DOUT15, DA850_VPIF_CLKO2,
773 /* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
774 static u8 da850_default_priorities[DA850_N_CP_INTC_IRQ] = {
775 [IRQ_DA8XX_COMMTX] = 7,
776 [IRQ_DA8XX_COMMRX] = 7,
777 [IRQ_DA8XX_NINT] = 7,
778 [IRQ_DA8XX_EVTOUT0] = 7,
779 [IRQ_DA8XX_EVTOUT1] = 7,
780 [IRQ_DA8XX_EVTOUT2] = 7,
781 [IRQ_DA8XX_EVTOUT3] = 7,
782 [IRQ_DA8XX_EVTOUT4] = 7,
783 [IRQ_DA8XX_EVTOUT5] = 7,
784 [IRQ_DA8XX_EVTOUT6] = 7,
785 [IRQ_DA8XX_EVTOUT7] = 7,
786 [IRQ_DA8XX_CCINT0] = 7,
787 [IRQ_DA8XX_CCERRINT] = 7,
788 [IRQ_DA8XX_TCERRINT0] = 7,
789 [IRQ_DA8XX_AEMIFINT] = 7,
790 [IRQ_DA8XX_I2CINT0] = 7,
791 [IRQ_DA8XX_MMCSDINT0] = 7,
792 [IRQ_DA8XX_MMCSDINT1] = 7,
793 [IRQ_DA8XX_ALLINT0] = 7,
795 [IRQ_DA8XX_SPINT0] = 7,
796 [IRQ_DA8XX_TINT12_0] = 7,
797 [IRQ_DA8XX_TINT34_0] = 7,
798 [IRQ_DA8XX_TINT12_1] = 7,
799 [IRQ_DA8XX_TINT34_1] = 7,
800 [IRQ_DA8XX_UARTINT0] = 7,
801 [IRQ_DA8XX_KEYMGRINT] = 7,
802 [IRQ_DA850_MPUADDRERR0] = 7,
803 [IRQ_DA8XX_CHIPINT0] = 7,
804 [IRQ_DA8XX_CHIPINT1] = 7,
805 [IRQ_DA8XX_CHIPINT2] = 7,
806 [IRQ_DA8XX_CHIPINT3] = 7,
807 [IRQ_DA8XX_TCERRINT1] = 7,
808 [IRQ_DA8XX_C0_RX_THRESH_PULSE] = 7,
809 [IRQ_DA8XX_C0_RX_PULSE] = 7,
810 [IRQ_DA8XX_C0_TX_PULSE] = 7,
811 [IRQ_DA8XX_C0_MISC_PULSE] = 7,
812 [IRQ_DA8XX_C1_RX_THRESH_PULSE] = 7,
813 [IRQ_DA8XX_C1_RX_PULSE] = 7,
814 [IRQ_DA8XX_C1_TX_PULSE] = 7,
815 [IRQ_DA8XX_C1_MISC_PULSE] = 7,
816 [IRQ_DA8XX_MEMERR] = 7,
817 [IRQ_DA8XX_GPIO0] = 7,
818 [IRQ_DA8XX_GPIO1] = 7,
819 [IRQ_DA8XX_GPIO2] = 7,
820 [IRQ_DA8XX_GPIO3] = 7,
821 [IRQ_DA8XX_GPIO4] = 7,
822 [IRQ_DA8XX_GPIO5] = 7,
823 [IRQ_DA8XX_GPIO6] = 7,
824 [IRQ_DA8XX_GPIO7] = 7,
825 [IRQ_DA8XX_GPIO8] = 7,
826 [IRQ_DA8XX_I2CINT1] = 7,
827 [IRQ_DA8XX_LCDINT] = 7,
828 [IRQ_DA8XX_UARTINT1] = 7,
829 [IRQ_DA8XX_MCASPINT] = 7,
830 [IRQ_DA8XX_ALLINT1] = 7,
831 [IRQ_DA8XX_SPINT1] = 7,
832 [IRQ_DA8XX_UHPI_INT1] = 7,
833 [IRQ_DA8XX_USB_INT] = 7,
834 [IRQ_DA8XX_IRQN] = 7,
835 [IRQ_DA8XX_RWAKEUP] = 7,
836 [IRQ_DA8XX_UARTINT2] = 7,
837 [IRQ_DA8XX_DFTSSINT] = 7,
838 [IRQ_DA8XX_EHRPWM0] = 7,
839 [IRQ_DA8XX_EHRPWM0TZ] = 7,
840 [IRQ_DA8XX_EHRPWM1] = 7,
841 [IRQ_DA8XX_EHRPWM1TZ] = 7,
842 [IRQ_DA850_SATAINT] = 7,
843 [IRQ_DA850_TINTALL_2] = 7,
844 [IRQ_DA8XX_ECAP0] = 7,
845 [IRQ_DA8XX_ECAP1] = 7,
846 [IRQ_DA8XX_ECAP2] = 7,
847 [IRQ_DA850_MMCSDINT0_1] = 7,
848 [IRQ_DA850_MMCSDINT1_1] = 7,
849 [IRQ_DA850_T12CMPINT0_2] = 7,
850 [IRQ_DA850_T12CMPINT1_2] = 7,
851 [IRQ_DA850_T12CMPINT2_2] = 7,
852 [IRQ_DA850_T12CMPINT3_2] = 7,
853 [IRQ_DA850_T12CMPINT4_2] = 7,
854 [IRQ_DA850_T12CMPINT5_2] = 7,
855 [IRQ_DA850_T12CMPINT6_2] = 7,
856 [IRQ_DA850_T12CMPINT7_2] = 7,
857 [IRQ_DA850_T12CMPINT0_3] = 7,
858 [IRQ_DA850_T12CMPINT1_3] = 7,
859 [IRQ_DA850_T12CMPINT2_3] = 7,
860 [IRQ_DA850_T12CMPINT3_3] = 7,
861 [IRQ_DA850_T12CMPINT4_3] = 7,
862 [IRQ_DA850_T12CMPINT5_3] = 7,
863 [IRQ_DA850_T12CMPINT6_3] = 7,
864 [IRQ_DA850_T12CMPINT7_3] = 7,
865 [IRQ_DA850_RPIINT] = 7,
866 [IRQ_DA850_VPIFINT] = 7,
867 [IRQ_DA850_CCINT1] = 7,
868 [IRQ_DA850_CCERRINT1] = 7,
869 [IRQ_DA850_TCERRINT2] = 7,
870 [IRQ_DA850_TINTALL_3] = 7,
871 [IRQ_DA850_MCBSP0RINT] = 7,
872 [IRQ_DA850_MCBSP0XINT] = 7,
873 [IRQ_DA850_MCBSP1RINT] = 7,
874 [IRQ_DA850_MCBSP1XINT] = 7,
875 [IRQ_DA8XX_ARMCLKSTOPREQ] = 7,
878 static struct map_desc da850_io_desc[] = {
881 .pfn = __phys_to_pfn(IO_PHYS),
886 .virtual = DA8XX_CP_INTC_VIRT,
887 .pfn = __phys_to_pfn(DA8XX_CP_INTC_BASE),
888 .length = DA8XX_CP_INTC_SIZE,
893 static u32 da850_psc_bases[] = { DA8XX_PSC0_BASE, DA8XX_PSC1_BASE };
895 /* Contents of JTAG ID register used to identify exact cpu type */
896 static struct davinci_id da850_ids[] = {
900 .manufacturer = 0x017, /* 0x02f >> 1 */
901 .cpu_id = DAVINCI_CPU_ID_DA850,
902 .name = "da850/omap-l138",
907 .manufacturer = 0x017, /* 0x02f >> 1 */
908 .cpu_id = DAVINCI_CPU_ID_DA850,
909 .name = "da850/omap-l138/am18x",
913 static struct davinci_timer_instance da850_timer_instance[4] = {
915 .base = DA8XX_TIMER64P0_BASE,
916 .bottom_irq = IRQ_DA8XX_TINT12_0,
917 .top_irq = IRQ_DA8XX_TINT34_0,
920 .base = DA8XX_TIMER64P1_BASE,
921 .bottom_irq = IRQ_DA8XX_TINT12_1,
922 .top_irq = IRQ_DA8XX_TINT34_1,
925 .base = DA850_TIMER64P2_BASE,
926 .bottom_irq = IRQ_DA850_TINT12_2,
927 .top_irq = IRQ_DA850_TINT34_2,
930 .base = DA850_TIMER64P3_BASE,
931 .bottom_irq = IRQ_DA850_TINT12_3,
932 .top_irq = IRQ_DA850_TINT34_3,
937 * T0_BOT: Timer 0, bottom : Used for clock_event
938 * T0_TOP: Timer 0, top : Used for clocksource
939 * T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer
941 static struct davinci_timer_info da850_timer_info = {
942 .timers = da850_timer_instance,
943 .clockevent_id = T0_BOT,
944 .clocksource_id = T0_TOP,
947 #ifdef CONFIG_CPU_FREQ
950 * According to the TRM, minimum PLLM results in maximum power savings.
951 * The OPP definitions below should keep the PLLM as low as possible.
953 * The output of the PLLM must be between 300 to 600 MHz.
956 unsigned int freq; /* in KHz */
959 unsigned int postdiv;
960 unsigned int cvdd_min; /* in uV */
961 unsigned int cvdd_max; /* in uV */
964 static const struct da850_opp da850_opp_456 = {
973 static const struct da850_opp da850_opp_408 = {
982 static const struct da850_opp da850_opp_372 = {
991 static const struct da850_opp da850_opp_300 = {
1000 static const struct da850_opp da850_opp_200 = {
1005 .cvdd_min = 1100000,
1006 .cvdd_max = 1160000,
1009 static const struct da850_opp da850_opp_96 = {
1014 .cvdd_min = 1000000,
1015 .cvdd_max = 1050000,
1020 .driver_data = (unsigned int) &da850_opp_##freq, \
1021 .frequency = freq * 1000, \
1024 static struct cpufreq_frequency_table da850_freq_table[] = {
1033 .frequency = CPUFREQ_TABLE_END,
1037 #ifdef CONFIG_REGULATOR
1038 static int da850_set_voltage(unsigned int index);
1039 static int da850_regulator_init(void);
1042 static struct davinci_cpufreq_config cpufreq_info = {
1043 .freq_table = da850_freq_table,
1044 #ifdef CONFIG_REGULATOR
1045 .init = da850_regulator_init,
1046 .set_voltage = da850_set_voltage,
1050 #ifdef CONFIG_REGULATOR
1051 static struct regulator *cvdd;
1053 static int da850_set_voltage(unsigned int index)
1055 struct da850_opp *opp;
1060 opp = (struct da850_opp *) cpufreq_info.freq_table[index].driver_data;
1062 return regulator_set_voltage(cvdd, opp->cvdd_min, opp->cvdd_max);
1065 static int da850_regulator_init(void)
1067 cvdd = regulator_get(NULL, "cvdd");
1068 if (WARN(IS_ERR(cvdd), "Unable to obtain voltage regulator for CVDD;"
1069 " voltage scaling unsupported\n")) {
1070 return PTR_ERR(cvdd);
1077 static struct platform_device da850_cpufreq_device = {
1078 .name = "cpufreq-davinci",
1080 .platform_data = &cpufreq_info,
1085 unsigned int da850_max_speed = 300000;
1087 int da850_register_cpufreq(char *async_clk)
1091 /* cpufreq driver can help keep an "async" clock constant */
1093 clk_add_alias("async", da850_cpufreq_device.name,
1095 for (i = 0; i < ARRAY_SIZE(da850_freq_table); i++) {
1096 if (da850_freq_table[i].frequency <= da850_max_speed) {
1097 cpufreq_info.freq_table = &da850_freq_table[i];
1102 return platform_device_register(&da850_cpufreq_device);
1105 static int da850_round_armrate(struct clk *clk, unsigned long rate)
1108 unsigned int best = (unsigned int) -1;
1109 struct cpufreq_frequency_table *table = cpufreq_info.freq_table;
1110 struct cpufreq_frequency_table *pos;
1112 rate /= 1000; /* convert to kHz */
1114 cpufreq_for_each_entry(pos, table) {
1115 diff = pos->frequency - rate;
1121 ret = pos->frequency;
1128 static int da850_set_armrate(struct clk *clk, unsigned long index)
1130 struct clk *pllclk = &pll0_clk;
1132 return clk_set_rate(pllclk, index);
1135 static int da850_set_pll0rate(struct clk *clk, unsigned long index)
1137 unsigned int prediv, mult, postdiv;
1138 struct da850_opp *opp;
1139 struct pll_data *pll = clk->pll_data;
1142 opp = (struct da850_opp *) cpufreq_info.freq_table[index].driver_data;
1143 prediv = opp->prediv;
1145 postdiv = opp->postdiv;
1147 ret = davinci_set_pllrate(pll, prediv, mult, postdiv);
1154 int __init da850_register_cpufreq(char *async_clk)
1159 static int da850_set_armrate(struct clk *clk, unsigned long rate)
1164 static int da850_set_pll0rate(struct clk *clk, unsigned long armrate)
1169 static int da850_round_armrate(struct clk *clk, unsigned long rate)
1175 /* VPIF resource, platform data */
1176 static u64 da850_vpif_dma_mask = DMA_BIT_MASK(32);
1178 static struct resource da850_vpif_resource[] = {
1180 .start = DA8XX_VPIF_BASE,
1181 .end = DA8XX_VPIF_BASE + 0xfff,
1182 .flags = IORESOURCE_MEM,
1186 static struct platform_device da850_vpif_dev = {
1190 .dma_mask = &da850_vpif_dma_mask,
1191 .coherent_dma_mask = DMA_BIT_MASK(32),
1193 .resource = da850_vpif_resource,
1194 .num_resources = ARRAY_SIZE(da850_vpif_resource),
1197 static struct resource da850_vpif_display_resource[] = {
1199 .start = IRQ_DA850_VPIFINT,
1200 .end = IRQ_DA850_VPIFINT,
1201 .flags = IORESOURCE_IRQ,
1205 static struct platform_device da850_vpif_display_dev = {
1206 .name = "vpif_display",
1209 .dma_mask = &da850_vpif_dma_mask,
1210 .coherent_dma_mask = DMA_BIT_MASK(32),
1212 .resource = da850_vpif_display_resource,
1213 .num_resources = ARRAY_SIZE(da850_vpif_display_resource),
1216 static struct resource da850_vpif_capture_resource[] = {
1218 .start = IRQ_DA850_VPIFINT,
1219 .end = IRQ_DA850_VPIFINT,
1220 .flags = IORESOURCE_IRQ,
1223 .start = IRQ_DA850_VPIFINT,
1224 .end = IRQ_DA850_VPIFINT,
1225 .flags = IORESOURCE_IRQ,
1229 static struct platform_device da850_vpif_capture_dev = {
1230 .name = "vpif_capture",
1233 .dma_mask = &da850_vpif_dma_mask,
1234 .coherent_dma_mask = DMA_BIT_MASK(32),
1236 .resource = da850_vpif_capture_resource,
1237 .num_resources = ARRAY_SIZE(da850_vpif_capture_resource),
1240 int __init da850_register_vpif(void)
1242 return platform_device_register(&da850_vpif_dev);
1245 int __init da850_register_vpif_display(struct vpif_display_config
1248 da850_vpif_display_dev.dev.platform_data = display_config;
1249 return platform_device_register(&da850_vpif_display_dev);
1252 int __init da850_register_vpif_capture(struct vpif_capture_config
1255 da850_vpif_capture_dev.dev.platform_data = capture_config;
1256 return platform_device_register(&da850_vpif_capture_dev);
1259 static struct davinci_gpio_platform_data da850_gpio_platform_data = {
1263 int __init da850_register_gpio(void)
1265 return da8xx_register_gpio(&da850_gpio_platform_data);
1268 static struct davinci_soc_info davinci_soc_info_da850 = {
1269 .io_desc = da850_io_desc,
1270 .io_desc_num = ARRAY_SIZE(da850_io_desc),
1271 .jtag_id_reg = DA8XX_SYSCFG0_BASE + DA8XX_JTAG_ID_REG,
1273 .ids_num = ARRAY_SIZE(da850_ids),
1274 .cpu_clks = da850_clks,
1275 .psc_bases = da850_psc_bases,
1276 .psc_bases_num = ARRAY_SIZE(da850_psc_bases),
1277 .pinmux_base = DA8XX_SYSCFG0_BASE + 0x120,
1278 .pinmux_pins = da850_pins,
1279 .pinmux_pins_num = ARRAY_SIZE(da850_pins),
1280 .intc_base = DA8XX_CP_INTC_BASE,
1281 .intc_type = DAVINCI_INTC_TYPE_CP_INTC,
1282 .intc_irq_prios = da850_default_priorities,
1283 .intc_irq_num = DA850_N_CP_INTC_IRQ,
1284 .timer_info = &da850_timer_info,
1285 .emac_pdata = &da8xx_emac_pdata,
1286 .sram_dma = DA8XX_SHARED_RAM_BASE,
1287 .sram_len = SZ_128K,
1290 void __init da850_init(void)
1294 davinci_common_init(&davinci_soc_info_da850);
1296 da8xx_syscfg0_base = ioremap(DA8XX_SYSCFG0_BASE, SZ_4K);
1297 if (WARN(!da8xx_syscfg0_base, "Unable to map syscfg0 module"))
1300 da8xx_syscfg1_base = ioremap(DA8XX_SYSCFG1_BASE, SZ_4K);
1301 if (WARN(!da8xx_syscfg1_base, "Unable to map syscfg1 module"))
1304 /* Unlock writing to PLL0 registers */
1305 v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP0_REG));
1306 v &= ~CFGCHIP0_PLL_MASTER_LOCK;
1307 __raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP0_REG));
1309 /* Unlock writing to PLL1 registers */
1310 v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
1311 v &= ~CFGCHIP3_PLL1_MASTER_LOCK;
1312 __raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
1314 davinci_clk_init(davinci_soc_info_da850.cpu_clks);