2 * DA8XX/OMAP L1XX platform device data
4 * Copyright (c) 2007-2009, MontaVista Software, Inc. <source@mvista.com>
5 * Derived from code that was:
6 * Copyright (C) 2006 Komal Shah <komal_shah802003@yahoo.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 #include <linux/init.h>
14 #include <linux/platform_device.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/serial_8250.h>
18 #include <mach/cputype.h>
19 #include <mach/common.h>
20 #include <mach/time.h>
21 #include <mach/da8xx.h>
22 #include <mach/cpuidle.h>
26 #define DA8XX_TPCC_BASE 0x01c00000
27 #define DA850_TPCC1_BASE 0x01e30000
28 #define DA8XX_TPTC0_BASE 0x01c08000
29 #define DA8XX_TPTC1_BASE 0x01c08400
30 #define DA850_TPTC2_BASE 0x01e38000
31 #define DA8XX_WDOG_BASE 0x01c21000 /* DA8XX_TIMER64P1_BASE */
32 #define DA8XX_I2C0_BASE 0x01c22000
33 #define DA8XX_RTC_BASE 0x01C23000
34 #define DA8XX_EMAC_CPPI_PORT_BASE 0x01e20000
35 #define DA8XX_EMAC_CPGMACSS_BASE 0x01e22000
36 #define DA8XX_EMAC_CPGMAC_BASE 0x01e23000
37 #define DA8XX_EMAC_MDIO_BASE 0x01e24000
38 #define DA8XX_GPIO_BASE 0x01e26000
39 #define DA8XX_I2C1_BASE 0x01e28000
41 #define DA8XX_EMAC_CTRL_REG_OFFSET 0x3000
42 #define DA8XX_EMAC_MOD_REG_OFFSET 0x2000
43 #define DA8XX_EMAC_RAM_OFFSET 0x0000
44 #define DA8XX_MDIO_REG_OFFSET 0x4000
45 #define DA8XX_EMAC_CTRL_RAM_SIZE SZ_8K
47 void __iomem *da8xx_syscfg0_base;
48 void __iomem *da8xx_syscfg1_base;
50 static struct plat_serial8250_port da8xx_serial_pdata[] = {
52 .mapbase = DA8XX_UART0_BASE,
53 .irq = IRQ_DA8XX_UARTINT0,
54 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
60 .mapbase = DA8XX_UART1_BASE,
61 .irq = IRQ_DA8XX_UARTINT1,
62 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
68 .mapbase = DA8XX_UART2_BASE,
69 .irq = IRQ_DA8XX_UARTINT2,
70 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
80 struct platform_device da8xx_serial_device = {
82 .id = PLAT8250_DEV_PLATFORM,
84 .platform_data = da8xx_serial_pdata,
88 static const s8 da8xx_queue_tc_mapping[][2] = {
89 /* {event queue no, TC no} */
95 static const s8 da8xx_queue_priority_mapping[][2] = {
96 /* {event queue no, Priority} */
102 static const s8 da850_queue_tc_mapping[][2] = {
103 /* {event queue no, TC no} */
108 static const s8 da850_queue_priority_mapping[][2] = {
109 /* {event queue no, Priority} */
114 static struct edma_soc_info da830_edma_info[] = {
121 .queue_tc_mapping = da8xx_queue_tc_mapping,
122 .queue_priority_mapping = da8xx_queue_priority_mapping,
126 static struct edma_soc_info da850_edma_info[] = {
133 .queue_tc_mapping = da8xx_queue_tc_mapping,
134 .queue_priority_mapping = da8xx_queue_priority_mapping,
142 .queue_tc_mapping = da850_queue_tc_mapping,
143 .queue_priority_mapping = da850_queue_priority_mapping,
147 static struct resource da830_edma_resources[] = {
150 .start = DA8XX_TPCC_BASE,
151 .end = DA8XX_TPCC_BASE + SZ_32K - 1,
152 .flags = IORESOURCE_MEM,
156 .start = DA8XX_TPTC0_BASE,
157 .end = DA8XX_TPTC0_BASE + SZ_1K - 1,
158 .flags = IORESOURCE_MEM,
162 .start = DA8XX_TPTC1_BASE,
163 .end = DA8XX_TPTC1_BASE + SZ_1K - 1,
164 .flags = IORESOURCE_MEM,
168 .start = IRQ_DA8XX_CCINT0,
169 .flags = IORESOURCE_IRQ,
173 .start = IRQ_DA8XX_CCERRINT,
174 .flags = IORESOURCE_IRQ,
178 static struct resource da850_edma_resources[] = {
181 .start = DA8XX_TPCC_BASE,
182 .end = DA8XX_TPCC_BASE + SZ_32K - 1,
183 .flags = IORESOURCE_MEM,
187 .start = DA8XX_TPTC0_BASE,
188 .end = DA8XX_TPTC0_BASE + SZ_1K - 1,
189 .flags = IORESOURCE_MEM,
193 .start = DA8XX_TPTC1_BASE,
194 .end = DA8XX_TPTC1_BASE + SZ_1K - 1,
195 .flags = IORESOURCE_MEM,
199 .start = DA850_TPCC1_BASE,
200 .end = DA850_TPCC1_BASE + SZ_32K - 1,
201 .flags = IORESOURCE_MEM,
205 .start = DA850_TPTC2_BASE,
206 .end = DA850_TPTC2_BASE + SZ_1K - 1,
207 .flags = IORESOURCE_MEM,
211 .start = IRQ_DA8XX_CCINT0,
212 .flags = IORESOURCE_IRQ,
216 .start = IRQ_DA8XX_CCERRINT,
217 .flags = IORESOURCE_IRQ,
221 .start = IRQ_DA850_CCINT1,
222 .flags = IORESOURCE_IRQ,
226 .start = IRQ_DA850_CCERRINT1,
227 .flags = IORESOURCE_IRQ,
231 static struct platform_device da830_edma_device = {
235 .platform_data = da830_edma_info,
237 .num_resources = ARRAY_SIZE(da830_edma_resources),
238 .resource = da830_edma_resources,
241 static struct platform_device da850_edma_device = {
245 .platform_data = da850_edma_info,
247 .num_resources = ARRAY_SIZE(da850_edma_resources),
248 .resource = da850_edma_resources,
251 int __init da8xx_register_edma(void)
253 struct platform_device *pdev;
255 if (cpu_is_davinci_da830())
256 pdev = &da830_edma_device;
257 else if (cpu_is_davinci_da850())
258 pdev = &da850_edma_device;
262 return platform_device_register(pdev);
265 static struct resource da8xx_i2c_resources0[] = {
267 .start = DA8XX_I2C0_BASE,
268 .end = DA8XX_I2C0_BASE + SZ_4K - 1,
269 .flags = IORESOURCE_MEM,
272 .start = IRQ_DA8XX_I2CINT0,
273 .end = IRQ_DA8XX_I2CINT0,
274 .flags = IORESOURCE_IRQ,
278 static struct platform_device da8xx_i2c_device0 = {
279 .name = "i2c_davinci",
281 .num_resources = ARRAY_SIZE(da8xx_i2c_resources0),
282 .resource = da8xx_i2c_resources0,
285 static struct resource da8xx_i2c_resources1[] = {
287 .start = DA8XX_I2C1_BASE,
288 .end = DA8XX_I2C1_BASE + SZ_4K - 1,
289 .flags = IORESOURCE_MEM,
292 .start = IRQ_DA8XX_I2CINT1,
293 .end = IRQ_DA8XX_I2CINT1,
294 .flags = IORESOURCE_IRQ,
298 static struct platform_device da8xx_i2c_device1 = {
299 .name = "i2c_davinci",
301 .num_resources = ARRAY_SIZE(da8xx_i2c_resources1),
302 .resource = da8xx_i2c_resources1,
305 int __init da8xx_register_i2c(int instance,
306 struct davinci_i2c_platform_data *pdata)
308 struct platform_device *pdev;
311 pdev = &da8xx_i2c_device0;
312 else if (instance == 1)
313 pdev = &da8xx_i2c_device1;
317 pdev->dev.platform_data = pdata;
318 return platform_device_register(pdev);
321 static struct resource da8xx_watchdog_resources[] = {
323 .start = DA8XX_WDOG_BASE,
324 .end = DA8XX_WDOG_BASE + SZ_4K - 1,
325 .flags = IORESOURCE_MEM,
329 struct platform_device davinci_wdt_device = {
332 .num_resources = ARRAY_SIZE(da8xx_watchdog_resources),
333 .resource = da8xx_watchdog_resources,
336 int __init da8xx_register_watchdog(void)
338 return platform_device_register(&davinci_wdt_device);
341 static struct resource da8xx_emac_resources[] = {
343 .start = DA8XX_EMAC_CPPI_PORT_BASE,
344 .end = DA8XX_EMAC_CPPI_PORT_BASE + 0x5000 - 1,
345 .flags = IORESOURCE_MEM,
348 .start = IRQ_DA8XX_C0_RX_THRESH_PULSE,
349 .end = IRQ_DA8XX_C0_RX_THRESH_PULSE,
350 .flags = IORESOURCE_IRQ,
353 .start = IRQ_DA8XX_C0_RX_PULSE,
354 .end = IRQ_DA8XX_C0_RX_PULSE,
355 .flags = IORESOURCE_IRQ,
358 .start = IRQ_DA8XX_C0_TX_PULSE,
359 .end = IRQ_DA8XX_C0_TX_PULSE,
360 .flags = IORESOURCE_IRQ,
363 .start = IRQ_DA8XX_C0_MISC_PULSE,
364 .end = IRQ_DA8XX_C0_MISC_PULSE,
365 .flags = IORESOURCE_IRQ,
369 struct emac_platform_data da8xx_emac_pdata = {
370 .ctrl_reg_offset = DA8XX_EMAC_CTRL_REG_OFFSET,
371 .ctrl_mod_reg_offset = DA8XX_EMAC_MOD_REG_OFFSET,
372 .ctrl_ram_offset = DA8XX_EMAC_RAM_OFFSET,
373 .mdio_reg_offset = DA8XX_MDIO_REG_OFFSET,
374 .ctrl_ram_size = DA8XX_EMAC_CTRL_RAM_SIZE,
375 .version = EMAC_VERSION_2,
378 static struct platform_device da8xx_emac_device = {
379 .name = "davinci_emac",
382 .platform_data = &da8xx_emac_pdata,
384 .num_resources = ARRAY_SIZE(da8xx_emac_resources),
385 .resource = da8xx_emac_resources,
388 int __init da8xx_register_emac(void)
390 return platform_device_register(&da8xx_emac_device);
393 static struct resource da830_mcasp1_resources[] = {
396 .start = DAVINCI_DA830_MCASP1_REG_BASE,
397 .end = DAVINCI_DA830_MCASP1_REG_BASE + (SZ_1K * 12) - 1,
398 .flags = IORESOURCE_MEM,
402 .start = DAVINCI_DA830_DMA_MCASP1_AXEVT,
403 .end = DAVINCI_DA830_DMA_MCASP1_AXEVT,
404 .flags = IORESOURCE_DMA,
408 .start = DAVINCI_DA830_DMA_MCASP1_AREVT,
409 .end = DAVINCI_DA830_DMA_MCASP1_AREVT,
410 .flags = IORESOURCE_DMA,
414 static struct platform_device da830_mcasp1_device = {
415 .name = "davinci-mcasp",
417 .num_resources = ARRAY_SIZE(da830_mcasp1_resources),
418 .resource = da830_mcasp1_resources,
421 static struct resource da850_mcasp_resources[] = {
424 .start = DAVINCI_DA8XX_MCASP0_REG_BASE,
425 .end = DAVINCI_DA8XX_MCASP0_REG_BASE + (SZ_1K * 12) - 1,
426 .flags = IORESOURCE_MEM,
430 .start = DAVINCI_DA8XX_DMA_MCASP0_AXEVT,
431 .end = DAVINCI_DA8XX_DMA_MCASP0_AXEVT,
432 .flags = IORESOURCE_DMA,
436 .start = DAVINCI_DA8XX_DMA_MCASP0_AREVT,
437 .end = DAVINCI_DA8XX_DMA_MCASP0_AREVT,
438 .flags = IORESOURCE_DMA,
442 static struct platform_device da850_mcasp_device = {
443 .name = "davinci-mcasp",
445 .num_resources = ARRAY_SIZE(da850_mcasp_resources),
446 .resource = da850_mcasp_resources,
449 void __init da8xx_register_mcasp(int id, struct snd_platform_data *pdata)
451 /* DA830/OMAP-L137 has 3 instances of McASP */
452 if (cpu_is_davinci_da830() && id == 1) {
453 da830_mcasp1_device.dev.platform_data = pdata;
454 platform_device_register(&da830_mcasp1_device);
455 } else if (cpu_is_davinci_da850()) {
456 da850_mcasp_device.dev.platform_data = pdata;
457 platform_device_register(&da850_mcasp_device);
461 static const struct display_panel disp_panel = {
468 static struct lcd_ctrl_config lcd_cfg = {
478 .invert_line_clock = 1,
479 .invert_frm_clock = 1,
485 struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata = {
486 .manu_name = "sharp",
487 .controller_data = &lcd_cfg,
488 .type = "Sharp_LCD035Q3DG01",
491 struct da8xx_lcdc_platform_data sharp_lk043t1dg01_pdata = {
492 .manu_name = "sharp",
493 .controller_data = &lcd_cfg,
494 .type = "Sharp_LK043T1DG01",
497 static struct resource da8xx_lcdc_resources[] = {
498 [0] = { /* registers */
499 .start = DA8XX_LCD_CNTRL_BASE,
500 .end = DA8XX_LCD_CNTRL_BASE + SZ_4K - 1,
501 .flags = IORESOURCE_MEM,
503 [1] = { /* interrupt */
504 .start = IRQ_DA8XX_LCDINT,
505 .end = IRQ_DA8XX_LCDINT,
506 .flags = IORESOURCE_IRQ,
510 static struct platform_device da8xx_lcdc_device = {
511 .name = "da8xx_lcdc",
513 .num_resources = ARRAY_SIZE(da8xx_lcdc_resources),
514 .resource = da8xx_lcdc_resources,
517 int __init da8xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata)
519 da8xx_lcdc_device.dev.platform_data = pdata;
520 return platform_device_register(&da8xx_lcdc_device);
523 static struct resource da8xx_mmcsd0_resources[] = {
525 .start = DA8XX_MMCSD0_BASE,
526 .end = DA8XX_MMCSD0_BASE + SZ_4K - 1,
527 .flags = IORESOURCE_MEM,
530 .start = IRQ_DA8XX_MMCSDINT0,
531 .end = IRQ_DA8XX_MMCSDINT0,
532 .flags = IORESOURCE_IRQ,
535 .start = EDMA_CTLR_CHAN(0, 16),
536 .end = EDMA_CTLR_CHAN(0, 16),
537 .flags = IORESOURCE_DMA,
540 .start = EDMA_CTLR_CHAN(0, 17),
541 .end = EDMA_CTLR_CHAN(0, 17),
542 .flags = IORESOURCE_DMA,
546 static struct platform_device da8xx_mmcsd0_device = {
547 .name = "davinci_mmc",
549 .num_resources = ARRAY_SIZE(da8xx_mmcsd0_resources),
550 .resource = da8xx_mmcsd0_resources,
553 int __init da8xx_register_mmcsd0(struct davinci_mmc_config *config)
555 da8xx_mmcsd0_device.dev.platform_data = config;
556 return platform_device_register(&da8xx_mmcsd0_device);
559 static struct resource da8xx_rtc_resources[] = {
561 .start = DA8XX_RTC_BASE,
562 .end = DA8XX_RTC_BASE + SZ_4K - 1,
563 .flags = IORESOURCE_MEM,
566 .start = IRQ_DA8XX_RTC,
567 .end = IRQ_DA8XX_RTC,
568 .flags = IORESOURCE_IRQ,
571 .start = IRQ_DA8XX_RTC,
572 .end = IRQ_DA8XX_RTC,
573 .flags = IORESOURCE_IRQ,
577 static struct platform_device da8xx_rtc_device = {
580 .num_resources = ARRAY_SIZE(da8xx_rtc_resources),
581 .resource = da8xx_rtc_resources,
584 int da8xx_register_rtc(void)
588 /* Unlock the rtc's registers */
589 __raw_writel(0x83e70b13, IO_ADDRESS(DA8XX_RTC_BASE + 0x6c));
590 __raw_writel(0x95a4f1e0, IO_ADDRESS(DA8XX_RTC_BASE + 0x70));
592 ret = platform_device_register(&da8xx_rtc_device);
594 /* Atleast on DA850, RTC is a wakeup source */
595 device_init_wakeup(&da8xx_rtc_device.dev, true);
600 static void __iomem *da8xx_ddr2_ctlr_base;
601 void __iomem * __init da8xx_get_mem_ctlr(void)
603 if (da8xx_ddr2_ctlr_base)
604 return da8xx_ddr2_ctlr_base;
606 da8xx_ddr2_ctlr_base = ioremap(DA8XX_DDR2_CTL_BASE, SZ_32K);
607 if (!da8xx_ddr2_ctlr_base)
608 pr_warning("%s: Unable to map DDR2 controller", __func__);
610 return da8xx_ddr2_ctlr_base;
613 static struct resource da8xx_cpuidle_resources[] = {
615 .start = DA8XX_DDR2_CTL_BASE,
616 .end = DA8XX_DDR2_CTL_BASE + SZ_32K - 1,
617 .flags = IORESOURCE_MEM,
621 /* DA8XX devices support DDR2 power down */
622 static struct davinci_cpuidle_config da8xx_cpuidle_pdata = {
627 static struct platform_device da8xx_cpuidle_device = {
628 .name = "cpuidle-davinci",
629 .num_resources = ARRAY_SIZE(da8xx_cpuidle_resources),
630 .resource = da8xx_cpuidle_resources,
632 .platform_data = &da8xx_cpuidle_pdata,
636 int __init da8xx_register_cpuidle(void)
638 da8xx_cpuidle_pdata.ddr2_ctlr_base = da8xx_get_mem_ctlr();
640 return platform_device_register(&da8xx_cpuidle_device);