2 * TI DaVinci DM355 chip specific setup
4 * Author: Kevin Hilman, Deep Root Systems, LLC
6 * 2007 (c) Deep Root Systems, LLC. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/clk.h>
14 #include <linux/platform_device.h>
15 #include <linux/dma-mapping.h>
17 #include <linux/spi/spi.h>
19 #include <asm/mach/map.h>
21 #include <mach/dm355.h>
22 #include <mach/clock.h>
23 #include <mach/cputype.h>
24 #include <mach/edma.h>
27 #include <mach/irqs.h>
28 #include <mach/common.h>
34 * Device specific clocks
36 #define DM355_REF_FREQ 24000000 /* 24 or 36 MHz */
38 static struct pll_data pll1_data = {
40 .phys_base = DAVINCI_PLL1_BASE,
41 .flags = PLL_HAS_PREDIV | PLL_HAS_POSTDIV,
44 static struct pll_data pll2_data = {
46 .phys_base = DAVINCI_PLL2_BASE,
47 .flags = PLL_HAS_PREDIV,
50 static struct clk ref_clk = {
52 /* FIXME -- crystal rate is board-specific */
53 .rate = DM355_REF_FREQ,
56 static struct clk pll1_clk = {
60 .pll_data = &pll1_data,
63 static struct clk pll1_aux_clk = {
64 .name = "pll1_aux_clk",
66 .flags = CLK_PLL | PRE_PLL,
69 static struct clk pll1_sysclk1 = {
70 .name = "pll1_sysclk1",
76 static struct clk pll1_sysclk2 = {
77 .name = "pll1_sysclk2",
83 static struct clk pll1_sysclk3 = {
84 .name = "pll1_sysclk3",
90 static struct clk pll1_sysclk4 = {
91 .name = "pll1_sysclk4",
97 static struct clk pll1_sysclkbp = {
98 .name = "pll1_sysclkbp",
100 .flags = CLK_PLL | PRE_PLL,
104 static struct clk vpss_dac_clk = {
106 .parent = &pll1_sysclk3,
107 .lpsc = DM355_LPSC_VPSS_DAC,
110 static struct clk vpss_master_clk = {
111 .name = "vpss_master",
112 .parent = &pll1_sysclk4,
113 .lpsc = DAVINCI_LPSC_VPSSMSTR,
117 static struct clk vpss_slave_clk = {
118 .name = "vpss_slave",
119 .parent = &pll1_sysclk4,
120 .lpsc = DAVINCI_LPSC_VPSSSLV,
124 static struct clk clkout1_clk = {
126 .parent = &pll1_aux_clk,
127 /* NOTE: clkout1 can be externally gated by muxing GPIO-18 */
130 static struct clk clkout2_clk = {
132 .parent = &pll1_sysclkbp,
135 static struct clk pll2_clk = {
139 .pll_data = &pll2_data,
142 static struct clk pll2_sysclk1 = {
143 .name = "pll2_sysclk1",
149 static struct clk pll2_sysclkbp = {
150 .name = "pll2_sysclkbp",
152 .flags = CLK_PLL | PRE_PLL,
156 static struct clk clkout3_clk = {
158 .parent = &pll2_sysclkbp,
159 /* NOTE: clkout3 can be externally gated by muxing GPIO-16 */
162 static struct clk arm_clk = {
164 .parent = &pll1_sysclk1,
165 .lpsc = DAVINCI_LPSC_ARM,
166 .flags = ALWAYS_ENABLED,
170 * NOT LISTED below, and not touched by Linux
171 * - in SyncReset state by default
172 * .lpsc = DAVINCI_LPSC_TPCC,
173 * .lpsc = DAVINCI_LPSC_TPTC0,
174 * .lpsc = DAVINCI_LPSC_TPTC1,
175 * .lpsc = DAVINCI_LPSC_DDR_EMIF, .parent = &sysclk2_clk,
176 * .lpsc = DAVINCI_LPSC_MEMSTICK,
177 * - in Enabled state by default
178 * .lpsc = DAVINCI_LPSC_SYSTEM_SUBSYS,
179 * .lpsc = DAVINCI_LPSC_SCR2, // "bus"
180 * .lpsc = DAVINCI_LPSC_SCR3, // "bus"
181 * .lpsc = DAVINCI_LPSC_SCR4, // "bus"
182 * .lpsc = DAVINCI_LPSC_CROSSBAR, // "emulation"
183 * .lpsc = DAVINCI_LPSC_CFG27, // "test"
184 * .lpsc = DAVINCI_LPSC_CFG3, // "test"
185 * .lpsc = DAVINCI_LPSC_CFG5, // "test"
188 static struct clk mjcp_clk = {
190 .parent = &pll1_sysclk1,
191 .lpsc = DAVINCI_LPSC_IMCOP,
194 static struct clk uart0_clk = {
196 .parent = &pll1_aux_clk,
197 .lpsc = DAVINCI_LPSC_UART0,
200 static struct clk uart1_clk = {
202 .parent = &pll1_aux_clk,
203 .lpsc = DAVINCI_LPSC_UART1,
206 static struct clk uart2_clk = {
208 .parent = &pll1_sysclk2,
209 .lpsc = DAVINCI_LPSC_UART2,
212 static struct clk i2c_clk = {
214 .parent = &pll1_aux_clk,
215 .lpsc = DAVINCI_LPSC_I2C,
218 static struct clk asp0_clk = {
220 .parent = &pll1_sysclk2,
221 .lpsc = DAVINCI_LPSC_McBSP,
224 static struct clk asp1_clk = {
226 .parent = &pll1_sysclk2,
227 .lpsc = DM355_LPSC_McBSP1,
230 static struct clk mmcsd0_clk = {
232 .parent = &pll1_sysclk2,
233 .lpsc = DAVINCI_LPSC_MMC_SD,
236 static struct clk mmcsd1_clk = {
238 .parent = &pll1_sysclk2,
239 .lpsc = DM355_LPSC_MMC_SD1,
242 static struct clk spi0_clk = {
244 .parent = &pll1_sysclk2,
245 .lpsc = DAVINCI_LPSC_SPI,
248 static struct clk spi1_clk = {
250 .parent = &pll1_sysclk2,
251 .lpsc = DM355_LPSC_SPI1,
254 static struct clk spi2_clk = {
256 .parent = &pll1_sysclk2,
257 .lpsc = DM355_LPSC_SPI2,
260 static struct clk gpio_clk = {
262 .parent = &pll1_sysclk2,
263 .lpsc = DAVINCI_LPSC_GPIO,
266 static struct clk aemif_clk = {
268 .parent = &pll1_sysclk2,
269 .lpsc = DAVINCI_LPSC_AEMIF,
272 static struct clk pwm0_clk = {
274 .parent = &pll1_aux_clk,
275 .lpsc = DAVINCI_LPSC_PWM0,
278 static struct clk pwm1_clk = {
280 .parent = &pll1_aux_clk,
281 .lpsc = DAVINCI_LPSC_PWM1,
284 static struct clk pwm2_clk = {
286 .parent = &pll1_aux_clk,
287 .lpsc = DAVINCI_LPSC_PWM2,
290 static struct clk pwm3_clk = {
292 .parent = &pll1_aux_clk,
293 .lpsc = DM355_LPSC_PWM3,
296 static struct clk timer0_clk = {
298 .parent = &pll1_aux_clk,
299 .lpsc = DAVINCI_LPSC_TIMER0,
302 static struct clk timer1_clk = {
304 .parent = &pll1_aux_clk,
305 .lpsc = DAVINCI_LPSC_TIMER1,
308 static struct clk timer2_clk = {
310 .parent = &pll1_aux_clk,
311 .lpsc = DAVINCI_LPSC_TIMER2,
312 .usecount = 1, /* REVISIT: why cant' this be disabled? */
315 static struct clk timer3_clk = {
317 .parent = &pll1_aux_clk,
318 .lpsc = DM355_LPSC_TIMER3,
321 static struct clk rto_clk = {
323 .parent = &pll1_aux_clk,
324 .lpsc = DM355_LPSC_RTO,
327 static struct clk usb_clk = {
329 .parent = &pll1_sysclk2,
330 .lpsc = DAVINCI_LPSC_USB,
333 static struct davinci_clk dm355_clks[] = {
334 CLK(NULL, "ref", &ref_clk),
335 CLK(NULL, "pll1", &pll1_clk),
336 CLK(NULL, "pll1_sysclk1", &pll1_sysclk1),
337 CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
338 CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
339 CLK(NULL, "pll1_sysclk4", &pll1_sysclk4),
340 CLK(NULL, "pll1_aux", &pll1_aux_clk),
341 CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp),
342 CLK(NULL, "vpss_dac", &vpss_dac_clk),
343 CLK(NULL, "vpss_master", &vpss_master_clk),
344 CLK(NULL, "vpss_slave", &vpss_slave_clk),
345 CLK(NULL, "clkout1", &clkout1_clk),
346 CLK(NULL, "clkout2", &clkout2_clk),
347 CLK(NULL, "pll2", &pll2_clk),
348 CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
349 CLK(NULL, "pll2_sysclkbp", &pll2_sysclkbp),
350 CLK(NULL, "clkout3", &clkout3_clk),
351 CLK(NULL, "arm", &arm_clk),
352 CLK(NULL, "mjcp", &mjcp_clk),
353 CLK(NULL, "uart0", &uart0_clk),
354 CLK(NULL, "uart1", &uart1_clk),
355 CLK(NULL, "uart2", &uart2_clk),
356 CLK("i2c_davinci.1", NULL, &i2c_clk),
357 CLK("soc-audio.0", NULL, &asp0_clk),
358 CLK("soc-audio.1", NULL, &asp1_clk),
359 CLK("davinci_mmc.0", NULL, &mmcsd0_clk),
360 CLK("davinci_mmc.1", NULL, &mmcsd1_clk),
361 CLK(NULL, "spi0", &spi0_clk),
362 CLK(NULL, "spi1", &spi1_clk),
363 CLK(NULL, "spi2", &spi2_clk),
364 CLK(NULL, "gpio", &gpio_clk),
365 CLK(NULL, "aemif", &aemif_clk),
366 CLK(NULL, "pwm0", &pwm0_clk),
367 CLK(NULL, "pwm1", &pwm1_clk),
368 CLK(NULL, "pwm2", &pwm2_clk),
369 CLK(NULL, "pwm3", &pwm3_clk),
370 CLK(NULL, "timer0", &timer0_clk),
371 CLK(NULL, "timer1", &timer1_clk),
372 CLK("watchdog", NULL, &timer2_clk),
373 CLK(NULL, "timer3", &timer3_clk),
374 CLK(NULL, "rto", &rto_clk),
375 CLK(NULL, "usb", &usb_clk),
376 CLK(NULL, NULL, NULL),
379 /*----------------------------------------------------------------------*/
381 static u64 dm355_spi0_dma_mask = DMA_BIT_MASK(32);
383 static struct resource dm355_spi0_resources[] = {
387 .flags = IORESOURCE_MEM,
390 .start = IRQ_DM355_SPINT0_1,
391 .flags = IORESOURCE_IRQ,
393 /* Not yet used, so not included:
395 * - IRQ_DM355_SPINT0_0
397 * - DAVINCI_DMA_SPI_SPIX
398 * - DAVINCI_DMA_SPI_SPIR
402 static struct platform_device dm355_spi0_device = {
403 .name = "spi_davinci",
406 .dma_mask = &dm355_spi0_dma_mask,
407 .coherent_dma_mask = DMA_BIT_MASK(32),
409 .num_resources = ARRAY_SIZE(dm355_spi0_resources),
410 .resource = dm355_spi0_resources,
413 void __init dm355_init_spi0(unsigned chipselect_mask,
414 struct spi_board_info *info, unsigned len)
416 /* for now, assume we need MISO */
417 davinci_cfg_reg(DM355_SPI0_SDI);
419 /* not all slaves will be wired up */
420 if (chipselect_mask & BIT(0))
421 davinci_cfg_reg(DM355_SPI0_SDENA0);
422 if (chipselect_mask & BIT(1))
423 davinci_cfg_reg(DM355_SPI0_SDENA1);
425 spi_register_board_info(info, len);
427 platform_device_register(&dm355_spi0_device);
430 /*----------------------------------------------------------------------*/
433 * Device specific mux setup
435 * soc description mux mode mode mux dbg
436 * reg offset mask mode
438 static const struct mux_config dm355_pins[] = {
439 #ifdef CONFIG_DAVINCI_MUX
440 MUX_CFG(DM355, MMCSD0, 4, 2, 1, 0, false)
442 MUX_CFG(DM355, SD1_CLK, 3, 6, 1, 1, false)
443 MUX_CFG(DM355, SD1_CMD, 3, 7, 1, 1, false)
444 MUX_CFG(DM355, SD1_DATA3, 3, 8, 3, 1, false)
445 MUX_CFG(DM355, SD1_DATA2, 3, 10, 3, 1, false)
446 MUX_CFG(DM355, SD1_DATA1, 3, 12, 3, 1, false)
447 MUX_CFG(DM355, SD1_DATA0, 3, 14, 3, 1, false)
449 MUX_CFG(DM355, I2C_SDA, 3, 19, 1, 1, false)
450 MUX_CFG(DM355, I2C_SCL, 3, 20, 1, 1, false)
452 MUX_CFG(DM355, MCBSP0_BDX, 3, 0, 1, 1, false)
453 MUX_CFG(DM355, MCBSP0_X, 3, 1, 1, 1, false)
454 MUX_CFG(DM355, MCBSP0_BFSX, 3, 2, 1, 1, false)
455 MUX_CFG(DM355, MCBSP0_BDR, 3, 3, 1, 1, false)
456 MUX_CFG(DM355, MCBSP0_R, 3, 4, 1, 1, false)
457 MUX_CFG(DM355, MCBSP0_BFSR, 3, 5, 1, 1, false)
459 MUX_CFG(DM355, SPI0_SDI, 4, 1, 1, 0, false)
460 MUX_CFG(DM355, SPI0_SDENA0, 4, 0, 1, 0, false)
461 MUX_CFG(DM355, SPI0_SDENA1, 3, 28, 1, 1, false)
463 INT_CFG(DM355, INT_EDMA_CC, 2, 1, 1, false)
464 INT_CFG(DM355, INT_EDMA_TC0_ERR, 3, 1, 1, false)
465 INT_CFG(DM355, INT_EDMA_TC1_ERR, 4, 1, 1, false)
467 EVT_CFG(DM355, EVT8_ASP1_TX, 0, 1, 0, false)
468 EVT_CFG(DM355, EVT9_ASP1_RX, 1, 1, 0, false)
469 EVT_CFG(DM355, EVT26_MMC0_RX, 2, 1, 0, false)
473 static u8 dm355_default_priorities[DAVINCI_N_AINTC_IRQ] = {
474 [IRQ_DM355_CCDC_VDINT0] = 2,
475 [IRQ_DM355_CCDC_VDINT1] = 6,
476 [IRQ_DM355_CCDC_VDINT2] = 6,
477 [IRQ_DM355_IPIPE_HST] = 6,
478 [IRQ_DM355_H3AINT] = 6,
479 [IRQ_DM355_IPIPE_SDR] = 6,
480 [IRQ_DM355_IPIPEIFINT] = 6,
481 [IRQ_DM355_OSDINT] = 7,
482 [IRQ_DM355_VENCINT] = 6,
486 [IRQ_DM355_RTOINT] = 4,
487 [IRQ_DM355_UARTINT2] = 7,
488 [IRQ_DM355_TINT6] = 7,
489 [IRQ_CCINT0] = 5, /* dma */
490 [IRQ_CCERRINT] = 5, /* dma */
491 [IRQ_TCERRINT0] = 5, /* dma */
492 [IRQ_TCERRINT] = 5, /* dma */
493 [IRQ_DM355_SPINT2_1] = 7,
494 [IRQ_DM355_TINT7] = 4,
495 [IRQ_DM355_SDIOINT0] = 7,
499 [IRQ_DM355_MMCINT1] = 7,
500 [IRQ_DM355_PWMINT3] = 7,
503 [IRQ_DM355_SDIOINT1] = 4,
504 [IRQ_TINT0_TINT12] = 2, /* clockevent */
505 [IRQ_TINT0_TINT34] = 2, /* clocksource */
506 [IRQ_TINT1_TINT12] = 7, /* DSP timer */
507 [IRQ_TINT1_TINT34] = 7, /* system tick */
514 [IRQ_DM355_SPINT0_0] = 3,
515 [IRQ_DM355_SPINT0_1] = 3,
516 [IRQ_DM355_GPIO0] = 3,
517 [IRQ_DM355_GPIO1] = 7,
518 [IRQ_DM355_GPIO2] = 4,
519 [IRQ_DM355_GPIO3] = 4,
520 [IRQ_DM355_GPIO4] = 7,
521 [IRQ_DM355_GPIO5] = 7,
522 [IRQ_DM355_GPIO6] = 7,
523 [IRQ_DM355_GPIO7] = 7,
524 [IRQ_DM355_GPIO8] = 7,
525 [IRQ_DM355_GPIO9] = 7,
526 [IRQ_DM355_GPIOBNK0] = 7,
527 [IRQ_DM355_GPIOBNK1] = 7,
528 [IRQ_DM355_GPIOBNK2] = 7,
529 [IRQ_DM355_GPIOBNK3] = 7,
530 [IRQ_DM355_GPIOBNK4] = 7,
531 [IRQ_DM355_GPIOBNK5] = 7,
532 [IRQ_DM355_GPIOBNK6] = 7,
538 /*----------------------------------------------------------------------*/
540 static const s8 dma_chan_dm355_no_event[] = {
547 static struct edma_soc_info dm355_edma_info = {
552 .noevent = dma_chan_dm355_no_event,
555 static struct resource edma_resources[] = {
559 .end = 0x01c00000 + SZ_64K - 1,
560 .flags = IORESOURCE_MEM,
565 .end = 0x01c10000 + SZ_1K - 1,
566 .flags = IORESOURCE_MEM,
571 .end = 0x01c10400 + SZ_1K - 1,
572 .flags = IORESOURCE_MEM,
576 .flags = IORESOURCE_IRQ,
579 .start = IRQ_CCERRINT,
580 .flags = IORESOURCE_IRQ,
582 /* not using (or muxing) TC*_ERR */
585 static struct platform_device dm355_edma_device = {
588 .dev.platform_data = &dm355_edma_info,
589 .num_resources = ARRAY_SIZE(edma_resources),
590 .resource = edma_resources,
593 /*----------------------------------------------------------------------*/
595 static struct map_desc dm355_io_desc[] = {
598 .pfn = __phys_to_pfn(IO_PHYS),
604 /* Contents of JTAG ID register used to identify exact cpu type */
605 static struct davinci_id dm355_ids[] = {
609 .manufacturer = 0x00f,
610 .cpu_id = DAVINCI_CPU_ID_DM355,
615 static void __iomem *dm355_psc_bases[] = {
616 IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE),
619 static struct davinci_soc_info davinci_soc_info_dm355 = {
620 .io_desc = dm355_io_desc,
621 .io_desc_num = ARRAY_SIZE(dm355_io_desc),
622 .jtag_id_base = IO_ADDRESS(0x01c40028),
624 .ids_num = ARRAY_SIZE(dm355_ids),
625 .cpu_clks = dm355_clks,
626 .psc_bases = dm355_psc_bases,
627 .psc_bases_num = ARRAY_SIZE(dm355_psc_bases),
628 .pinmux_base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE),
629 .pinmux_pins = dm355_pins,
630 .pinmux_pins_num = ARRAY_SIZE(dm355_pins),
631 .intc_base = IO_ADDRESS(DAVINCI_ARM_INTC_BASE),
632 .intc_type = DAVINCI_INTC_TYPE_AINTC,
633 .intc_irq_prios = dm355_default_priorities,
634 .intc_irq_num = DAVINCI_N_AINTC_IRQ,
637 void __init dm355_init(void)
639 davinci_common_init(&davinci_soc_info_dm355);
642 static int __init dm355_init_devices(void)
644 if (!cpu_is_davinci_dm355())
647 davinci_cfg_reg(DM355_INT_EDMA_CC);
648 platform_device_register(&dm355_edma_device);
651 postcore_initcall(dm355_init_devices);