arch/arm/mach-davinci/dm355.c

   1 /*
   2  * TI DaVinci DM355 chip specific setup
   3  *
   4  * Author: Kevin Hilman, Deep Root Systems, LLC
   5  *
   6  * 2007 (c) Deep Root Systems, LLC. This file is licensed under
   7  * the terms of the GNU General Public License version 2. This program
   8  * is licensed "as is" without any warranty of any kind, whether express
   9  * or implied.
  10  */
  11 #include <linux/kernel.h>
  12 #include <linux/init.h>
  13 #include <linux/clk.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/dma-mapping.h>
  16
  17 #include <linux/spi/spi.h>
  18
  19 #include <asm/mach/map.h>
  20
  21 #include <mach/dm355.h>
  22 #include <mach/clock.h>
  23 #include <mach/cputype.h>
  24 #include <mach/edma.h>
  25 #include <mach/psc.h>
  26 #include <mach/mux.h>
  27 #include <mach/irqs.h>
  28 #include <mach/common.h>
  29
  30 #include "clock.h"
  31 #include "mux.h"
  32
  33 /*
  34  * Device specific clocks
  35  */
  36 #define DM355_REF_FREQ          24000000        /* 24 or 36 MHz */
  37
  38 static struct pll_data pll1_data = {
  39         .num       = 1,
  40         .phys_base = DAVINCI_PLL1_BASE,
  41         .flags     = PLL_HAS_PREDIV | PLL_HAS_POSTDIV,
  42 };
  43
  44 static struct pll_data pll2_data = {
  45         .num       = 2,
  46         .phys_base = DAVINCI_PLL2_BASE,
  47         .flags     = PLL_HAS_PREDIV,
  48 };
  49
  50 static struct clk ref_clk = {
  51         .name = "ref_clk",
  52         /* FIXME -- crystal rate is board-specific */
  53         .rate = DM355_REF_FREQ,
  54 };
  55
  56 static struct clk pll1_clk = {
  57         .name = "pll1",
  58         .parent = &ref_clk,
  59         .flags = CLK_PLL,
  60         .pll_data = &pll1_data,
  61 };
  62
  63 static struct clk pll1_aux_clk = {
  64         .name = "pll1_aux_clk",
  65         .parent = &pll1_clk,
  66         .flags = CLK_PLL | PRE_PLL,
  67 };
  68
  69 static struct clk pll1_sysclk1 = {
  70         .name = "pll1_sysclk1",
  71         .parent = &pll1_clk,
  72         .flags = CLK_PLL,
  73         .div_reg = PLLDIV1,
  74 };
  75
  76 static struct clk pll1_sysclk2 = {
  77         .name = "pll1_sysclk2",
  78         .parent = &pll1_clk,
  79         .flags = CLK_PLL,
  80         .div_reg = PLLDIV2,
  81 };
  82
  83 static struct clk pll1_sysclk3 = {
  84         .name = "pll1_sysclk3",
  85         .parent = &pll1_clk,
  86         .flags = CLK_PLL,
  87         .div_reg = PLLDIV3,
  88 };
  89
  90 static struct clk pll1_sysclk4 = {
  91         .name = "pll1_sysclk4",
  92         .parent = &pll1_clk,
  93         .flags = CLK_PLL,
  94         .div_reg = PLLDIV4,
  95 };
  96
  97 static struct clk pll1_sysclkbp = {
  98         .name = "pll1_sysclkbp",
  99         .parent = &pll1_clk,
 100         .flags = CLK_PLL | PRE_PLL,
 101         .div_reg = BPDIV
 102 };
 103
 104 static struct clk vpss_dac_clk = {
 105         .name = "vpss_dac",
 106         .parent = &pll1_sysclk3,
 107         .lpsc = DM355_LPSC_VPSS_DAC,
 108 };
 109
 110 static struct clk vpss_master_clk = {
 111         .name = "vpss_master",
 112         .parent = &pll1_sysclk4,
 113         .lpsc = DAVINCI_LPSC_VPSSMSTR,
 114         .flags = CLK_PSC,
 115 };
 116
 117 static struct clk vpss_slave_clk = {
 118         .name = "vpss_slave",
 119         .parent = &pll1_sysclk4,
 120         .lpsc = DAVINCI_LPSC_VPSSSLV,
 121 };
 122
 123
 124 static struct clk clkout1_clk = {
 125         .name = "clkout1",
 126         .parent = &pll1_aux_clk,
 127         /* NOTE:  clkout1 can be externally gated by muxing GPIO-18 */
 128 };
 129
 130 static struct clk clkout2_clk = {
 131         .name = "clkout2",
 132         .parent = &pll1_sysclkbp,
 133 };
 134
 135 static struct clk pll2_clk = {
 136         .name = "pll2",
 137         .parent = &ref_clk,
 138         .flags = CLK_PLL,
 139         .pll_data = &pll2_data,
 140 };
 141
 142 static struct clk pll2_sysclk1 = {
 143         .name = "pll2_sysclk1",
 144         .parent = &pll2_clk,
 145         .flags = CLK_PLL,
 146         .div_reg = PLLDIV1,
 147 };
 148
 149 static struct clk pll2_sysclkbp = {
 150         .name = "pll2_sysclkbp",
 151         .parent = &pll2_clk,
 152         .flags = CLK_PLL | PRE_PLL,
 153         .div_reg = BPDIV
 154 };
 155
 156 static struct clk clkout3_clk = {
 157         .name = "clkout3",
 158         .parent = &pll2_sysclkbp,
 159         /* NOTE:  clkout3 can be externally gated by muxing GPIO-16 */
 160 };
 161
 162 static struct clk arm_clk = {
 163         .name = "arm_clk",
 164         .parent = &pll1_sysclk1,
 165         .lpsc = DAVINCI_LPSC_ARM,
 166         .flags = ALWAYS_ENABLED,
 167 };
 168
 169 /*
 170  * NOT LISTED below, and not touched by Linux
 171  *   - in SyncReset state by default
 172  *      .lpsc = DAVINCI_LPSC_TPCC,
 173  *      .lpsc = DAVINCI_LPSC_TPTC0,
 174  *      .lpsc = DAVINCI_LPSC_TPTC1,
 175  *      .lpsc = DAVINCI_LPSC_DDR_EMIF, .parent = &sysclk2_clk,
 176  *      .lpsc = DAVINCI_LPSC_MEMSTICK,
 177  *   - in Enabled state by default
 178  *      .lpsc = DAVINCI_LPSC_SYSTEM_SUBSYS,
 179  *      .lpsc = DAVINCI_LPSC_SCR2,      // "bus"
 180  *      .lpsc = DAVINCI_LPSC_SCR3,      // "bus"
 181  *      .lpsc = DAVINCI_LPSC_SCR4,      // "bus"
 182  *      .lpsc = DAVINCI_LPSC_CROSSBAR,  // "emulation"
 183  *      .lpsc = DAVINCI_LPSC_CFG27,     // "test"
 184  *      .lpsc = DAVINCI_LPSC_CFG3,      // "test"
 185  *      .lpsc = DAVINCI_LPSC_CFG5,      // "test"
 186  */
 187
 188 static struct clk mjcp_clk = {
 189         .name = "mjcp",
 190         .parent = &pll1_sysclk1,
 191         .lpsc = DAVINCI_LPSC_IMCOP,
 192 };
 193
 194 static struct clk uart0_clk = {
 195         .name = "uart0",
 196         .parent = &pll1_aux_clk,
 197         .lpsc = DAVINCI_LPSC_UART0,
 198 };
 199
 200 static struct clk uart1_clk = {
 201         .name = "uart1",
 202         .parent = &pll1_aux_clk,
 203         .lpsc = DAVINCI_LPSC_UART1,
 204 };
 205
 206 static struct clk uart2_clk = {
 207         .name = "uart2",
 208         .parent = &pll1_sysclk2,
 209         .lpsc = DAVINCI_LPSC_UART2,
 210 };
 211
 212 static struct clk i2c_clk = {
 213         .name = "i2c",
 214         .parent = &pll1_aux_clk,
 215         .lpsc = DAVINCI_LPSC_I2C,
 216 };
 217
 218 static struct clk asp0_clk = {
 219         .name = "asp0",
 220         .parent = &pll1_sysclk2,
 221         .lpsc = DAVINCI_LPSC_McBSP,
 222 };
 223
 224 static struct clk asp1_clk = {
 225         .name = "asp1",
 226         .parent = &pll1_sysclk2,
 227         .lpsc = DM355_LPSC_McBSP1,
 228 };
 229
 230 static struct clk mmcsd0_clk = {
 231         .name = "mmcsd0",
 232         .parent = &pll1_sysclk2,
 233         .lpsc = DAVINCI_LPSC_MMC_SD,
 234 };
 235
 236 static struct clk mmcsd1_clk = {
 237         .name = "mmcsd1",
 238         .parent = &pll1_sysclk2,
 239         .lpsc = DM355_LPSC_MMC_SD1,
 240 };
 241
 242 static struct clk spi0_clk = {
 243         .name = "spi0",
 244         .parent = &pll1_sysclk2,
 245         .lpsc = DAVINCI_LPSC_SPI,
 246 };
 247
 248 static struct clk spi1_clk = {
 249         .name = "spi1",
 250         .parent = &pll1_sysclk2,
 251         .lpsc = DM355_LPSC_SPI1,
 252 };
 253
 254 static struct clk spi2_clk = {
 255         .name = "spi2",
 256         .parent = &pll1_sysclk2,
 257         .lpsc = DM355_LPSC_SPI2,
 258 };
 259
 260 static struct clk gpio_clk = {
 261         .name = "gpio",
 262         .parent = &pll1_sysclk2,
 263         .lpsc = DAVINCI_LPSC_GPIO,
 264 };
 265
 266 static struct clk aemif_clk = {
 267         .name = "aemif",
 268         .parent = &pll1_sysclk2,
 269         .lpsc = DAVINCI_LPSC_AEMIF,
 270 };
 271
 272 static struct clk pwm0_clk = {
 273         .name = "pwm0",
 274         .parent = &pll1_aux_clk,
 275         .lpsc = DAVINCI_LPSC_PWM0,
 276 };
 277
 278 static struct clk pwm1_clk = {
 279         .name = "pwm1",
 280         .parent = &pll1_aux_clk,
 281         .lpsc = DAVINCI_LPSC_PWM1,
 282 };
 283
 284 static struct clk pwm2_clk = {
 285         .name = "pwm2",
 286         .parent = &pll1_aux_clk,
 287         .lpsc = DAVINCI_LPSC_PWM2,
 288 };
 289
 290 static struct clk pwm3_clk = {
 291         .name = "pwm3",
 292         .parent = &pll1_aux_clk,
 293         .lpsc = DM355_LPSC_PWM3,
 294 };
 295
 296 static struct clk timer0_clk = {
 297         .name = "timer0",
 298         .parent = &pll1_aux_clk,
 299         .lpsc = DAVINCI_LPSC_TIMER0,
 300 };
 301
 302 static struct clk timer1_clk = {
 303         .name = "timer1",
 304         .parent = &pll1_aux_clk,
 305         .lpsc = DAVINCI_LPSC_TIMER1,
 306 };
 307
 308 static struct clk timer2_clk = {
 309         .name = "timer2",
 310         .parent = &pll1_aux_clk,
 311         .lpsc = DAVINCI_LPSC_TIMER2,
 312         .usecount = 1,              /* REVISIT: why cant' this be disabled? */
 313 };
 314
 315 static struct clk timer3_clk = {
 316         .name = "timer3",
 317         .parent = &pll1_aux_clk,
 318         .lpsc = DM355_LPSC_TIMER3,
 319 };
 320
 321 static struct clk rto_clk = {
 322         .name = "rto",
 323         .parent = &pll1_aux_clk,
 324         .lpsc = DM355_LPSC_RTO,
 325 };
 326
 327 static struct clk usb_clk = {
 328         .name = "usb",
 329         .parent = &pll1_sysclk2,
 330         .lpsc = DAVINCI_LPSC_USB,
 331 };
 332
 333 static struct davinci_clk dm355_clks[] = {
 334         CLK(NULL, "ref", &ref_clk),
 335         CLK(NULL, "pll1", &pll1_clk),
 336         CLK(NULL, "pll1_sysclk1", &pll1_sysclk1),
 337         CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
 338         CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
 339         CLK(NULL, "pll1_sysclk4", &pll1_sysclk4),
 340         CLK(NULL, "pll1_aux", &pll1_aux_clk),
 341         CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp),
 342         CLK(NULL, "vpss_dac", &vpss_dac_clk),
 343         CLK(NULL, "vpss_master", &vpss_master_clk),
 344         CLK(NULL, "vpss_slave", &vpss_slave_clk),
 345         CLK(NULL, "clkout1", &clkout1_clk),
 346         CLK(NULL, "clkout2", &clkout2_clk),
 347         CLK(NULL, "pll2", &pll2_clk),
 348         CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
 349         CLK(NULL, "pll2_sysclkbp", &pll2_sysclkbp),
 350         CLK(NULL, "clkout3", &clkout3_clk),
 351         CLK(NULL, "arm", &arm_clk),
 352         CLK(NULL, "mjcp", &mjcp_clk),
 353         CLK(NULL, "uart0", &uart0_clk),
 354         CLK(NULL, "uart1", &uart1_clk),
 355         CLK(NULL, "uart2", &uart2_clk),
 356         CLK("i2c_davinci.1", NULL, &i2c_clk),
 357         CLK("soc-audio.0", NULL, &asp0_clk),
 358         CLK("soc-audio.1", NULL, &asp1_clk),
 359         CLK("davinci_mmc.0", NULL, &mmcsd0_clk),
 360         CLK("davinci_mmc.1", NULL, &mmcsd1_clk),
 361         CLK(NULL, "spi0", &spi0_clk),
 362         CLK(NULL, "spi1", &spi1_clk),
 363         CLK(NULL, "spi2", &spi2_clk),
 364         CLK(NULL, "gpio", &gpio_clk),
 365         CLK(NULL, "aemif", &aemif_clk),
 366         CLK(NULL, "pwm0", &pwm0_clk),
 367         CLK(NULL, "pwm1", &pwm1_clk),
 368         CLK(NULL, "pwm2", &pwm2_clk),
 369         CLK(NULL, "pwm3", &pwm3_clk),
 370         CLK(NULL, "timer0", &timer0_clk),
 371         CLK(NULL, "timer1", &timer1_clk),
 372         CLK("watchdog", NULL, &timer2_clk),
 373         CLK(NULL, "timer3", &timer3_clk),
 374         CLK(NULL, "rto", &rto_clk),
 375         CLK(NULL, "usb", &usb_clk),
 376         CLK(NULL, NULL, NULL),
 377 };
 378
 379 /*----------------------------------------------------------------------*/
 380
 381 static u64 dm355_spi0_dma_mask = DMA_BIT_MASK(32);
 382
 383 static struct resource dm355_spi0_resources[] = {
 384         {
 385                 .start = 0x01c66000,
 386                 .end   = 0x01c667ff,
 387                 .flags = IORESOURCE_MEM,
 388         },
 389         {
 390                 .start = IRQ_DM355_SPINT0_1,
 391                 .flags = IORESOURCE_IRQ,
 392         },
 393         /* Not yet used, so not included:
 394          * IORESOURCE_IRQ:
 395          *  - IRQ_DM355_SPINT0_0
 396          * IORESOURCE_DMA:
 397          *  - DAVINCI_DMA_SPI_SPIX
 398          *  - DAVINCI_DMA_SPI_SPIR
 399          */
 400 };
 401
 402 static struct platform_device dm355_spi0_device = {
 403         .name = "spi_davinci",
 404         .id = 0,
 405         .dev = {
 406                 .dma_mask = &dm355_spi0_dma_mask,
 407                 .coherent_dma_mask = DMA_BIT_MASK(32),
 408         },
 409         .num_resources = ARRAY_SIZE(dm355_spi0_resources),
 410         .resource = dm355_spi0_resources,
 411 };
 412
 413 void __init dm355_init_spi0(unsigned chipselect_mask,
 414                 struct spi_board_info *info, unsigned len)
 415 {
 416         /* for now, assume we need MISO */
 417         davinci_cfg_reg(DM355_SPI0_SDI);
 418
 419         /* not all slaves will be wired up */
 420         if (chipselect_mask & BIT(0))
 421                 davinci_cfg_reg(DM355_SPI0_SDENA0);
 422         if (chipselect_mask & BIT(1))
 423                 davinci_cfg_reg(DM355_SPI0_SDENA1);
 424
 425         spi_register_board_info(info, len);
 426
 427         platform_device_register(&dm355_spi0_device);
 428 }
 429
 430 /*----------------------------------------------------------------------*/
 431
 432 /*
 433  * Device specific mux setup
 434  *
 435  *      soc     description     mux  mode   mode  mux    dbg
 436  *                              reg  offset mask  mode
 437  */
 438 static const struct mux_config dm355_pins[] = {
 439 #ifdef CONFIG_DAVINCI_MUX
 440 MUX_CFG(DM355,  MMCSD0,         4,   2,     1,    0,     false)
 441
 442 MUX_CFG(DM355,  SD1_CLK,        3,   6,     1,    1,     false)
 443 MUX_CFG(DM355,  SD1_CMD,        3,   7,     1,    1,     false)
 444 MUX_CFG(DM355,  SD1_DATA3,      3,   8,     3,    1,     false)
 445 MUX_CFG(DM355,  SD1_DATA2,      3,   10,    3,    1,     false)
 446 MUX_CFG(DM355,  SD1_DATA1,      3,   12,    3,    1,     false)
 447 MUX_CFG(DM355,  SD1_DATA0,      3,   14,    3,    1,     false)
 448
 449 MUX_CFG(DM355,  I2C_SDA,        3,   19,    1,    1,     false)
 450 MUX_CFG(DM355,  I2C_SCL,        3,   20,    1,    1,     false)
 451
 452 MUX_CFG(DM355,  MCBSP0_BDX,     3,   0,     1,    1,     false)
 453 MUX_CFG(DM355,  MCBSP0_X,       3,   1,     1,    1,     false)
 454 MUX_CFG(DM355,  MCBSP0_BFSX,    3,   2,     1,    1,     false)
 455 MUX_CFG(DM355,  MCBSP0_BDR,     3,   3,     1,    1,     false)
 456 MUX_CFG(DM355,  MCBSP0_R,       3,   4,     1,    1,     false)
 457 MUX_CFG(DM355,  MCBSP0_BFSR,    3,   5,     1,    1,     false)
 458
 459 MUX_CFG(DM355,  SPI0_SDI,       4,   1,     1,    0,     false)
 460 MUX_CFG(DM355,  SPI0_SDENA0,    4,   0,     1,    0,     false)
 461 MUX_CFG(DM355,  SPI0_SDENA1,    3,   28,    1,    1,     false)
 462
 463 INT_CFG(DM355,  INT_EDMA_CC,          2,    1,    1,     false)
 464 INT_CFG(DM355,  INT_EDMA_TC0_ERR,     3,    1,    1,     false)
 465 INT_CFG(DM355,  INT_EDMA_TC1_ERR,     4,    1,    1,     false)
 466
 467 EVT_CFG(DM355,  EVT8_ASP1_TX,         0,    1,    0,     false)
 468 EVT_CFG(DM355,  EVT9_ASP1_RX,         1,    1,    0,     false)
 469 EVT_CFG(DM355,  EVT26_MMC0_RX,        2,    1,    0,     false)
 470 #endif
 471 };
 472
 473 /*----------------------------------------------------------------------*/
 474
 475 static const s8 dma_chan_dm355_no_event[] = {
 476         12, 13, 24, 56, 57,
 477         58, 59, 60, 61, 62,
 478         63,
 479         -1
 480 };
 481
 482 static struct edma_soc_info dm355_edma_info = {
 483         .n_channel      = 64,
 484         .n_region       = 4,
 485         .n_slot         = 128,
 486         .n_tc           = 2,
 487         .noevent        = dma_chan_dm355_no_event,
 488 };
 489
 490 static struct resource edma_resources[] = {
 491         {
 492                 .name   = "edma_cc",
 493                 .start  = 0x01c00000,
 494                 .end    = 0x01c00000 + SZ_64K - 1,
 495                 .flags  = IORESOURCE_MEM,
 496         },
 497         {
 498                 .name   = "edma_tc0",
 499                 .start  = 0x01c10000,
 500                 .end    = 0x01c10000 + SZ_1K - 1,
 501                 .flags  = IORESOURCE_MEM,
 502         },
 503         {
 504                 .name   = "edma_tc1",
 505                 .start  = 0x01c10400,
 506                 .end    = 0x01c10400 + SZ_1K - 1,
 507                 .flags  = IORESOURCE_MEM,
 508         },
 509         {
 510                 .start  = IRQ_CCINT0,
 511                 .flags  = IORESOURCE_IRQ,
 512         },
 513         {
 514                 .start  = IRQ_CCERRINT,
 515                 .flags  = IORESOURCE_IRQ,
 516         },
 517         /* not using (or muxing) TC*_ERR */
 518 };
 519
 520 static struct platform_device dm355_edma_device = {
 521         .name                   = "edma",
 522         .id                     = -1,
 523         .dev.platform_data      = &dm355_edma_info,
 524         .num_resources          = ARRAY_SIZE(edma_resources),
 525         .resource               = edma_resources,
 526 };
 527
 528 /*----------------------------------------------------------------------*/
 529
 530 static struct map_desc dm355_io_desc[] = {
 531         {
 532                 .virtual        = IO_VIRT,
 533                 .pfn            = __phys_to_pfn(IO_PHYS),
 534                 .length         = IO_SIZE,
 535                 .type           = MT_DEVICE
 536         },
 537 };
 538
 539 /* Contents of JTAG ID register used to identify exact cpu type */
 540 static struct davinci_id dm355_ids[] = {
 541         {
 542                 .variant        = 0x0,
 543                 .part_no        = 0xb73b,
 544                 .manufacturer   = 0x00f,
 545                 .cpu_id         = DAVINCI_CPU_ID_DM355,
 546                 .name           = "dm355",
 547         },
 548 };
 549
 550 static void __iomem *dm355_psc_bases[] = {
 551         IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE),
 552 };
 553
 554 static struct davinci_soc_info davinci_soc_info_dm355 = {
 555         .io_desc                = dm355_io_desc,
 556         .io_desc_num            = ARRAY_SIZE(dm355_io_desc),
 557         .jtag_id_base           = IO_ADDRESS(0x01c40028),
 558         .ids                    = dm355_ids,
 559         .ids_num                = ARRAY_SIZE(dm355_ids),
 560         .cpu_clks               = dm355_clks,
 561         .psc_bases              = dm355_psc_bases,
 562         .psc_bases_num          = ARRAY_SIZE(dm355_psc_bases),
 563         .pinmux_base            = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE),
 564         .pinmux_pins            = dm355_pins,
 565         .pinmux_pins_num        = ARRAY_SIZE(dm355_pins),
 566 };
 567
 568 void __init dm355_init(void)
 569 {
 570         davinci_common_init(&davinci_soc_info_dm355);
 571 }
 572
 573 static int __init dm355_init_devices(void)
 574 {
 575         if (!cpu_is_davinci_dm355())
 576                 return 0;
 577
 578         davinci_cfg_reg(DM355_INT_EDMA_CC);
 579         platform_device_register(&dm355_edma_device);
 580         return 0;
 581 }
 582 postcore_initcall(dm355_init_devices);