2 * TI DaVinci DM355 chip specific setup
4 * Author: Kevin Hilman, Deep Root Systems, LLC
6 * 2007 (c) Deep Root Systems, LLC. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
11 #include <linux/init.h>
12 #include <linux/clk.h>
13 #include <linux/serial_8250.h>
14 #include <linux/platform_device.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/spi/spi.h>
17 #include <linux/platform_data/edma.h>
18 #include <linux/platform_data/gpio-davinci.h>
19 #include <linux/platform_data/spi-davinci.h>
21 #include <asm/mach/map.h>
23 #include <mach/cputype.h>
26 #include <mach/irqs.h>
27 #include <mach/time.h>
28 #include <mach/serial.h>
29 #include <mach/common.h>
36 #define DM355_UART2_BASE (IO_PHYS + 0x206000)
37 #define DM355_OSD_BASE (IO_PHYS + 0x70200)
38 #define DM355_VENC_BASE (IO_PHYS + 0x70400)
41 * Device specific clocks
43 #define DM355_REF_FREQ 24000000 /* 24 or 36 MHz */
45 static struct pll_data pll1_data = {
47 .phys_base = DAVINCI_PLL1_BASE,
48 .flags = PLL_HAS_PREDIV | PLL_HAS_POSTDIV,
51 static struct pll_data pll2_data = {
53 .phys_base = DAVINCI_PLL2_BASE,
54 .flags = PLL_HAS_PREDIV,
57 static struct clk ref_clk = {
59 /* FIXME -- crystal rate is board-specific */
60 .rate = DM355_REF_FREQ,
63 static struct clk pll1_clk = {
67 .pll_data = &pll1_data,
70 static struct clk pll1_aux_clk = {
71 .name = "pll1_aux_clk",
73 .flags = CLK_PLL | PRE_PLL,
76 static struct clk pll1_sysclk1 = {
77 .name = "pll1_sysclk1",
83 static struct clk pll1_sysclk2 = {
84 .name = "pll1_sysclk2",
90 static struct clk pll1_sysclk3 = {
91 .name = "pll1_sysclk3",
97 static struct clk pll1_sysclk4 = {
98 .name = "pll1_sysclk4",
104 static struct clk pll1_sysclkbp = {
105 .name = "pll1_sysclkbp",
107 .flags = CLK_PLL | PRE_PLL,
111 static struct clk vpss_dac_clk = {
113 .parent = &pll1_sysclk3,
114 .lpsc = DM355_LPSC_VPSS_DAC,
117 static struct clk vpss_master_clk = {
118 .name = "vpss_master",
119 .parent = &pll1_sysclk4,
120 .lpsc = DAVINCI_LPSC_VPSSMSTR,
124 static struct clk vpss_slave_clk = {
125 .name = "vpss_slave",
126 .parent = &pll1_sysclk4,
127 .lpsc = DAVINCI_LPSC_VPSSSLV,
130 static struct clk clkout1_clk = {
132 .parent = &pll1_aux_clk,
133 /* NOTE: clkout1 can be externally gated by muxing GPIO-18 */
136 static struct clk clkout2_clk = {
138 .parent = &pll1_sysclkbp,
141 static struct clk pll2_clk = {
145 .pll_data = &pll2_data,
148 static struct clk pll2_sysclk1 = {
149 .name = "pll2_sysclk1",
155 static struct clk pll2_sysclkbp = {
156 .name = "pll2_sysclkbp",
158 .flags = CLK_PLL | PRE_PLL,
162 static struct clk clkout3_clk = {
164 .parent = &pll2_sysclkbp,
165 /* NOTE: clkout3 can be externally gated by muxing GPIO-16 */
168 static struct clk arm_clk = {
170 .parent = &pll1_sysclk1,
171 .lpsc = DAVINCI_LPSC_ARM,
172 .flags = ALWAYS_ENABLED,
176 * NOT LISTED below, and not touched by Linux
177 * - in SyncReset state by default
178 * .lpsc = DAVINCI_LPSC_TPCC,
179 * .lpsc = DAVINCI_LPSC_TPTC0,
180 * .lpsc = DAVINCI_LPSC_TPTC1,
181 * .lpsc = DAVINCI_LPSC_DDR_EMIF, .parent = &sysclk2_clk,
182 * .lpsc = DAVINCI_LPSC_MEMSTICK,
183 * - in Enabled state by default
184 * .lpsc = DAVINCI_LPSC_SYSTEM_SUBSYS,
185 * .lpsc = DAVINCI_LPSC_SCR2, // "bus"
186 * .lpsc = DAVINCI_LPSC_SCR3, // "bus"
187 * .lpsc = DAVINCI_LPSC_SCR4, // "bus"
188 * .lpsc = DAVINCI_LPSC_CROSSBAR, // "emulation"
189 * .lpsc = DAVINCI_LPSC_CFG27, // "test"
190 * .lpsc = DAVINCI_LPSC_CFG3, // "test"
191 * .lpsc = DAVINCI_LPSC_CFG5, // "test"
194 static struct clk mjcp_clk = {
196 .parent = &pll1_sysclk1,
197 .lpsc = DAVINCI_LPSC_IMCOP,
200 static struct clk uart0_clk = {
202 .parent = &pll1_aux_clk,
203 .lpsc = DAVINCI_LPSC_UART0,
206 static struct clk uart1_clk = {
208 .parent = &pll1_aux_clk,
209 .lpsc = DAVINCI_LPSC_UART1,
212 static struct clk uart2_clk = {
214 .parent = &pll1_sysclk2,
215 .lpsc = DAVINCI_LPSC_UART2,
218 static struct clk i2c_clk = {
220 .parent = &pll1_aux_clk,
221 .lpsc = DAVINCI_LPSC_I2C,
224 static struct clk asp0_clk = {
226 .parent = &pll1_sysclk2,
227 .lpsc = DAVINCI_LPSC_McBSP,
230 static struct clk asp1_clk = {
232 .parent = &pll1_sysclk2,
233 .lpsc = DM355_LPSC_McBSP1,
236 static struct clk mmcsd0_clk = {
238 .parent = &pll1_sysclk2,
239 .lpsc = DAVINCI_LPSC_MMC_SD,
242 static struct clk mmcsd1_clk = {
244 .parent = &pll1_sysclk2,
245 .lpsc = DM355_LPSC_MMC_SD1,
248 static struct clk spi0_clk = {
250 .parent = &pll1_sysclk2,
251 .lpsc = DAVINCI_LPSC_SPI,
254 static struct clk spi1_clk = {
256 .parent = &pll1_sysclk2,
257 .lpsc = DM355_LPSC_SPI1,
260 static struct clk spi2_clk = {
262 .parent = &pll1_sysclk2,
263 .lpsc = DM355_LPSC_SPI2,
266 static struct clk gpio_clk = {
268 .parent = &pll1_sysclk2,
269 .lpsc = DAVINCI_LPSC_GPIO,
272 static struct clk aemif_clk = {
274 .parent = &pll1_sysclk2,
275 .lpsc = DAVINCI_LPSC_AEMIF,
278 static struct clk pwm0_clk = {
280 .parent = &pll1_aux_clk,
281 .lpsc = DAVINCI_LPSC_PWM0,
284 static struct clk pwm1_clk = {
286 .parent = &pll1_aux_clk,
287 .lpsc = DAVINCI_LPSC_PWM1,
290 static struct clk pwm2_clk = {
292 .parent = &pll1_aux_clk,
293 .lpsc = DAVINCI_LPSC_PWM2,
296 static struct clk pwm3_clk = {
298 .parent = &pll1_aux_clk,
299 .lpsc = DM355_LPSC_PWM3,
302 static struct clk timer0_clk = {
304 .parent = &pll1_aux_clk,
305 .lpsc = DAVINCI_LPSC_TIMER0,
308 static struct clk timer1_clk = {
310 .parent = &pll1_aux_clk,
311 .lpsc = DAVINCI_LPSC_TIMER1,
314 static struct clk timer2_clk = {
316 .parent = &pll1_aux_clk,
317 .lpsc = DAVINCI_LPSC_TIMER2,
318 .usecount = 1, /* REVISIT: why can't this be disabled? */
321 static struct clk timer3_clk = {
323 .parent = &pll1_aux_clk,
324 .lpsc = DM355_LPSC_TIMER3,
327 static struct clk rto_clk = {
329 .parent = &pll1_aux_clk,
330 .lpsc = DM355_LPSC_RTO,
333 static struct clk usb_clk = {
335 .parent = &pll1_sysclk2,
336 .lpsc = DAVINCI_LPSC_USB,
339 static struct clk_lookup dm355_clks[] = {
340 CLK(NULL, "ref", &ref_clk),
341 CLK(NULL, "pll1", &pll1_clk),
342 CLK(NULL, "pll1_sysclk1", &pll1_sysclk1),
343 CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
344 CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
345 CLK(NULL, "pll1_sysclk4", &pll1_sysclk4),
346 CLK(NULL, "pll1_aux", &pll1_aux_clk),
347 CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp),
348 CLK(NULL, "vpss_dac", &vpss_dac_clk),
349 CLK("vpss", "master", &vpss_master_clk),
350 CLK("vpss", "slave", &vpss_slave_clk),
351 CLK(NULL, "clkout1", &clkout1_clk),
352 CLK(NULL, "clkout2", &clkout2_clk),
353 CLK(NULL, "pll2", &pll2_clk),
354 CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
355 CLK(NULL, "pll2_sysclkbp", &pll2_sysclkbp),
356 CLK(NULL, "clkout3", &clkout3_clk),
357 CLK(NULL, "arm", &arm_clk),
358 CLK(NULL, "mjcp", &mjcp_clk),
359 CLK("serial8250.0", NULL, &uart0_clk),
360 CLK("serial8250.1", NULL, &uart1_clk),
361 CLK("serial8250.2", NULL, &uart2_clk),
362 CLK("i2c_davinci.1", NULL, &i2c_clk),
363 CLK("davinci-mcbsp.0", NULL, &asp0_clk),
364 CLK("davinci-mcbsp.1", NULL, &asp1_clk),
365 CLK("dm6441-mmc.0", NULL, &mmcsd0_clk),
366 CLK("dm6441-mmc.1", NULL, &mmcsd1_clk),
367 CLK("spi_davinci.0", NULL, &spi0_clk),
368 CLK("spi_davinci.1", NULL, &spi1_clk),
369 CLK("spi_davinci.2", NULL, &spi2_clk),
370 CLK(NULL, "gpio", &gpio_clk),
371 CLK(NULL, "aemif", &aemif_clk),
372 CLK(NULL, "pwm0", &pwm0_clk),
373 CLK(NULL, "pwm1", &pwm1_clk),
374 CLK(NULL, "pwm2", &pwm2_clk),
375 CLK(NULL, "pwm3", &pwm3_clk),
376 CLK(NULL, "timer0", &timer0_clk),
377 CLK(NULL, "timer1", &timer1_clk),
378 CLK("watchdog", NULL, &timer2_clk),
379 CLK(NULL, "timer3", &timer3_clk),
380 CLK(NULL, "rto", &rto_clk),
381 CLK(NULL, "usb", &usb_clk),
382 CLK(NULL, NULL, NULL),
385 /*----------------------------------------------------------------------*/
387 static u64 dm355_spi0_dma_mask = DMA_BIT_MASK(32);
389 static struct resource dm355_spi0_resources[] = {
393 .flags = IORESOURCE_MEM,
396 .start = IRQ_DM355_SPINT0_0,
397 .flags = IORESOURCE_IRQ,
401 .flags = IORESOURCE_DMA,
405 .flags = IORESOURCE_DMA,
409 static struct davinci_spi_platform_data dm355_spi0_pdata = {
410 .version = SPI_VERSION_1,
413 .dma_event_q = EVENTQ_1,
415 static struct platform_device dm355_spi0_device = {
416 .name = "spi_davinci",
419 .dma_mask = &dm355_spi0_dma_mask,
420 .coherent_dma_mask = DMA_BIT_MASK(32),
421 .platform_data = &dm355_spi0_pdata,
423 .num_resources = ARRAY_SIZE(dm355_spi0_resources),
424 .resource = dm355_spi0_resources,
427 void __init dm355_init_spi0(unsigned chipselect_mask,
428 const struct spi_board_info *info, unsigned len)
430 /* for now, assume we need MISO */
431 davinci_cfg_reg(DM355_SPI0_SDI);
433 /* not all slaves will be wired up */
434 if (chipselect_mask & BIT(0))
435 davinci_cfg_reg(DM355_SPI0_SDENA0);
436 if (chipselect_mask & BIT(1))
437 davinci_cfg_reg(DM355_SPI0_SDENA1);
439 spi_register_board_info(info, len);
441 platform_device_register(&dm355_spi0_device);
444 /*----------------------------------------------------------------------*/
450 * Device specific mux setup
452 * soc description mux mode mode mux dbg
453 * reg offset mask mode
455 static const struct mux_config dm355_pins[] = {
456 #ifdef CONFIG_DAVINCI_MUX
457 MUX_CFG(DM355, MMCSD0, 4, 2, 1, 0, false)
459 MUX_CFG(DM355, SD1_CLK, 3, 6, 1, 1, false)
460 MUX_CFG(DM355, SD1_CMD, 3, 7, 1, 1, false)
461 MUX_CFG(DM355, SD1_DATA3, 3, 8, 3, 1, false)
462 MUX_CFG(DM355, SD1_DATA2, 3, 10, 3, 1, false)
463 MUX_CFG(DM355, SD1_DATA1, 3, 12, 3, 1, false)
464 MUX_CFG(DM355, SD1_DATA0, 3, 14, 3, 1, false)
466 MUX_CFG(DM355, I2C_SDA, 3, 19, 1, 1, false)
467 MUX_CFG(DM355, I2C_SCL, 3, 20, 1, 1, false)
469 MUX_CFG(DM355, MCBSP0_BDX, 3, 0, 1, 1, false)
470 MUX_CFG(DM355, MCBSP0_X, 3, 1, 1, 1, false)
471 MUX_CFG(DM355, MCBSP0_BFSX, 3, 2, 1, 1, false)
472 MUX_CFG(DM355, MCBSP0_BDR, 3, 3, 1, 1, false)
473 MUX_CFG(DM355, MCBSP0_R, 3, 4, 1, 1, false)
474 MUX_CFG(DM355, MCBSP0_BFSR, 3, 5, 1, 1, false)
476 MUX_CFG(DM355, SPI0_SDI, 4, 1, 1, 0, false)
477 MUX_CFG(DM355, SPI0_SDENA0, 4, 0, 1, 0, false)
478 MUX_CFG(DM355, SPI0_SDENA1, 3, 28, 1, 1, false)
480 INT_CFG(DM355, INT_EDMA_CC, 2, 1, 1, false)
481 INT_CFG(DM355, INT_EDMA_TC0_ERR, 3, 1, 1, false)
482 INT_CFG(DM355, INT_EDMA_TC1_ERR, 4, 1, 1, false)
484 EVT_CFG(DM355, EVT8_ASP1_TX, 0, 1, 0, false)
485 EVT_CFG(DM355, EVT9_ASP1_RX, 1, 1, 0, false)
486 EVT_CFG(DM355, EVT26_MMC0_RX, 2, 1, 0, false)
488 MUX_CFG(DM355, VOUT_FIELD, 1, 18, 3, 1, false)
489 MUX_CFG(DM355, VOUT_FIELD_G70, 1, 18, 3, 0, false)
490 MUX_CFG(DM355, VOUT_HVSYNC, 1, 16, 1, 0, false)
491 MUX_CFG(DM355, VOUT_COUTL_EN, 1, 0, 0xff, 0x55, false)
492 MUX_CFG(DM355, VOUT_COUTH_EN, 1, 8, 0xff, 0x55, false)
494 MUX_CFG(DM355, VIN_PCLK, 0, 14, 1, 1, false)
495 MUX_CFG(DM355, VIN_CAM_WEN, 0, 13, 1, 1, false)
496 MUX_CFG(DM355, VIN_CAM_VD, 0, 12, 1, 1, false)
497 MUX_CFG(DM355, VIN_CAM_HD, 0, 11, 1, 1, false)
498 MUX_CFG(DM355, VIN_YIN_EN, 0, 10, 1, 1, false)
499 MUX_CFG(DM355, VIN_CINL_EN, 0, 0, 0xff, 0x55, false)
500 MUX_CFG(DM355, VIN_CINH_EN, 0, 8, 3, 3, false)
504 static u8 dm355_default_priorities[DAVINCI_N_AINTC_IRQ] = {
505 [IRQ_DM355_CCDC_VDINT0] = 2,
506 [IRQ_DM355_CCDC_VDINT1] = 6,
507 [IRQ_DM355_CCDC_VDINT2] = 6,
508 [IRQ_DM355_IPIPE_HST] = 6,
509 [IRQ_DM355_H3AINT] = 6,
510 [IRQ_DM355_IPIPE_SDR] = 6,
511 [IRQ_DM355_IPIPEIFINT] = 6,
512 [IRQ_DM355_OSDINT] = 7,
513 [IRQ_DM355_VENCINT] = 6,
517 [IRQ_DM355_RTOINT] = 4,
518 [IRQ_DM355_UARTINT2] = 7,
519 [IRQ_DM355_TINT6] = 7,
520 [IRQ_CCINT0] = 5, /* dma */
521 [IRQ_CCERRINT] = 5, /* dma */
522 [IRQ_TCERRINT0] = 5, /* dma */
523 [IRQ_TCERRINT] = 5, /* dma */
524 [IRQ_DM355_SPINT2_1] = 7,
525 [IRQ_DM355_TINT7] = 4,
526 [IRQ_DM355_SDIOINT0] = 7,
530 [IRQ_DM355_MMCINT1] = 7,
531 [IRQ_DM355_PWMINT3] = 7,
534 [IRQ_DM355_SDIOINT1] = 4,
535 [IRQ_TINT0_TINT12] = 2, /* clockevent */
536 [IRQ_TINT0_TINT34] = 2, /* clocksource */
537 [IRQ_TINT1_TINT12] = 7, /* DSP timer */
538 [IRQ_TINT1_TINT34] = 7, /* system tick */
545 [IRQ_DM355_SPINT0_0] = 3,
546 [IRQ_DM355_SPINT0_1] = 3,
547 [IRQ_DM355_GPIO0] = 3,
548 [IRQ_DM355_GPIO1] = 7,
549 [IRQ_DM355_GPIO2] = 4,
550 [IRQ_DM355_GPIO3] = 4,
551 [IRQ_DM355_GPIO4] = 7,
552 [IRQ_DM355_GPIO5] = 7,
553 [IRQ_DM355_GPIO6] = 7,
554 [IRQ_DM355_GPIO7] = 7,
555 [IRQ_DM355_GPIO8] = 7,
556 [IRQ_DM355_GPIO9] = 7,
557 [IRQ_DM355_GPIOBNK0] = 7,
558 [IRQ_DM355_GPIOBNK1] = 7,
559 [IRQ_DM355_GPIOBNK2] = 7,
560 [IRQ_DM355_GPIOBNK3] = 7,
561 [IRQ_DM355_GPIOBNK4] = 7,
562 [IRQ_DM355_GPIOBNK5] = 7,
563 [IRQ_DM355_GPIOBNK6] = 7,
569 /*----------------------------------------------------------------------*/
572 queue_tc_mapping[][2] = {
573 /* {event queue no, TC no} */
580 queue_priority_mapping[][2] = {
581 /* {event queue no, Priority} */
587 static struct edma_soc_info edma_cc0_info = {
593 .queue_tc_mapping = queue_tc_mapping,
594 .queue_priority_mapping = queue_priority_mapping,
595 .default_queue = EVENTQ_1,
598 static struct edma_soc_info *dm355_edma_info[EDMA_MAX_CC] = {
602 static struct resource edma_resources[] = {
606 .end = 0x01c00000 + SZ_64K - 1,
607 .flags = IORESOURCE_MEM,
612 .end = 0x01c10000 + SZ_1K - 1,
613 .flags = IORESOURCE_MEM,
618 .end = 0x01c10400 + SZ_1K - 1,
619 .flags = IORESOURCE_MEM,
624 .flags = IORESOURCE_IRQ,
628 .start = IRQ_CCERRINT,
629 .flags = IORESOURCE_IRQ,
631 /* not using (or muxing) TC*_ERR */
634 static struct platform_device dm355_edma_device = {
637 .dev.platform_data = dm355_edma_info,
638 .num_resources = ARRAY_SIZE(edma_resources),
639 .resource = edma_resources,
642 static struct resource dm355_asp1_resources[] = {
644 .start = DAVINCI_ASP1_BASE,
645 .end = DAVINCI_ASP1_BASE + SZ_8K - 1,
646 .flags = IORESOURCE_MEM,
649 .start = DAVINCI_DMA_ASP1_TX,
650 .end = DAVINCI_DMA_ASP1_TX,
651 .flags = IORESOURCE_DMA,
654 .start = DAVINCI_DMA_ASP1_RX,
655 .end = DAVINCI_DMA_ASP1_RX,
656 .flags = IORESOURCE_DMA,
660 static struct platform_device dm355_asp1_device = {
661 .name = "davinci-mcbsp",
663 .num_resources = ARRAY_SIZE(dm355_asp1_resources),
664 .resource = dm355_asp1_resources,
667 static void dm355_ccdc_setup_pinmux(void)
669 davinci_cfg_reg(DM355_VIN_PCLK);
670 davinci_cfg_reg(DM355_VIN_CAM_WEN);
671 davinci_cfg_reg(DM355_VIN_CAM_VD);
672 davinci_cfg_reg(DM355_VIN_CAM_HD);
673 davinci_cfg_reg(DM355_VIN_YIN_EN);
674 davinci_cfg_reg(DM355_VIN_CINL_EN);
675 davinci_cfg_reg(DM355_VIN_CINH_EN);
678 static struct resource dm355_vpss_resources[] = {
680 /* VPSS BL Base address */
683 .end = 0x01c70800 + 0xff,
684 .flags = IORESOURCE_MEM,
687 /* VPSS CLK Base address */
690 .end = 0x01c70000 + 0xf,
691 .flags = IORESOURCE_MEM,
695 static struct platform_device dm355_vpss_device = {
698 .dev.platform_data = "dm355_vpss",
699 .num_resources = ARRAY_SIZE(dm355_vpss_resources),
700 .resource = dm355_vpss_resources,
703 static struct resource vpfe_resources[] = {
707 .flags = IORESOURCE_IRQ,
712 .flags = IORESOURCE_IRQ,
716 static u64 vpfe_capture_dma_mask = DMA_BIT_MASK(32);
717 static struct resource dm355_ccdc_resource[] = {
718 /* CCDC Base address */
720 .flags = IORESOURCE_MEM,
722 .end = 0x01c70600 + 0x1ff,
725 static struct platform_device dm355_ccdc_dev = {
726 .name = "dm355_ccdc",
728 .num_resources = ARRAY_SIZE(dm355_ccdc_resource),
729 .resource = dm355_ccdc_resource,
731 .dma_mask = &vpfe_capture_dma_mask,
732 .coherent_dma_mask = DMA_BIT_MASK(32),
733 .platform_data = dm355_ccdc_setup_pinmux,
737 static struct platform_device vpfe_capture_dev = {
738 .name = CAPTURE_DRV_NAME,
740 .num_resources = ARRAY_SIZE(vpfe_resources),
741 .resource = vpfe_resources,
743 .dma_mask = &vpfe_capture_dma_mask,
744 .coherent_dma_mask = DMA_BIT_MASK(32),
748 static struct resource dm355_osd_resources[] = {
750 .start = DM355_OSD_BASE,
751 .end = DM355_OSD_BASE + 0x17f,
752 .flags = IORESOURCE_MEM,
756 static struct platform_device dm355_osd_dev = {
757 .name = DM355_VPBE_OSD_SUBDEV_NAME,
759 .num_resources = ARRAY_SIZE(dm355_osd_resources),
760 .resource = dm355_osd_resources,
762 .dma_mask = &vpfe_capture_dma_mask,
763 .coherent_dma_mask = DMA_BIT_MASK(32),
767 static struct resource dm355_venc_resources[] = {
769 .start = IRQ_VENCINT,
771 .flags = IORESOURCE_IRQ,
773 /* venc registers io space */
775 .start = DM355_VENC_BASE,
776 .end = DM355_VENC_BASE + 0x17f,
777 .flags = IORESOURCE_MEM,
779 /* VDAC config register io space */
781 .start = DAVINCI_SYSTEM_MODULE_BASE + SYSMOD_VDAC_CONFIG,
782 .end = DAVINCI_SYSTEM_MODULE_BASE + SYSMOD_VDAC_CONFIG + 3,
783 .flags = IORESOURCE_MEM,
787 static struct resource dm355_v4l2_disp_resources[] = {
789 .start = IRQ_VENCINT,
791 .flags = IORESOURCE_IRQ,
793 /* venc registers io space */
795 .start = DM355_VENC_BASE,
796 .end = DM355_VENC_BASE + 0x17f,
797 .flags = IORESOURCE_MEM,
801 static int dm355_vpbe_setup_pinmux(enum v4l2_mbus_pixelcode if_type,
805 case V4L2_MBUS_FMT_SGRBG8_1X8:
806 davinci_cfg_reg(DM355_VOUT_FIELD_G70);
808 case V4L2_MBUS_FMT_YUYV10_1X20:
810 davinci_cfg_reg(DM355_VOUT_FIELD);
812 davinci_cfg_reg(DM355_VOUT_FIELD_G70);
818 davinci_cfg_reg(DM355_VOUT_COUTL_EN);
819 davinci_cfg_reg(DM355_VOUT_COUTH_EN);
824 static int dm355_venc_setup_clock(enum vpbe_enc_timings_type type,
827 void __iomem *vpss_clk_ctrl_reg;
829 vpss_clk_ctrl_reg = DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL);
833 writel(VPSS_DACCLKEN_ENABLE | VPSS_VENCCLKEN_ENABLE,
836 case VPBE_ENC_DV_TIMINGS:
837 if (pclock > 27000000)
839 * For HD, use external clock source since we cannot
840 * support HD mode with internal clocks.
842 writel(VPSS_MUXSEL_EXTCLK_ENABLE, vpss_clk_ctrl_reg);
851 static struct platform_device dm355_vpbe_display = {
854 .num_resources = ARRAY_SIZE(dm355_v4l2_disp_resources),
855 .resource = dm355_v4l2_disp_resources,
857 .dma_mask = &vpfe_capture_dma_mask,
858 .coherent_dma_mask = DMA_BIT_MASK(32),
862 static struct venc_platform_data dm355_venc_pdata = {
863 .setup_pinmux = dm355_vpbe_setup_pinmux,
864 .setup_clock = dm355_venc_setup_clock,
867 static struct platform_device dm355_venc_dev = {
868 .name = DM355_VPBE_VENC_SUBDEV_NAME,
870 .num_resources = ARRAY_SIZE(dm355_venc_resources),
871 .resource = dm355_venc_resources,
873 .dma_mask = &vpfe_capture_dma_mask,
874 .coherent_dma_mask = DMA_BIT_MASK(32),
875 .platform_data = (void *)&dm355_venc_pdata,
879 static struct platform_device dm355_vpbe_dev = {
880 .name = "vpbe_controller",
883 .dma_mask = &vpfe_capture_dma_mask,
884 .coherent_dma_mask = DMA_BIT_MASK(32),
888 static struct resource dm355_gpio_resources[] = {
890 .start = DAVINCI_GPIO_BASE,
891 .end = DAVINCI_GPIO_BASE + SZ_4K - 1,
892 .flags = IORESOURCE_MEM,
895 .start = IRQ_DM355_GPIOBNK0,
896 .end = IRQ_DM355_GPIOBNK6,
897 .flags = IORESOURCE_IRQ,
901 static struct davinci_gpio_platform_data dm355_gpio_platform_data = {
903 .intc_irq_num = DAVINCI_N_AINTC_IRQ,
906 int __init dm355_gpio_register(void)
908 return davinci_gpio_register(dm355_gpio_resources,
909 sizeof(dm355_gpio_resources),
910 &dm355_gpio_platform_data);
912 /*----------------------------------------------------------------------*/
914 static struct map_desc dm355_io_desc[] = {
917 .pfn = __phys_to_pfn(IO_PHYS),
923 /* Contents of JTAG ID register used to identify exact cpu type */
924 static struct davinci_id dm355_ids[] = {
928 .manufacturer = 0x00f,
929 .cpu_id = DAVINCI_CPU_ID_DM355,
934 static u32 dm355_psc_bases[] = { DAVINCI_PWR_SLEEP_CNTRL_BASE };
937 * T0_BOT: Timer 0, bottom: clockevent source for hrtimers
938 * T0_TOP: Timer 0, top : clocksource for generic timekeeping
939 * T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code)
940 * T1_TOP: Timer 1, top : <unused>
942 static struct davinci_timer_info dm355_timer_info = {
943 .timers = davinci_timer_instance,
944 .clockevent_id = T0_BOT,
945 .clocksource_id = T0_TOP,
948 static struct plat_serial8250_port dm355_serial0_platform_data[] = {
950 .mapbase = DAVINCI_UART0_BASE,
952 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
961 static struct plat_serial8250_port dm355_serial1_platform_data[] = {
963 .mapbase = DAVINCI_UART1_BASE,
965 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
974 static struct plat_serial8250_port dm355_serial2_platform_data[] = {
976 .mapbase = DM355_UART2_BASE,
977 .irq = IRQ_DM355_UARTINT2,
978 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
988 struct platform_device dm355_serial_device[] = {
990 .name = "serial8250",
991 .id = PLAT8250_DEV_PLATFORM,
993 .platform_data = dm355_serial0_platform_data,
997 .name = "serial8250",
998 .id = PLAT8250_DEV_PLATFORM1,
1000 .platform_data = dm355_serial1_platform_data,
1004 .name = "serial8250",
1005 .id = PLAT8250_DEV_PLATFORM2,
1007 .platform_data = dm355_serial2_platform_data,
1014 static struct davinci_soc_info davinci_soc_info_dm355 = {
1015 .io_desc = dm355_io_desc,
1016 .io_desc_num = ARRAY_SIZE(dm355_io_desc),
1017 .jtag_id_reg = 0x01c40028,
1019 .ids_num = ARRAY_SIZE(dm355_ids),
1020 .cpu_clks = dm355_clks,
1021 .psc_bases = dm355_psc_bases,
1022 .psc_bases_num = ARRAY_SIZE(dm355_psc_bases),
1023 .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
1024 .pinmux_pins = dm355_pins,
1025 .pinmux_pins_num = ARRAY_SIZE(dm355_pins),
1026 .intc_base = DAVINCI_ARM_INTC_BASE,
1027 .intc_type = DAVINCI_INTC_TYPE_AINTC,
1028 .intc_irq_prios = dm355_default_priorities,
1029 .intc_irq_num = DAVINCI_N_AINTC_IRQ,
1030 .timer_info = &dm355_timer_info,
1031 .sram_dma = 0x00010000,
1035 void __init dm355_init_asp1(u32 evt_enable, struct snd_platform_data *pdata)
1037 /* we don't use ASP1 IRQs, or we'd need to mux them ... */
1038 if (evt_enable & ASP1_TX_EVT_EN)
1039 davinci_cfg_reg(DM355_EVT8_ASP1_TX);
1041 if (evt_enable & ASP1_RX_EVT_EN)
1042 davinci_cfg_reg(DM355_EVT9_ASP1_RX);
1044 dm355_asp1_device.dev.platform_data = pdata;
1045 platform_device_register(&dm355_asp1_device);
1048 void __init dm355_init(void)
1050 davinci_common_init(&davinci_soc_info_dm355);
1051 davinci_map_sysmod();
1054 int __init dm355_init_video(struct vpfe_config *vpfe_cfg,
1055 struct vpbe_config *vpbe_cfg)
1057 if (vpfe_cfg || vpbe_cfg)
1058 platform_device_register(&dm355_vpss_device);
1061 vpfe_capture_dev.dev.platform_data = vpfe_cfg;
1062 platform_device_register(&dm355_ccdc_dev);
1063 platform_device_register(&vpfe_capture_dev);
1067 dm355_vpbe_dev.dev.platform_data = vpbe_cfg;
1068 platform_device_register(&dm355_osd_dev);
1069 platform_device_register(&dm355_venc_dev);
1070 platform_device_register(&dm355_vpbe_dev);
1071 platform_device_register(&dm355_vpbe_display);
1077 static int __init dm355_init_devices(void)
1079 if (!cpu_is_davinci_dm355())
1082 davinci_cfg_reg(DM355_INT_EDMA_CC);
1083 platform_device_register(&dm355_edma_device);
1087 postcore_initcall(dm355_init_devices);