2 * TI DaVinci DM355 chip specific setup
4 * Author: Kevin Hilman, Deep Root Systems, LLC
6 * 2007 (c) Deep Root Systems, LLC. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
11 #include <linux/init.h>
12 #include <linux/clk.h>
13 #include <linux/serial_8250.h>
14 #include <linux/platform_device.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/gpio.h>
18 #include <linux/spi/spi.h>
20 #include <asm/mach/map.h>
22 #include <mach/dm355.h>
23 #include <mach/cputype.h>
24 #include <mach/edma.h>
27 #include <mach/irqs.h>
28 #include <mach/time.h>
29 #include <mach/serial.h>
30 #include <mach/common.h>
37 #define DM355_UART2_BASE (IO_PHYS + 0x206000)
40 * Device specific clocks
42 #define DM355_REF_FREQ 24000000 /* 24 or 36 MHz */
44 static struct pll_data pll1_data = {
46 .phys_base = DAVINCI_PLL1_BASE,
47 .flags = PLL_HAS_PREDIV | PLL_HAS_POSTDIV,
50 static struct pll_data pll2_data = {
52 .phys_base = DAVINCI_PLL2_BASE,
53 .flags = PLL_HAS_PREDIV,
56 static struct clk ref_clk = {
58 /* FIXME -- crystal rate is board-specific */
59 .rate = DM355_REF_FREQ,
62 static struct clk pll1_clk = {
66 .pll_data = &pll1_data,
69 static struct clk pll1_aux_clk = {
70 .name = "pll1_aux_clk",
72 .flags = CLK_PLL | PRE_PLL,
75 static struct clk pll1_sysclk1 = {
76 .name = "pll1_sysclk1",
82 static struct clk pll1_sysclk2 = {
83 .name = "pll1_sysclk2",
89 static struct clk pll1_sysclk3 = {
90 .name = "pll1_sysclk3",
96 static struct clk pll1_sysclk4 = {
97 .name = "pll1_sysclk4",
103 static struct clk pll1_sysclkbp = {
104 .name = "pll1_sysclkbp",
106 .flags = CLK_PLL | PRE_PLL,
110 static struct clk vpss_dac_clk = {
112 .parent = &pll1_sysclk3,
113 .lpsc = DM355_LPSC_VPSS_DAC,
116 static struct clk vpss_master_clk = {
117 .name = "vpss_master",
118 .parent = &pll1_sysclk4,
119 .lpsc = DAVINCI_LPSC_VPSSMSTR,
123 static struct clk vpss_slave_clk = {
124 .name = "vpss_slave",
125 .parent = &pll1_sysclk4,
126 .lpsc = DAVINCI_LPSC_VPSSSLV,
129 static struct clk clkout1_clk = {
131 .parent = &pll1_aux_clk,
132 /* NOTE: clkout1 can be externally gated by muxing GPIO-18 */
135 static struct clk clkout2_clk = {
137 .parent = &pll1_sysclkbp,
140 static struct clk pll2_clk = {
144 .pll_data = &pll2_data,
147 static struct clk pll2_sysclk1 = {
148 .name = "pll2_sysclk1",
154 static struct clk pll2_sysclkbp = {
155 .name = "pll2_sysclkbp",
157 .flags = CLK_PLL | PRE_PLL,
161 static struct clk clkout3_clk = {
163 .parent = &pll2_sysclkbp,
164 /* NOTE: clkout3 can be externally gated by muxing GPIO-16 */
167 static struct clk arm_clk = {
169 .parent = &pll1_sysclk1,
170 .lpsc = DAVINCI_LPSC_ARM,
171 .flags = ALWAYS_ENABLED,
175 * NOT LISTED below, and not touched by Linux
176 * - in SyncReset state by default
177 * .lpsc = DAVINCI_LPSC_TPCC,
178 * .lpsc = DAVINCI_LPSC_TPTC0,
179 * .lpsc = DAVINCI_LPSC_TPTC1,
180 * .lpsc = DAVINCI_LPSC_DDR_EMIF, .parent = &sysclk2_clk,
181 * .lpsc = DAVINCI_LPSC_MEMSTICK,
182 * - in Enabled state by default
183 * .lpsc = DAVINCI_LPSC_SYSTEM_SUBSYS,
184 * .lpsc = DAVINCI_LPSC_SCR2, // "bus"
185 * .lpsc = DAVINCI_LPSC_SCR3, // "bus"
186 * .lpsc = DAVINCI_LPSC_SCR4, // "bus"
187 * .lpsc = DAVINCI_LPSC_CROSSBAR, // "emulation"
188 * .lpsc = DAVINCI_LPSC_CFG27, // "test"
189 * .lpsc = DAVINCI_LPSC_CFG3, // "test"
190 * .lpsc = DAVINCI_LPSC_CFG5, // "test"
193 static struct clk mjcp_clk = {
195 .parent = &pll1_sysclk1,
196 .lpsc = DAVINCI_LPSC_IMCOP,
199 static struct clk uart0_clk = {
201 .parent = &pll1_aux_clk,
202 .lpsc = DAVINCI_LPSC_UART0,
205 static struct clk uart1_clk = {
207 .parent = &pll1_aux_clk,
208 .lpsc = DAVINCI_LPSC_UART1,
211 static struct clk uart2_clk = {
213 .parent = &pll1_sysclk2,
214 .lpsc = DAVINCI_LPSC_UART2,
217 static struct clk i2c_clk = {
219 .parent = &pll1_aux_clk,
220 .lpsc = DAVINCI_LPSC_I2C,
223 static struct clk asp0_clk = {
225 .parent = &pll1_sysclk2,
226 .lpsc = DAVINCI_LPSC_McBSP,
229 static struct clk asp1_clk = {
231 .parent = &pll1_sysclk2,
232 .lpsc = DM355_LPSC_McBSP1,
235 static struct clk mmcsd0_clk = {
237 .parent = &pll1_sysclk2,
238 .lpsc = DAVINCI_LPSC_MMC_SD,
241 static struct clk mmcsd1_clk = {
243 .parent = &pll1_sysclk2,
244 .lpsc = DM355_LPSC_MMC_SD1,
247 static struct clk spi0_clk = {
249 .parent = &pll1_sysclk2,
250 .lpsc = DAVINCI_LPSC_SPI,
253 static struct clk spi1_clk = {
255 .parent = &pll1_sysclk2,
256 .lpsc = DM355_LPSC_SPI1,
259 static struct clk spi2_clk = {
261 .parent = &pll1_sysclk2,
262 .lpsc = DM355_LPSC_SPI2,
265 static struct clk gpio_clk = {
267 .parent = &pll1_sysclk2,
268 .lpsc = DAVINCI_LPSC_GPIO,
271 static struct clk aemif_clk = {
273 .parent = &pll1_sysclk2,
274 .lpsc = DAVINCI_LPSC_AEMIF,
277 static struct clk pwm0_clk = {
279 .parent = &pll1_aux_clk,
280 .lpsc = DAVINCI_LPSC_PWM0,
283 static struct clk pwm1_clk = {
285 .parent = &pll1_aux_clk,
286 .lpsc = DAVINCI_LPSC_PWM1,
289 static struct clk pwm2_clk = {
291 .parent = &pll1_aux_clk,
292 .lpsc = DAVINCI_LPSC_PWM2,
295 static struct clk pwm3_clk = {
297 .parent = &pll1_aux_clk,
298 .lpsc = DM355_LPSC_PWM3,
301 static struct clk timer0_clk = {
303 .parent = &pll1_aux_clk,
304 .lpsc = DAVINCI_LPSC_TIMER0,
307 static struct clk timer1_clk = {
309 .parent = &pll1_aux_clk,
310 .lpsc = DAVINCI_LPSC_TIMER1,
313 static struct clk timer2_clk = {
315 .parent = &pll1_aux_clk,
316 .lpsc = DAVINCI_LPSC_TIMER2,
317 .usecount = 1, /* REVISIT: why cant' this be disabled? */
320 static struct clk timer3_clk = {
322 .parent = &pll1_aux_clk,
323 .lpsc = DM355_LPSC_TIMER3,
326 static struct clk rto_clk = {
328 .parent = &pll1_aux_clk,
329 .lpsc = DM355_LPSC_RTO,
332 static struct clk usb_clk = {
334 .parent = &pll1_sysclk2,
335 .lpsc = DAVINCI_LPSC_USB,
338 static struct clk_lookup dm355_clks[] = {
339 CLK(NULL, "ref", &ref_clk),
340 CLK(NULL, "pll1", &pll1_clk),
341 CLK(NULL, "pll1_sysclk1", &pll1_sysclk1),
342 CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
343 CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
344 CLK(NULL, "pll1_sysclk4", &pll1_sysclk4),
345 CLK(NULL, "pll1_aux", &pll1_aux_clk),
346 CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp),
347 CLK(NULL, "vpss_dac", &vpss_dac_clk),
348 CLK(NULL, "vpss_master", &vpss_master_clk),
349 CLK(NULL, "vpss_slave", &vpss_slave_clk),
350 CLK(NULL, "clkout1", &clkout1_clk),
351 CLK(NULL, "clkout2", &clkout2_clk),
352 CLK(NULL, "pll2", &pll2_clk),
353 CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
354 CLK(NULL, "pll2_sysclkbp", &pll2_sysclkbp),
355 CLK(NULL, "clkout3", &clkout3_clk),
356 CLK(NULL, "arm", &arm_clk),
357 CLK(NULL, "mjcp", &mjcp_clk),
358 CLK(NULL, "uart0", &uart0_clk),
359 CLK(NULL, "uart1", &uart1_clk),
360 CLK(NULL, "uart2", &uart2_clk),
361 CLK("i2c_davinci.1", NULL, &i2c_clk),
362 CLK("davinci-asp.0", NULL, &asp0_clk),
363 CLK("davinci-asp.1", NULL, &asp1_clk),
364 CLK("davinci_mmc.0", NULL, &mmcsd0_clk),
365 CLK("davinci_mmc.1", NULL, &mmcsd1_clk),
366 CLK("spi_davinci.0", NULL, &spi0_clk),
367 CLK("spi_davinci.1", NULL, &spi1_clk),
368 CLK("spi_davinci.2", NULL, &spi2_clk),
369 CLK(NULL, "gpio", &gpio_clk),
370 CLK(NULL, "aemif", &aemif_clk),
371 CLK(NULL, "pwm0", &pwm0_clk),
372 CLK(NULL, "pwm1", &pwm1_clk),
373 CLK(NULL, "pwm2", &pwm2_clk),
374 CLK(NULL, "pwm3", &pwm3_clk),
375 CLK(NULL, "timer0", &timer0_clk),
376 CLK(NULL, "timer1", &timer1_clk),
377 CLK("watchdog", NULL, &timer2_clk),
378 CLK(NULL, "timer3", &timer3_clk),
379 CLK(NULL, "rto", &rto_clk),
380 CLK(NULL, "usb", &usb_clk),
381 CLK(NULL, NULL, NULL),
384 /*----------------------------------------------------------------------*/
386 static u64 dm355_spi0_dma_mask = DMA_BIT_MASK(32);
388 static struct resource dm355_spi0_resources[] = {
392 .flags = IORESOURCE_MEM,
395 .start = IRQ_DM355_SPINT0_0,
396 .flags = IORESOURCE_IRQ,
400 .flags = IORESOURCE_DMA,
404 .flags = IORESOURCE_DMA,
408 .flags = IORESOURCE_DMA,
412 static struct davinci_spi_platform_data dm355_spi0_pdata = {
413 .version = SPI_VERSION_1,
418 .poll_mode = 1, /* 0 -> interrupt mode 1-> polling mode */
422 static struct platform_device dm355_spi0_device = {
423 .name = "spi_davinci",
426 .dma_mask = &dm355_spi0_dma_mask,
427 .coherent_dma_mask = DMA_BIT_MASK(32),
428 .platform_data = &dm355_spi0_pdata,
430 .num_resources = ARRAY_SIZE(dm355_spi0_resources),
431 .resource = dm355_spi0_resources,
434 void __init dm355_init_spi0(unsigned chipselect_mask,
435 struct spi_board_info *info, unsigned len)
437 /* for now, assume we need MISO */
438 davinci_cfg_reg(DM355_SPI0_SDI);
440 /* not all slaves will be wired up */
441 if (chipselect_mask & BIT(0))
442 davinci_cfg_reg(DM355_SPI0_SDENA0);
443 if (chipselect_mask & BIT(1))
444 davinci_cfg_reg(DM355_SPI0_SDENA1);
446 spi_register_board_info(info, len);
448 platform_device_register(&dm355_spi0_device);
451 /*----------------------------------------------------------------------*/
462 * Device specific mux setup
464 * soc description mux mode mode mux dbg
465 * reg offset mask mode
467 static const struct mux_config dm355_pins[] = {
468 #ifdef CONFIG_DAVINCI_MUX
469 MUX_CFG(DM355, MMCSD0, 4, 2, 1, 0, false)
471 MUX_CFG(DM355, SD1_CLK, 3, 6, 1, 1, false)
472 MUX_CFG(DM355, SD1_CMD, 3, 7, 1, 1, false)
473 MUX_CFG(DM355, SD1_DATA3, 3, 8, 3, 1, false)
474 MUX_CFG(DM355, SD1_DATA2, 3, 10, 3, 1, false)
475 MUX_CFG(DM355, SD1_DATA1, 3, 12, 3, 1, false)
476 MUX_CFG(DM355, SD1_DATA0, 3, 14, 3, 1, false)
478 MUX_CFG(DM355, I2C_SDA, 3, 19, 1, 1, false)
479 MUX_CFG(DM355, I2C_SCL, 3, 20, 1, 1, false)
481 MUX_CFG(DM355, MCBSP0_BDX, 3, 0, 1, 1, false)
482 MUX_CFG(DM355, MCBSP0_X, 3, 1, 1, 1, false)
483 MUX_CFG(DM355, MCBSP0_BFSX, 3, 2, 1, 1, false)
484 MUX_CFG(DM355, MCBSP0_BDR, 3, 3, 1, 1, false)
485 MUX_CFG(DM355, MCBSP0_R, 3, 4, 1, 1, false)
486 MUX_CFG(DM355, MCBSP0_BFSR, 3, 5, 1, 1, false)
488 MUX_CFG(DM355, SPI0_SDI, 4, 1, 1, 0, false)
489 MUX_CFG(DM355, SPI0_SDENA0, 4, 0, 1, 0, false)
490 MUX_CFG(DM355, SPI0_SDENA1, 3, 28, 1, 1, false)
492 INT_CFG(DM355, INT_EDMA_CC, 2, 1, 1, false)
493 INT_CFG(DM355, INT_EDMA_TC0_ERR, 3, 1, 1, false)
494 INT_CFG(DM355, INT_EDMA_TC1_ERR, 4, 1, 1, false)
496 EVT_CFG(DM355, EVT8_ASP1_TX, 0, 1, 0, false)
497 EVT_CFG(DM355, EVT9_ASP1_RX, 1, 1, 0, false)
498 EVT_CFG(DM355, EVT26_MMC0_RX, 2, 1, 0, false)
500 MUX_CFG(DM355, VOUT_FIELD, 1, 18, 3, 1, false)
501 MUX_CFG(DM355, VOUT_FIELD_G70, 1, 18, 3, 0, false)
502 MUX_CFG(DM355, VOUT_HVSYNC, 1, 16, 1, 0, false)
503 MUX_CFG(DM355, VOUT_COUTL_EN, 1, 0, 0xff, 0x55, false)
504 MUX_CFG(DM355, VOUT_COUTH_EN, 1, 8, 0xff, 0x55, false)
506 MUX_CFG(DM355, VIN_PCLK, 0, 14, 1, 1, false)
507 MUX_CFG(DM355, VIN_CAM_WEN, 0, 13, 1, 1, false)
508 MUX_CFG(DM355, VIN_CAM_VD, 0, 12, 1, 1, false)
509 MUX_CFG(DM355, VIN_CAM_HD, 0, 11, 1, 1, false)
510 MUX_CFG(DM355, VIN_YIN_EN, 0, 10, 1, 1, false)
511 MUX_CFG(DM355, VIN_CINL_EN, 0, 0, 0xff, 0x55, false)
512 MUX_CFG(DM355, VIN_CINH_EN, 0, 8, 3, 3, false)
516 static u8 dm355_default_priorities[DAVINCI_N_AINTC_IRQ] = {
517 [IRQ_DM355_CCDC_VDINT0] = 2,
518 [IRQ_DM355_CCDC_VDINT1] = 6,
519 [IRQ_DM355_CCDC_VDINT2] = 6,
520 [IRQ_DM355_IPIPE_HST] = 6,
521 [IRQ_DM355_H3AINT] = 6,
522 [IRQ_DM355_IPIPE_SDR] = 6,
523 [IRQ_DM355_IPIPEIFINT] = 6,
524 [IRQ_DM355_OSDINT] = 7,
525 [IRQ_DM355_VENCINT] = 6,
529 [IRQ_DM355_RTOINT] = 4,
530 [IRQ_DM355_UARTINT2] = 7,
531 [IRQ_DM355_TINT6] = 7,
532 [IRQ_CCINT0] = 5, /* dma */
533 [IRQ_CCERRINT] = 5, /* dma */
534 [IRQ_TCERRINT0] = 5, /* dma */
535 [IRQ_TCERRINT] = 5, /* dma */
536 [IRQ_DM355_SPINT2_1] = 7,
537 [IRQ_DM355_TINT7] = 4,
538 [IRQ_DM355_SDIOINT0] = 7,
542 [IRQ_DM355_MMCINT1] = 7,
543 [IRQ_DM355_PWMINT3] = 7,
546 [IRQ_DM355_SDIOINT1] = 4,
547 [IRQ_TINT0_TINT12] = 2, /* clockevent */
548 [IRQ_TINT0_TINT34] = 2, /* clocksource */
549 [IRQ_TINT1_TINT12] = 7, /* DSP timer */
550 [IRQ_TINT1_TINT34] = 7, /* system tick */
557 [IRQ_DM355_SPINT0_0] = 3,
558 [IRQ_DM355_SPINT0_1] = 3,
559 [IRQ_DM355_GPIO0] = 3,
560 [IRQ_DM355_GPIO1] = 7,
561 [IRQ_DM355_GPIO2] = 4,
562 [IRQ_DM355_GPIO3] = 4,
563 [IRQ_DM355_GPIO4] = 7,
564 [IRQ_DM355_GPIO5] = 7,
565 [IRQ_DM355_GPIO6] = 7,
566 [IRQ_DM355_GPIO7] = 7,
567 [IRQ_DM355_GPIO8] = 7,
568 [IRQ_DM355_GPIO9] = 7,
569 [IRQ_DM355_GPIOBNK0] = 7,
570 [IRQ_DM355_GPIOBNK1] = 7,
571 [IRQ_DM355_GPIOBNK2] = 7,
572 [IRQ_DM355_GPIOBNK3] = 7,
573 [IRQ_DM355_GPIOBNK4] = 7,
574 [IRQ_DM355_GPIOBNK5] = 7,
575 [IRQ_DM355_GPIOBNK6] = 7,
581 /*----------------------------------------------------------------------*/
584 queue_tc_mapping[][2] = {
585 /* {event queue no, TC no} */
592 queue_priority_mapping[][2] = {
593 /* {event queue no, Priority} */
599 static struct edma_soc_info dm355_edma_info[] = {
606 .queue_tc_mapping = queue_tc_mapping,
607 .queue_priority_mapping = queue_priority_mapping,
611 static struct resource edma_resources[] = {
615 .end = 0x01c00000 + SZ_64K - 1,
616 .flags = IORESOURCE_MEM,
621 .end = 0x01c10000 + SZ_1K - 1,
622 .flags = IORESOURCE_MEM,
627 .end = 0x01c10400 + SZ_1K - 1,
628 .flags = IORESOURCE_MEM,
633 .flags = IORESOURCE_IRQ,
637 .start = IRQ_CCERRINT,
638 .flags = IORESOURCE_IRQ,
640 /* not using (or muxing) TC*_ERR */
643 static struct platform_device dm355_edma_device = {
646 .dev.platform_data = dm355_edma_info,
647 .num_resources = ARRAY_SIZE(edma_resources),
648 .resource = edma_resources,
651 static struct resource dm355_asp1_resources[] = {
653 .start = DAVINCI_ASP1_BASE,
654 .end = DAVINCI_ASP1_BASE + SZ_8K - 1,
655 .flags = IORESOURCE_MEM,
658 .start = DAVINCI_DMA_ASP1_TX,
659 .end = DAVINCI_DMA_ASP1_TX,
660 .flags = IORESOURCE_DMA,
663 .start = DAVINCI_DMA_ASP1_RX,
664 .end = DAVINCI_DMA_ASP1_RX,
665 .flags = IORESOURCE_DMA,
669 static struct platform_device dm355_asp1_device = {
670 .name = "davinci-asp",
672 .num_resources = ARRAY_SIZE(dm355_asp1_resources),
673 .resource = dm355_asp1_resources,
676 static void dm355_ccdc_setup_pinmux(void)
678 davinci_cfg_reg(DM355_VIN_PCLK);
679 davinci_cfg_reg(DM355_VIN_CAM_WEN);
680 davinci_cfg_reg(DM355_VIN_CAM_VD);
681 davinci_cfg_reg(DM355_VIN_CAM_HD);
682 davinci_cfg_reg(DM355_VIN_YIN_EN);
683 davinci_cfg_reg(DM355_VIN_CINL_EN);
684 davinci_cfg_reg(DM355_VIN_CINH_EN);
687 static struct resource dm355_vpss_resources[] = {
689 /* VPSS BL Base address */
692 .end = 0x01c70800 + 0xff,
693 .flags = IORESOURCE_MEM,
696 /* VPSS CLK Base address */
699 .end = 0x01c70000 + 0xf,
700 .flags = IORESOURCE_MEM,
704 static struct platform_device dm355_vpss_device = {
707 .dev.platform_data = "dm355_vpss",
708 .num_resources = ARRAY_SIZE(dm355_vpss_resources),
709 .resource = dm355_vpss_resources,
712 static struct resource vpfe_resources[] = {
716 .flags = IORESOURCE_IRQ,
721 .flags = IORESOURCE_IRQ,
725 static u64 vpfe_capture_dma_mask = DMA_BIT_MASK(32);
726 static struct resource dm355_ccdc_resource[] = {
727 /* CCDC Base address */
729 .flags = IORESOURCE_MEM,
731 .end = 0x01c70600 + 0x1ff,
734 static struct platform_device dm355_ccdc_dev = {
735 .name = "dm355_ccdc",
737 .num_resources = ARRAY_SIZE(dm355_ccdc_resource),
738 .resource = dm355_ccdc_resource,
740 .dma_mask = &vpfe_capture_dma_mask,
741 .coherent_dma_mask = DMA_BIT_MASK(32),
742 .platform_data = dm355_ccdc_setup_pinmux,
746 static struct platform_device vpfe_capture_dev = {
747 .name = CAPTURE_DRV_NAME,
749 .num_resources = ARRAY_SIZE(vpfe_resources),
750 .resource = vpfe_resources,
752 .dma_mask = &vpfe_capture_dma_mask,
753 .coherent_dma_mask = DMA_BIT_MASK(32),
757 void dm355_set_vpfe_config(struct vpfe_config *cfg)
759 vpfe_capture_dev.dev.platform_data = cfg;
762 /*----------------------------------------------------------------------*/
764 static struct map_desc dm355_io_desc[] = {
767 .pfn = __phys_to_pfn(IO_PHYS),
772 .virtual = SRAM_VIRT,
773 .pfn = __phys_to_pfn(0x00010000),
775 /* MT_MEMORY_NONCACHED requires supersection alignment */
780 /* Contents of JTAG ID register used to identify exact cpu type */
781 static struct davinci_id dm355_ids[] = {
785 .manufacturer = 0x00f,
786 .cpu_id = DAVINCI_CPU_ID_DM355,
791 static void __iomem *dm355_psc_bases[] = {
792 IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE),
796 * T0_BOT: Timer 0, bottom: clockevent source for hrtimers
797 * T0_TOP: Timer 0, top : clocksource for generic timekeeping
798 * T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code)
799 * T1_TOP: Timer 1, top : <unused>
801 struct davinci_timer_info dm355_timer_info = {
802 .timers = davinci_timer_instance,
803 .clockevent_id = T0_BOT,
804 .clocksource_id = T0_TOP,
807 static struct plat_serial8250_port dm355_serial_platform_data[] = {
809 .mapbase = DAVINCI_UART0_BASE,
811 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
817 .mapbase = DAVINCI_UART1_BASE,
819 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
825 .mapbase = DM355_UART2_BASE,
826 .irq = IRQ_DM355_UARTINT2,
827 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
837 static struct platform_device dm355_serial_device = {
838 .name = "serial8250",
839 .id = PLAT8250_DEV_PLATFORM,
841 .platform_data = dm355_serial_platform_data,
845 static struct davinci_soc_info davinci_soc_info_dm355 = {
846 .io_desc = dm355_io_desc,
847 .io_desc_num = ARRAY_SIZE(dm355_io_desc),
848 .jtag_id_base = IO_ADDRESS(0x01c40028),
850 .ids_num = ARRAY_SIZE(dm355_ids),
851 .cpu_clks = dm355_clks,
852 .psc_bases = dm355_psc_bases,
853 .psc_bases_num = ARRAY_SIZE(dm355_psc_bases),
854 .pinmux_base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE),
855 .pinmux_pins = dm355_pins,
856 .pinmux_pins_num = ARRAY_SIZE(dm355_pins),
857 .intc_base = IO_ADDRESS(DAVINCI_ARM_INTC_BASE),
858 .intc_type = DAVINCI_INTC_TYPE_AINTC,
859 .intc_irq_prios = dm355_default_priorities,
860 .intc_irq_num = DAVINCI_N_AINTC_IRQ,
861 .timer_info = &dm355_timer_info,
862 .gpio_base = IO_ADDRESS(DAVINCI_GPIO_BASE),
864 .gpio_irq = IRQ_DM355_GPIOBNK0,
865 .serial_dev = &dm355_serial_device,
866 .sram_dma = 0x00010000,
870 void __init dm355_init_asp1(u32 evt_enable, struct snd_platform_data *pdata)
872 /* we don't use ASP1 IRQs, or we'd need to mux them ... */
873 if (evt_enable & ASP1_TX_EVT_EN)
874 davinci_cfg_reg(DM355_EVT8_ASP1_TX);
876 if (evt_enable & ASP1_RX_EVT_EN)
877 davinci_cfg_reg(DM355_EVT9_ASP1_RX);
879 dm355_asp1_device.dev.platform_data = pdata;
880 platform_device_register(&dm355_asp1_device);
883 void __init dm355_init(void)
885 davinci_common_init(&davinci_soc_info_dm355);
888 static int __init dm355_init_devices(void)
890 if (!cpu_is_davinci_dm355())
893 /* Add ccdc clock aliases */
894 clk_add_alias("master", dm355_ccdc_dev.name, "vpss_master", NULL);
895 clk_add_alias("slave", dm355_ccdc_dev.name, "vpss_master", NULL);
896 davinci_cfg_reg(DM355_INT_EDMA_CC);
897 platform_device_register(&dm355_edma_device);
898 platform_device_register(&dm355_vpss_device);
899 platform_device_register(&dm355_ccdc_dev);
900 platform_device_register(&vpfe_capture_dev);
904 postcore_initcall(dm355_init_devices);