2 * TI DaVinci DM365 chip specific setup
4 * Copyright (C) 2009 Texas Instruments
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 #include <linux/init.h>
16 #include <linux/clk.h>
17 #include <linux/serial_8250.h>
18 #include <linux/platform_device.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/spi/spi.h>
21 #include <linux/platform_data/edma.h>
22 #include <linux/platform_data/gpio-davinci.h>
23 #include <linux/platform_data/keyscan-davinci.h>
24 #include <linux/platform_data/spi-davinci.h>
26 #include <asm/mach/map.h>
28 #include <mach/cputype.h>
31 #include <mach/irqs.h>
32 #include <mach/time.h>
33 #include <mach/serial.h>
34 #include <mach/common.h>
41 #define DM365_REF_FREQ 24000000 /* 24 MHz on the DM365 EVM */
42 #define DM365_RTC_BASE 0x01c69000
43 #define DM365_KEYSCAN_BASE 0x01c69400
44 #define DM365_OSD_BASE 0x01c71c00
45 #define DM365_VENC_BASE 0x01c71e00
46 #define DAVINCI_DM365_VC_BASE 0x01d0c000
47 #define DAVINCI_DMA_VC_TX 2
48 #define DAVINCI_DMA_VC_RX 3
49 #define DM365_EMAC_BASE 0x01d07000
50 #define DM365_EMAC_MDIO_BASE (DM365_EMAC_BASE + 0x4000)
51 #define DM365_EMAC_CNTRL_OFFSET 0x0000
52 #define DM365_EMAC_CNTRL_MOD_OFFSET 0x3000
53 #define DM365_EMAC_CNTRL_RAM_OFFSET 0x1000
54 #define DM365_EMAC_CNTRL_RAM_SIZE 0x2000
56 static struct pll_data pll1_data = {
58 .phys_base = DAVINCI_PLL1_BASE,
59 .flags = PLL_HAS_POSTDIV | PLL_HAS_PREDIV,
62 static struct pll_data pll2_data = {
64 .phys_base = DAVINCI_PLL2_BASE,
65 .flags = PLL_HAS_POSTDIV | PLL_HAS_PREDIV,
68 static struct clk ref_clk = {
70 .rate = DM365_REF_FREQ,
73 static struct clk pll1_clk = {
77 .pll_data = &pll1_data,
80 static struct clk pll1_aux_clk = {
81 .name = "pll1_aux_clk",
83 .flags = CLK_PLL | PRE_PLL,
86 static struct clk pll1_sysclkbp = {
87 .name = "pll1_sysclkbp",
89 .flags = CLK_PLL | PRE_PLL,
93 static struct clk clkout0_clk = {
96 .flags = CLK_PLL | PRE_PLL,
99 static struct clk pll1_sysclk1 = {
100 .name = "pll1_sysclk1",
106 static struct clk pll1_sysclk2 = {
107 .name = "pll1_sysclk2",
113 static struct clk pll1_sysclk3 = {
114 .name = "pll1_sysclk3",
120 static struct clk pll1_sysclk4 = {
121 .name = "pll1_sysclk4",
127 static struct clk pll1_sysclk5 = {
128 .name = "pll1_sysclk5",
134 static struct clk pll1_sysclk6 = {
135 .name = "pll1_sysclk6",
141 static struct clk pll1_sysclk7 = {
142 .name = "pll1_sysclk7",
148 static struct clk pll1_sysclk8 = {
149 .name = "pll1_sysclk8",
155 static struct clk pll1_sysclk9 = {
156 .name = "pll1_sysclk9",
162 static struct clk pll2_clk = {
166 .pll_data = &pll2_data,
169 static struct clk pll2_aux_clk = {
170 .name = "pll2_aux_clk",
172 .flags = CLK_PLL | PRE_PLL,
175 static struct clk clkout1_clk = {
178 .flags = CLK_PLL | PRE_PLL,
181 static struct clk pll2_sysclk1 = {
182 .name = "pll2_sysclk1",
188 static struct clk pll2_sysclk2 = {
189 .name = "pll2_sysclk2",
195 static struct clk pll2_sysclk3 = {
196 .name = "pll2_sysclk3",
202 static struct clk pll2_sysclk4 = {
203 .name = "pll2_sysclk4",
209 static struct clk pll2_sysclk5 = {
210 .name = "pll2_sysclk5",
216 static struct clk pll2_sysclk6 = {
217 .name = "pll2_sysclk6",
223 static struct clk pll2_sysclk7 = {
224 .name = "pll2_sysclk7",
230 static struct clk pll2_sysclk8 = {
231 .name = "pll2_sysclk8",
237 static struct clk pll2_sysclk9 = {
238 .name = "pll2_sysclk9",
244 static struct clk vpss_dac_clk = {
246 .parent = &pll1_sysclk3,
247 .lpsc = DM365_LPSC_DAC_CLK,
250 static struct clk vpss_master_clk = {
251 .name = "vpss_master",
252 .parent = &pll1_sysclk5,
253 .lpsc = DM365_LPSC_VPSSMSTR,
257 static struct clk vpss_slave_clk = {
258 .name = "vpss_slave",
259 .parent = &pll1_sysclk5,
260 .lpsc = DAVINCI_LPSC_VPSSSLV,
263 static struct clk arm_clk = {
265 .parent = &pll2_sysclk2,
266 .lpsc = DAVINCI_LPSC_ARM,
267 .flags = ALWAYS_ENABLED,
270 static struct clk uart0_clk = {
272 .parent = &pll1_aux_clk,
273 .lpsc = DAVINCI_LPSC_UART0,
276 static struct clk uart1_clk = {
278 .parent = &pll1_sysclk4,
279 .lpsc = DAVINCI_LPSC_UART1,
282 static struct clk i2c_clk = {
284 .parent = &pll1_aux_clk,
285 .lpsc = DAVINCI_LPSC_I2C,
288 static struct clk mmcsd0_clk = {
290 .parent = &pll1_sysclk8,
291 .lpsc = DAVINCI_LPSC_MMC_SD,
294 static struct clk mmcsd1_clk = {
296 .parent = &pll1_sysclk4,
297 .lpsc = DM365_LPSC_MMC_SD1,
300 static struct clk spi0_clk = {
302 .parent = &pll1_sysclk4,
303 .lpsc = DAVINCI_LPSC_SPI,
306 static struct clk spi1_clk = {
308 .parent = &pll1_sysclk4,
309 .lpsc = DM365_LPSC_SPI1,
312 static struct clk spi2_clk = {
314 .parent = &pll1_sysclk4,
315 .lpsc = DM365_LPSC_SPI2,
318 static struct clk spi3_clk = {
320 .parent = &pll1_sysclk4,
321 .lpsc = DM365_LPSC_SPI3,
324 static struct clk spi4_clk = {
326 .parent = &pll1_aux_clk,
327 .lpsc = DM365_LPSC_SPI4,
330 static struct clk gpio_clk = {
332 .parent = &pll1_sysclk4,
333 .lpsc = DAVINCI_LPSC_GPIO,
336 static struct clk aemif_clk = {
338 .parent = &pll1_sysclk4,
339 .lpsc = DAVINCI_LPSC_AEMIF,
342 static struct clk pwm0_clk = {
344 .parent = &pll1_aux_clk,
345 .lpsc = DAVINCI_LPSC_PWM0,
348 static struct clk pwm1_clk = {
350 .parent = &pll1_aux_clk,
351 .lpsc = DAVINCI_LPSC_PWM1,
354 static struct clk pwm2_clk = {
356 .parent = &pll1_aux_clk,
357 .lpsc = DAVINCI_LPSC_PWM2,
360 static struct clk pwm3_clk = {
363 .lpsc = DM365_LPSC_PWM3,
366 static struct clk timer0_clk = {
368 .parent = &pll1_aux_clk,
369 .lpsc = DAVINCI_LPSC_TIMER0,
372 static struct clk timer1_clk = {
374 .parent = &pll1_aux_clk,
375 .lpsc = DAVINCI_LPSC_TIMER1,
378 static struct clk timer2_clk = {
380 .parent = &pll1_aux_clk,
381 .lpsc = DAVINCI_LPSC_TIMER2,
385 static struct clk timer3_clk = {
387 .parent = &pll1_aux_clk,
388 .lpsc = DM365_LPSC_TIMER3,
391 static struct clk usb_clk = {
393 .parent = &pll1_aux_clk,
394 .lpsc = DAVINCI_LPSC_USB,
397 static struct clk emac_clk = {
399 .parent = &pll1_sysclk4,
400 .lpsc = DM365_LPSC_EMAC,
403 static struct clk voicecodec_clk = {
404 .name = "voice_codec",
405 .parent = &pll2_sysclk4,
406 .lpsc = DM365_LPSC_VOICE_CODEC,
409 static struct clk asp0_clk = {
411 .parent = &pll1_sysclk4,
412 .lpsc = DM365_LPSC_McBSP1,
415 static struct clk rto_clk = {
417 .parent = &pll1_sysclk4,
418 .lpsc = DM365_LPSC_RTO,
421 static struct clk mjcp_clk = {
423 .parent = &pll1_sysclk3,
424 .lpsc = DM365_LPSC_MJCP,
427 static struct clk_lookup dm365_clks[] = {
428 CLK(NULL, "ref", &ref_clk),
429 CLK(NULL, "pll1", &pll1_clk),
430 CLK(NULL, "pll1_aux", &pll1_aux_clk),
431 CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp),
432 CLK(NULL, "clkout0", &clkout0_clk),
433 CLK(NULL, "pll1_sysclk1", &pll1_sysclk1),
434 CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
435 CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
436 CLK(NULL, "pll1_sysclk4", &pll1_sysclk4),
437 CLK(NULL, "pll1_sysclk5", &pll1_sysclk5),
438 CLK(NULL, "pll1_sysclk6", &pll1_sysclk6),
439 CLK(NULL, "pll1_sysclk7", &pll1_sysclk7),
440 CLK(NULL, "pll1_sysclk8", &pll1_sysclk8),
441 CLK(NULL, "pll1_sysclk9", &pll1_sysclk9),
442 CLK(NULL, "pll2", &pll2_clk),
443 CLK(NULL, "pll2_aux", &pll2_aux_clk),
444 CLK(NULL, "clkout1", &clkout1_clk),
445 CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
446 CLK(NULL, "pll2_sysclk2", &pll2_sysclk2),
447 CLK(NULL, "pll2_sysclk3", &pll2_sysclk3),
448 CLK(NULL, "pll2_sysclk4", &pll2_sysclk4),
449 CLK(NULL, "pll2_sysclk5", &pll2_sysclk5),
450 CLK(NULL, "pll2_sysclk6", &pll2_sysclk6),
451 CLK(NULL, "pll2_sysclk7", &pll2_sysclk7),
452 CLK(NULL, "pll2_sysclk8", &pll2_sysclk8),
453 CLK(NULL, "pll2_sysclk9", &pll2_sysclk9),
454 CLK(NULL, "vpss_dac", &vpss_dac_clk),
455 CLK("vpss", "master", &vpss_master_clk),
456 CLK("vpss", "slave", &vpss_slave_clk),
457 CLK(NULL, "arm", &arm_clk),
458 CLK("serial8250.0", NULL, &uart0_clk),
459 CLK("serial8250.1", NULL, &uart1_clk),
460 CLK("i2c_davinci.1", NULL, &i2c_clk),
461 CLK("da830-mmc.0", NULL, &mmcsd0_clk),
462 CLK("da830-mmc.1", NULL, &mmcsd1_clk),
463 CLK("spi_davinci.0", NULL, &spi0_clk),
464 CLK("spi_davinci.1", NULL, &spi1_clk),
465 CLK("spi_davinci.2", NULL, &spi2_clk),
466 CLK("spi_davinci.3", NULL, &spi3_clk),
467 CLK("spi_davinci.4", NULL, &spi4_clk),
468 CLK(NULL, "gpio", &gpio_clk),
469 CLK(NULL, "aemif", &aemif_clk),
470 CLK(NULL, "pwm0", &pwm0_clk),
471 CLK(NULL, "pwm1", &pwm1_clk),
472 CLK(NULL, "pwm2", &pwm2_clk),
473 CLK(NULL, "pwm3", &pwm3_clk),
474 CLK(NULL, "timer0", &timer0_clk),
475 CLK(NULL, "timer1", &timer1_clk),
476 CLK("davinci-wdt", NULL, &timer2_clk),
477 CLK(NULL, "timer3", &timer3_clk),
478 CLK(NULL, "usb", &usb_clk),
479 CLK("davinci_emac.1", NULL, &emac_clk),
480 CLK("davinci_mdio.0", "fck", &emac_clk),
481 CLK("davinci_voicecodec", NULL, &voicecodec_clk),
482 CLK("davinci-mcbsp", NULL, &asp0_clk),
483 CLK(NULL, "rto", &rto_clk),
484 CLK(NULL, "mjcp", &mjcp_clk),
485 CLK(NULL, NULL, NULL),
488 /*----------------------------------------------------------------------*/
494 static const struct mux_config dm365_pins[] = {
495 #ifdef CONFIG_DAVINCI_MUX
496 MUX_CFG(DM365, MMCSD0, 0, 24, 1, 0, false)
498 MUX_CFG(DM365, SD1_CLK, 0, 16, 3, 1, false)
499 MUX_CFG(DM365, SD1_CMD, 4, 30, 3, 1, false)
500 MUX_CFG(DM365, SD1_DATA3, 4, 28, 3, 1, false)
501 MUX_CFG(DM365, SD1_DATA2, 4, 26, 3, 1, false)
502 MUX_CFG(DM365, SD1_DATA1, 4, 24, 3, 1, false)
503 MUX_CFG(DM365, SD1_DATA0, 4, 22, 3, 1, false)
505 MUX_CFG(DM365, I2C_SDA, 3, 23, 3, 2, false)
506 MUX_CFG(DM365, I2C_SCL, 3, 21, 3, 2, false)
508 MUX_CFG(DM365, AEMIF_AR_A14, 2, 0, 3, 1, false)
509 MUX_CFG(DM365, AEMIF_AR_BA0, 2, 0, 3, 2, false)
510 MUX_CFG(DM365, AEMIF_A3, 2, 2, 3, 1, false)
511 MUX_CFG(DM365, AEMIF_A7, 2, 4, 3, 1, false)
512 MUX_CFG(DM365, AEMIF_D15_8, 2, 6, 1, 1, false)
513 MUX_CFG(DM365, AEMIF_CE0, 2, 7, 1, 0, false)
514 MUX_CFG(DM365, AEMIF_CE1, 2, 8, 1, 0, false)
515 MUX_CFG(DM365, AEMIF_WE_OE, 2, 9, 1, 0, false)
517 MUX_CFG(DM365, MCBSP0_BDX, 0, 23, 1, 1, false)
518 MUX_CFG(DM365, MCBSP0_X, 0, 22, 1, 1, false)
519 MUX_CFG(DM365, MCBSP0_BFSX, 0, 21, 1, 1, false)
520 MUX_CFG(DM365, MCBSP0_BDR, 0, 20, 1, 1, false)
521 MUX_CFG(DM365, MCBSP0_R, 0, 19, 1, 1, false)
522 MUX_CFG(DM365, MCBSP0_BFSR, 0, 18, 1, 1, false)
524 MUX_CFG(DM365, SPI0_SCLK, 3, 28, 1, 1, false)
525 MUX_CFG(DM365, SPI0_SDI, 3, 26, 3, 1, false)
526 MUX_CFG(DM365, SPI0_SDO, 3, 25, 1, 1, false)
527 MUX_CFG(DM365, SPI0_SDENA0, 3, 29, 3, 1, false)
528 MUX_CFG(DM365, SPI0_SDENA1, 3, 26, 3, 2, false)
530 MUX_CFG(DM365, UART0_RXD, 3, 20, 1, 1, false)
531 MUX_CFG(DM365, UART0_TXD, 3, 19, 1, 1, false)
532 MUX_CFG(DM365, UART1_RXD, 3, 17, 3, 2, false)
533 MUX_CFG(DM365, UART1_TXD, 3, 15, 3, 2, false)
534 MUX_CFG(DM365, UART1_RTS, 3, 23, 3, 1, false)
535 MUX_CFG(DM365, UART1_CTS, 3, 21, 3, 1, false)
537 MUX_CFG(DM365, EMAC_TX_EN, 3, 17, 3, 1, false)
538 MUX_CFG(DM365, EMAC_TX_CLK, 3, 15, 3, 1, false)
539 MUX_CFG(DM365, EMAC_COL, 3, 14, 1, 1, false)
540 MUX_CFG(DM365, EMAC_TXD3, 3, 13, 1, 1, false)
541 MUX_CFG(DM365, EMAC_TXD2, 3, 12, 1, 1, false)
542 MUX_CFG(DM365, EMAC_TXD1, 3, 11, 1, 1, false)
543 MUX_CFG(DM365, EMAC_TXD0, 3, 10, 1, 1, false)
544 MUX_CFG(DM365, EMAC_RXD3, 3, 9, 1, 1, false)
545 MUX_CFG(DM365, EMAC_RXD2, 3, 8, 1, 1, false)
546 MUX_CFG(DM365, EMAC_RXD1, 3, 7, 1, 1, false)
547 MUX_CFG(DM365, EMAC_RXD0, 3, 6, 1, 1, false)
548 MUX_CFG(DM365, EMAC_RX_CLK, 3, 5, 1, 1, false)
549 MUX_CFG(DM365, EMAC_RX_DV, 3, 4, 1, 1, false)
550 MUX_CFG(DM365, EMAC_RX_ER, 3, 3, 1, 1, false)
551 MUX_CFG(DM365, EMAC_CRS, 3, 2, 1, 1, false)
552 MUX_CFG(DM365, EMAC_MDIO, 3, 1, 1, 1, false)
553 MUX_CFG(DM365, EMAC_MDCLK, 3, 0, 1, 1, false)
555 MUX_CFG(DM365, KEYSCAN, 2, 0, 0x3f, 0x3f, false)
557 MUX_CFG(DM365, PWM0, 1, 0, 3, 2, false)
558 MUX_CFG(DM365, PWM0_G23, 3, 26, 3, 3, false)
559 MUX_CFG(DM365, PWM1, 1, 2, 3, 2, false)
560 MUX_CFG(DM365, PWM1_G25, 3, 29, 3, 2, false)
561 MUX_CFG(DM365, PWM2_G87, 1, 10, 3, 2, false)
562 MUX_CFG(DM365, PWM2_G88, 1, 8, 3, 2, false)
563 MUX_CFG(DM365, PWM2_G89, 1, 6, 3, 2, false)
564 MUX_CFG(DM365, PWM2_G90, 1, 4, 3, 2, false)
565 MUX_CFG(DM365, PWM3_G80, 1, 20, 3, 3, false)
566 MUX_CFG(DM365, PWM3_G81, 1, 18, 3, 3, false)
567 MUX_CFG(DM365, PWM3_G85, 1, 14, 3, 2, false)
568 MUX_CFG(DM365, PWM3_G86, 1, 12, 3, 2, false)
570 MUX_CFG(DM365, SPI1_SCLK, 4, 2, 3, 1, false)
571 MUX_CFG(DM365, SPI1_SDI, 3, 31, 1, 1, false)
572 MUX_CFG(DM365, SPI1_SDO, 4, 0, 3, 1, false)
573 MUX_CFG(DM365, SPI1_SDENA0, 4, 4, 3, 1, false)
574 MUX_CFG(DM365, SPI1_SDENA1, 4, 0, 3, 2, false)
576 MUX_CFG(DM365, SPI2_SCLK, 4, 10, 3, 1, false)
577 MUX_CFG(DM365, SPI2_SDI, 4, 6, 3, 1, false)
578 MUX_CFG(DM365, SPI2_SDO, 4, 8, 3, 1, false)
579 MUX_CFG(DM365, SPI2_SDENA0, 4, 12, 3, 1, false)
580 MUX_CFG(DM365, SPI2_SDENA1, 4, 8, 3, 2, false)
582 MUX_CFG(DM365, SPI3_SCLK, 0, 0, 3, 2, false)
583 MUX_CFG(DM365, SPI3_SDI, 0, 2, 3, 2, false)
584 MUX_CFG(DM365, SPI3_SDO, 0, 6, 3, 2, false)
585 MUX_CFG(DM365, SPI3_SDENA0, 0, 4, 3, 2, false)
586 MUX_CFG(DM365, SPI3_SDENA1, 0, 6, 3, 3, false)
588 MUX_CFG(DM365, SPI4_SCLK, 4, 18, 3, 1, false)
589 MUX_CFG(DM365, SPI4_SDI, 4, 14, 3, 1, false)
590 MUX_CFG(DM365, SPI4_SDO, 4, 16, 3, 1, false)
591 MUX_CFG(DM365, SPI4_SDENA0, 4, 20, 3, 1, false)
592 MUX_CFG(DM365, SPI4_SDENA1, 4, 16, 3, 2, false)
594 MUX_CFG(DM365, CLKOUT0, 4, 20, 3, 3, false)
595 MUX_CFG(DM365, CLKOUT1, 4, 16, 3, 3, false)
596 MUX_CFG(DM365, CLKOUT2, 4, 8, 3, 3, false)
598 MUX_CFG(DM365, GPIO20, 3, 21, 3, 0, false)
599 MUX_CFG(DM365, GPIO30, 4, 6, 3, 0, false)
600 MUX_CFG(DM365, GPIO31, 4, 8, 3, 0, false)
601 MUX_CFG(DM365, GPIO32, 4, 10, 3, 0, false)
602 MUX_CFG(DM365, GPIO33, 4, 12, 3, 0, false)
603 MUX_CFG(DM365, GPIO40, 4, 26, 3, 0, false)
604 MUX_CFG(DM365, GPIO64_57, 2, 6, 1, 0, false)
606 MUX_CFG(DM365, VOUT_FIELD, 1, 18, 3, 1, false)
607 MUX_CFG(DM365, VOUT_FIELD_G81, 1, 18, 3, 0, false)
608 MUX_CFG(DM365, VOUT_HVSYNC, 1, 16, 1, 0, false)
609 MUX_CFG(DM365, VOUT_COUTL_EN, 1, 0, 0xff, 0x55, false)
610 MUX_CFG(DM365, VOUT_COUTH_EN, 1, 8, 0xff, 0x55, false)
611 MUX_CFG(DM365, VIN_CAM_WEN, 0, 14, 3, 0, false)
612 MUX_CFG(DM365, VIN_CAM_VD, 0, 13, 1, 0, false)
613 MUX_CFG(DM365, VIN_CAM_HD, 0, 12, 1, 0, false)
614 MUX_CFG(DM365, VIN_YIN4_7_EN, 0, 0, 0xff, 0, false)
615 MUX_CFG(DM365, VIN_YIN0_3_EN, 0, 8, 0xf, 0, false)
617 INT_CFG(DM365, INT_EDMA_CC, 2, 1, 1, false)
618 INT_CFG(DM365, INT_EDMA_TC0_ERR, 3, 1, 1, false)
619 INT_CFG(DM365, INT_EDMA_TC1_ERR, 4, 1, 1, false)
620 INT_CFG(DM365, INT_EDMA_TC2_ERR, 22, 1, 1, false)
621 INT_CFG(DM365, INT_EDMA_TC3_ERR, 23, 1, 1, false)
622 INT_CFG(DM365, INT_PRTCSS, 10, 1, 1, false)
623 INT_CFG(DM365, INT_EMAC_RXTHRESH, 14, 1, 1, false)
624 INT_CFG(DM365, INT_EMAC_RXPULSE, 15, 1, 1, false)
625 INT_CFG(DM365, INT_EMAC_TXPULSE, 16, 1, 1, false)
626 INT_CFG(DM365, INT_EMAC_MISCPULSE, 17, 1, 1, false)
627 INT_CFG(DM365, INT_IMX0_ENABLE, 0, 1, 0, false)
628 INT_CFG(DM365, INT_IMX0_DISABLE, 0, 1, 1, false)
629 INT_CFG(DM365, INT_HDVICP_ENABLE, 0, 1, 1, false)
630 INT_CFG(DM365, INT_HDVICP_DISABLE, 0, 1, 0, false)
631 INT_CFG(DM365, INT_IMX1_ENABLE, 24, 1, 1, false)
632 INT_CFG(DM365, INT_IMX1_DISABLE, 24, 1, 0, false)
633 INT_CFG(DM365, INT_NSF_ENABLE, 25, 1, 1, false)
634 INT_CFG(DM365, INT_NSF_DISABLE, 25, 1, 0, false)
636 EVT_CFG(DM365, EVT2_ASP_TX, 0, 1, 0, false)
637 EVT_CFG(DM365, EVT3_ASP_RX, 1, 1, 0, false)
638 EVT_CFG(DM365, EVT2_VC_TX, 0, 1, 1, false)
639 EVT_CFG(DM365, EVT3_VC_RX, 1, 1, 1, false)
643 static u64 dm365_spi0_dma_mask = DMA_BIT_MASK(32);
645 static struct davinci_spi_platform_data dm365_spi0_pdata = {
646 .version = SPI_VERSION_1,
648 .dma_event_q = EVENTQ_3,
649 .prescaler_limit = 1,
652 static struct resource dm365_spi0_resources[] = {
656 .flags = IORESOURCE_MEM,
659 .start = IRQ_DM365_SPIINT0_0,
660 .flags = IORESOURCE_IRQ,
664 .flags = IORESOURCE_DMA,
668 .flags = IORESOURCE_DMA,
672 static struct platform_device dm365_spi0_device = {
673 .name = "spi_davinci",
676 .dma_mask = &dm365_spi0_dma_mask,
677 .coherent_dma_mask = DMA_BIT_MASK(32),
678 .platform_data = &dm365_spi0_pdata,
680 .num_resources = ARRAY_SIZE(dm365_spi0_resources),
681 .resource = dm365_spi0_resources,
684 void __init dm365_init_spi0(unsigned chipselect_mask,
685 const struct spi_board_info *info, unsigned len)
687 davinci_cfg_reg(DM365_SPI0_SCLK);
688 davinci_cfg_reg(DM365_SPI0_SDI);
689 davinci_cfg_reg(DM365_SPI0_SDO);
691 /* not all slaves will be wired up */
692 if (chipselect_mask & BIT(0))
693 davinci_cfg_reg(DM365_SPI0_SDENA0);
694 if (chipselect_mask & BIT(1))
695 davinci_cfg_reg(DM365_SPI0_SDENA1);
697 spi_register_board_info(info, len);
699 platform_device_register(&dm365_spi0_device);
702 static struct resource dm365_gpio_resources[] = {
704 .start = DAVINCI_GPIO_BASE,
705 .end = DAVINCI_GPIO_BASE + SZ_4K - 1,
706 .flags = IORESOURCE_MEM,
709 .start = IRQ_DM365_GPIO0,
710 .end = IRQ_DM365_GPIO7,
711 .flags = IORESOURCE_IRQ,
715 static struct davinci_gpio_platform_data dm365_gpio_platform_data = {
720 int __init dm365_gpio_register(void)
722 return davinci_gpio_register(dm365_gpio_resources,
723 ARRAY_SIZE(dm365_gpio_resources),
724 &dm365_gpio_platform_data);
727 static struct emac_platform_data dm365_emac_pdata = {
728 .ctrl_reg_offset = DM365_EMAC_CNTRL_OFFSET,
729 .ctrl_mod_reg_offset = DM365_EMAC_CNTRL_MOD_OFFSET,
730 .ctrl_ram_offset = DM365_EMAC_CNTRL_RAM_OFFSET,
731 .ctrl_ram_size = DM365_EMAC_CNTRL_RAM_SIZE,
732 .version = EMAC_VERSION_2,
735 static struct resource dm365_emac_resources[] = {
737 .start = DM365_EMAC_BASE,
738 .end = DM365_EMAC_BASE + SZ_16K - 1,
739 .flags = IORESOURCE_MEM,
742 .start = IRQ_DM365_EMAC_RXTHRESH,
743 .end = IRQ_DM365_EMAC_RXTHRESH,
744 .flags = IORESOURCE_IRQ,
747 .start = IRQ_DM365_EMAC_RXPULSE,
748 .end = IRQ_DM365_EMAC_RXPULSE,
749 .flags = IORESOURCE_IRQ,
752 .start = IRQ_DM365_EMAC_TXPULSE,
753 .end = IRQ_DM365_EMAC_TXPULSE,
754 .flags = IORESOURCE_IRQ,
757 .start = IRQ_DM365_EMAC_MISCPULSE,
758 .end = IRQ_DM365_EMAC_MISCPULSE,
759 .flags = IORESOURCE_IRQ,
763 static struct platform_device dm365_emac_device = {
764 .name = "davinci_emac",
767 .platform_data = &dm365_emac_pdata,
769 .num_resources = ARRAY_SIZE(dm365_emac_resources),
770 .resource = dm365_emac_resources,
773 static struct resource dm365_mdio_resources[] = {
775 .start = DM365_EMAC_MDIO_BASE,
776 .end = DM365_EMAC_MDIO_BASE + SZ_4K - 1,
777 .flags = IORESOURCE_MEM,
781 static struct platform_device dm365_mdio_device = {
782 .name = "davinci_mdio",
784 .num_resources = ARRAY_SIZE(dm365_mdio_resources),
785 .resource = dm365_mdio_resources,
788 static u8 dm365_default_priorities[DAVINCI_N_AINTC_IRQ] = {
796 [IRQ_DM365_INSFINT] = 7,
800 [IRQ_DM365_IMCOPINT] = 4,
802 [IRQ_DM365_RTOINT] = 7,
803 [IRQ_DM365_TINT5] = 7,
804 [IRQ_DM365_TINT6] = 5,
810 [IRQ_DM365_SPINT2_1] = 7,
811 [IRQ_DM365_TINT7] = 7,
812 [IRQ_DM365_SDIOINT0] = 7,
816 [IRQ_DM365_MMCINT1] = 7,
817 [IRQ_DM365_PWMINT3] = 7,
819 [IRQ_DM365_SDIOINT1] = 2,
820 [IRQ_TINT0_TINT12] = 7,
821 [IRQ_TINT0_TINT34] = 7,
822 [IRQ_TINT1_TINT12] = 7,
823 [IRQ_TINT1_TINT34] = 7,
830 [IRQ_DM365_RTCINT] = 3,
831 [IRQ_DM365_SPIINT0_0] = 3,
832 [IRQ_DM365_SPIINT3_0] = 3,
833 [IRQ_DM365_GPIO0] = 3,
834 [IRQ_DM365_GPIO1] = 7,
835 [IRQ_DM365_GPIO2] = 4,
836 [IRQ_DM365_GPIO3] = 4,
837 [IRQ_DM365_GPIO4] = 7,
838 [IRQ_DM365_GPIO5] = 7,
839 [IRQ_DM365_GPIO6] = 7,
840 [IRQ_DM365_GPIO7] = 7,
841 [IRQ_DM365_EMAC_RXTHRESH] = 7,
842 [IRQ_DM365_EMAC_RXPULSE] = 7,
843 [IRQ_DM365_EMAC_TXPULSE] = 7,
844 [IRQ_DM365_EMAC_MISCPULSE] = 7,
845 [IRQ_DM365_GPIO12] = 7,
846 [IRQ_DM365_GPIO13] = 7,
847 [IRQ_DM365_GPIO14] = 7,
848 [IRQ_DM365_GPIO15] = 7,
849 [IRQ_DM365_KEYINT] = 7,
850 [IRQ_DM365_TCERRINT2] = 7,
851 [IRQ_DM365_TCERRINT3] = 7,
852 [IRQ_DM365_EMUINT] = 7,
855 /* Four Transfer Controllers on DM365 */
857 dm365_queue_priority_mapping[][2] = {
858 /* {event queue no, Priority} */
866 static struct edma_soc_info edma_cc0_info = {
867 .queue_priority_mapping = dm365_queue_priority_mapping,
868 .default_queue = EVENTQ_3,
871 static struct edma_soc_info *dm365_edma_info[EDMA_MAX_CC] = {
875 static struct resource edma_resources[] = {
879 .end = 0x01c00000 + SZ_64K - 1,
880 .flags = IORESOURCE_MEM,
885 .end = 0x01c10000 + SZ_1K - 1,
886 .flags = IORESOURCE_MEM,
891 .end = 0x01c10400 + SZ_1K - 1,
892 .flags = IORESOURCE_MEM,
897 .end = 0x01c10800 + SZ_1K - 1,
898 .flags = IORESOURCE_MEM,
903 .end = 0x01c10c00 + SZ_1K - 1,
904 .flags = IORESOURCE_MEM,
909 .flags = IORESOURCE_IRQ,
913 .start = IRQ_CCERRINT,
914 .flags = IORESOURCE_IRQ,
916 /* not using TC*_ERR */
919 static struct platform_device dm365_edma_device = {
922 .dev.platform_data = dm365_edma_info,
923 .num_resources = ARRAY_SIZE(edma_resources),
924 .resource = edma_resources,
927 static struct resource dm365_asp_resources[] = {
930 .start = DAVINCI_DM365_ASP0_BASE,
931 .end = DAVINCI_DM365_ASP0_BASE + SZ_8K - 1,
932 .flags = IORESOURCE_MEM,
935 .start = DAVINCI_DMA_ASP0_TX,
936 .end = DAVINCI_DMA_ASP0_TX,
937 .flags = IORESOURCE_DMA,
940 .start = DAVINCI_DMA_ASP0_RX,
941 .end = DAVINCI_DMA_ASP0_RX,
942 .flags = IORESOURCE_DMA,
946 static struct platform_device dm365_asp_device = {
947 .name = "davinci-mcbsp",
949 .num_resources = ARRAY_SIZE(dm365_asp_resources),
950 .resource = dm365_asp_resources,
953 static struct resource dm365_vc_resources[] = {
955 .start = DAVINCI_DM365_VC_BASE,
956 .end = DAVINCI_DM365_VC_BASE + SZ_1K - 1,
957 .flags = IORESOURCE_MEM,
960 .start = DAVINCI_DMA_VC_TX,
961 .end = DAVINCI_DMA_VC_TX,
962 .flags = IORESOURCE_DMA,
965 .start = DAVINCI_DMA_VC_RX,
966 .end = DAVINCI_DMA_VC_RX,
967 .flags = IORESOURCE_DMA,
971 static struct platform_device dm365_vc_device = {
972 .name = "davinci_voicecodec",
974 .num_resources = ARRAY_SIZE(dm365_vc_resources),
975 .resource = dm365_vc_resources,
978 static struct resource dm365_rtc_resources[] = {
980 .start = DM365_RTC_BASE,
981 .end = DM365_RTC_BASE + SZ_1K - 1,
982 .flags = IORESOURCE_MEM,
985 .start = IRQ_DM365_RTCINT,
986 .flags = IORESOURCE_IRQ,
990 static struct platform_device dm365_rtc_device = {
991 .name = "rtc_davinci",
993 .num_resources = ARRAY_SIZE(dm365_rtc_resources),
994 .resource = dm365_rtc_resources,
997 static struct map_desc dm365_io_desc[] = {
1000 .pfn = __phys_to_pfn(IO_PHYS),
1006 static struct resource dm365_ks_resources[] = {
1009 .start = DM365_KEYSCAN_BASE,
1010 .end = DM365_KEYSCAN_BASE + SZ_1K - 1,
1011 .flags = IORESOURCE_MEM,
1015 .start = IRQ_DM365_KEYINT,
1016 .end = IRQ_DM365_KEYINT,
1017 .flags = IORESOURCE_IRQ,
1021 static struct platform_device dm365_ks_device = {
1022 .name = "davinci_keyscan",
1024 .num_resources = ARRAY_SIZE(dm365_ks_resources),
1025 .resource = dm365_ks_resources,
1028 /* Contents of JTAG ID register used to identify exact cpu type */
1029 static struct davinci_id dm365_ids[] = {
1033 .manufacturer = 0x017,
1034 .cpu_id = DAVINCI_CPU_ID_DM365,
1035 .name = "dm365_rev1.1",
1040 .manufacturer = 0x017,
1041 .cpu_id = DAVINCI_CPU_ID_DM365,
1042 .name = "dm365_rev1.2",
1046 static u32 dm365_psc_bases[] = { DAVINCI_PWR_SLEEP_CNTRL_BASE };
1048 static struct davinci_timer_info dm365_timer_info = {
1049 .timers = davinci_timer_instance,
1050 .clockevent_id = T0_BOT,
1051 .clocksource_id = T0_TOP,
1054 #define DM365_UART1_BASE (IO_PHYS + 0x106000)
1056 static struct plat_serial8250_port dm365_serial0_platform_data[] = {
1058 .mapbase = DAVINCI_UART0_BASE,
1059 .irq = IRQ_UARTINT0,
1060 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
1069 static struct plat_serial8250_port dm365_serial1_platform_data[] = {
1071 .mapbase = DM365_UART1_BASE,
1072 .irq = IRQ_UARTINT1,
1073 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
1083 struct platform_device dm365_serial_device[] = {
1085 .name = "serial8250",
1086 .id = PLAT8250_DEV_PLATFORM,
1088 .platform_data = dm365_serial0_platform_data,
1092 .name = "serial8250",
1093 .id = PLAT8250_DEV_PLATFORM1,
1095 .platform_data = dm365_serial1_platform_data,
1102 static struct davinci_soc_info davinci_soc_info_dm365 = {
1103 .io_desc = dm365_io_desc,
1104 .io_desc_num = ARRAY_SIZE(dm365_io_desc),
1105 .jtag_id_reg = 0x01c40028,
1107 .ids_num = ARRAY_SIZE(dm365_ids),
1108 .cpu_clks = dm365_clks,
1109 .psc_bases = dm365_psc_bases,
1110 .psc_bases_num = ARRAY_SIZE(dm365_psc_bases),
1111 .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
1112 .pinmux_pins = dm365_pins,
1113 .pinmux_pins_num = ARRAY_SIZE(dm365_pins),
1114 .intc_base = DAVINCI_ARM_INTC_BASE,
1115 .intc_type = DAVINCI_INTC_TYPE_AINTC,
1116 .intc_irq_prios = dm365_default_priorities,
1117 .intc_irq_num = DAVINCI_N_AINTC_IRQ,
1118 .timer_info = &dm365_timer_info,
1119 .emac_pdata = &dm365_emac_pdata,
1120 .sram_dma = 0x00010000,
1124 void __init dm365_init_asp(struct snd_platform_data *pdata)
1126 davinci_cfg_reg(DM365_MCBSP0_BDX);
1127 davinci_cfg_reg(DM365_MCBSP0_X);
1128 davinci_cfg_reg(DM365_MCBSP0_BFSX);
1129 davinci_cfg_reg(DM365_MCBSP0_BDR);
1130 davinci_cfg_reg(DM365_MCBSP0_R);
1131 davinci_cfg_reg(DM365_MCBSP0_BFSR);
1132 davinci_cfg_reg(DM365_EVT2_ASP_TX);
1133 davinci_cfg_reg(DM365_EVT3_ASP_RX);
1134 dm365_asp_device.dev.platform_data = pdata;
1135 platform_device_register(&dm365_asp_device);
1138 void __init dm365_init_vc(struct snd_platform_data *pdata)
1140 davinci_cfg_reg(DM365_EVT2_VC_TX);
1141 davinci_cfg_reg(DM365_EVT3_VC_RX);
1142 dm365_vc_device.dev.platform_data = pdata;
1143 platform_device_register(&dm365_vc_device);
1146 void __init dm365_init_ks(struct davinci_ks_platform_data *pdata)
1148 dm365_ks_device.dev.platform_data = pdata;
1149 platform_device_register(&dm365_ks_device);
1152 void __init dm365_init_rtc(void)
1154 davinci_cfg_reg(DM365_INT_PRTCSS);
1155 platform_device_register(&dm365_rtc_device);
1158 void __init dm365_init(void)
1160 davinci_common_init(&davinci_soc_info_dm365);
1161 davinci_map_sysmod();
1164 static struct resource dm365_vpss_resources[] = {
1166 /* VPSS ISP5 Base address */
1168 .start = 0x01c70000,
1169 .end = 0x01c70000 + 0xff,
1170 .flags = IORESOURCE_MEM,
1173 /* VPSS CLK Base address */
1175 .start = 0x01c70200,
1176 .end = 0x01c70200 + 0xff,
1177 .flags = IORESOURCE_MEM,
1181 static struct platform_device dm365_vpss_device = {
1184 .dev.platform_data = "dm365_vpss",
1185 .num_resources = ARRAY_SIZE(dm365_vpss_resources),
1186 .resource = dm365_vpss_resources,
1189 static struct resource vpfe_resources[] = {
1191 .start = IRQ_VDINT0,
1193 .flags = IORESOURCE_IRQ,
1196 .start = IRQ_VDINT1,
1198 .flags = IORESOURCE_IRQ,
1202 static u64 vpfe_capture_dma_mask = DMA_BIT_MASK(32);
1203 static struct platform_device vpfe_capture_dev = {
1204 .name = CAPTURE_DRV_NAME,
1206 .num_resources = ARRAY_SIZE(vpfe_resources),
1207 .resource = vpfe_resources,
1209 .dma_mask = &vpfe_capture_dma_mask,
1210 .coherent_dma_mask = DMA_BIT_MASK(32),
1214 static void dm365_isif_setup_pinmux(void)
1216 davinci_cfg_reg(DM365_VIN_CAM_WEN);
1217 davinci_cfg_reg(DM365_VIN_CAM_VD);
1218 davinci_cfg_reg(DM365_VIN_CAM_HD);
1219 davinci_cfg_reg(DM365_VIN_YIN4_7_EN);
1220 davinci_cfg_reg(DM365_VIN_YIN0_3_EN);
1223 static struct resource isif_resource[] = {
1224 /* ISIF Base address */
1226 .start = 0x01c71000,
1227 .end = 0x01c71000 + 0x1ff,
1228 .flags = IORESOURCE_MEM,
1230 /* ISIF Linearization table 0 */
1233 .end = 0x1C7C000 + 0x2ff,
1234 .flags = IORESOURCE_MEM,
1236 /* ISIF Linearization table 1 */
1239 .end = 0x1C7C400 + 0x2ff,
1240 .flags = IORESOURCE_MEM,
1243 static struct platform_device dm365_isif_dev = {
1246 .num_resources = ARRAY_SIZE(isif_resource),
1247 .resource = isif_resource,
1249 .dma_mask = &vpfe_capture_dma_mask,
1250 .coherent_dma_mask = DMA_BIT_MASK(32),
1251 .platform_data = dm365_isif_setup_pinmux,
1255 static struct resource dm365_osd_resources[] = {
1257 .start = DM365_OSD_BASE,
1258 .end = DM365_OSD_BASE + 0xff,
1259 .flags = IORESOURCE_MEM,
1263 static u64 dm365_video_dma_mask = DMA_BIT_MASK(32);
1265 static struct platform_device dm365_osd_dev = {
1266 .name = DM365_VPBE_OSD_SUBDEV_NAME,
1268 .num_resources = ARRAY_SIZE(dm365_osd_resources),
1269 .resource = dm365_osd_resources,
1271 .dma_mask = &dm365_video_dma_mask,
1272 .coherent_dma_mask = DMA_BIT_MASK(32),
1276 static struct resource dm365_venc_resources[] = {
1278 .start = IRQ_VENCINT,
1280 .flags = IORESOURCE_IRQ,
1282 /* venc registers io space */
1284 .start = DM365_VENC_BASE,
1285 .end = DM365_VENC_BASE + 0x177,
1286 .flags = IORESOURCE_MEM,
1288 /* vdaccfg registers io space */
1290 .start = DAVINCI_SYSTEM_MODULE_BASE + SYSMOD_VDAC_CONFIG,
1291 .end = DAVINCI_SYSTEM_MODULE_BASE + SYSMOD_VDAC_CONFIG + 3,
1292 .flags = IORESOURCE_MEM,
1296 static struct resource dm365_v4l2_disp_resources[] = {
1298 .start = IRQ_VENCINT,
1300 .flags = IORESOURCE_IRQ,
1302 /* venc registers io space */
1304 .start = DM365_VENC_BASE,
1305 .end = DM365_VENC_BASE + 0x177,
1306 .flags = IORESOURCE_MEM,
1310 static int dm365_vpbe_setup_pinmux(u32 if_type, int field)
1313 case MEDIA_BUS_FMT_SGRBG8_1X8:
1314 davinci_cfg_reg(DM365_VOUT_FIELD_G81);
1315 davinci_cfg_reg(DM365_VOUT_COUTL_EN);
1316 davinci_cfg_reg(DM365_VOUT_COUTH_EN);
1318 case MEDIA_BUS_FMT_YUYV10_1X20:
1320 davinci_cfg_reg(DM365_VOUT_FIELD);
1322 davinci_cfg_reg(DM365_VOUT_FIELD_G81);
1323 davinci_cfg_reg(DM365_VOUT_COUTL_EN);
1324 davinci_cfg_reg(DM365_VOUT_COUTH_EN);
1333 static int dm365_venc_setup_clock(enum vpbe_enc_timings_type type,
1334 unsigned int pclock)
1336 void __iomem *vpss_clkctl_reg;
1339 vpss_clkctl_reg = DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL);
1343 val = VPSS_VENCCLKEN_ENABLE | VPSS_DACCLKEN_ENABLE;
1345 case VPBE_ENC_DV_TIMINGS:
1346 if (pclock <= 27000000) {
1347 val = VPSS_VENCCLKEN_ENABLE | VPSS_DACCLKEN_ENABLE;
1349 /* set sysclk4 to output 74.25 MHz from pll1 */
1350 val = VPSS_PLLC2SYSCLK5_ENABLE | VPSS_DACCLKEN_ENABLE |
1351 VPSS_VENCCLKEN_ENABLE;
1357 writel(val, vpss_clkctl_reg);
1362 static struct platform_device dm365_vpbe_display = {
1363 .name = "vpbe-v4l2",
1365 .num_resources = ARRAY_SIZE(dm365_v4l2_disp_resources),
1366 .resource = dm365_v4l2_disp_resources,
1368 .dma_mask = &dm365_video_dma_mask,
1369 .coherent_dma_mask = DMA_BIT_MASK(32),
1373 static struct venc_platform_data dm365_venc_pdata = {
1374 .setup_pinmux = dm365_vpbe_setup_pinmux,
1375 .setup_clock = dm365_venc_setup_clock,
1378 static struct platform_device dm365_venc_dev = {
1379 .name = DM365_VPBE_VENC_SUBDEV_NAME,
1381 .num_resources = ARRAY_SIZE(dm365_venc_resources),
1382 .resource = dm365_venc_resources,
1384 .dma_mask = &dm365_video_dma_mask,
1385 .coherent_dma_mask = DMA_BIT_MASK(32),
1386 .platform_data = (void *)&dm365_venc_pdata,
1390 static struct platform_device dm365_vpbe_dev = {
1391 .name = "vpbe_controller",
1394 .dma_mask = &dm365_video_dma_mask,
1395 .coherent_dma_mask = DMA_BIT_MASK(32),
1399 int __init dm365_init_video(struct vpfe_config *vpfe_cfg,
1400 struct vpbe_config *vpbe_cfg)
1402 if (vpfe_cfg || vpbe_cfg)
1403 platform_device_register(&dm365_vpss_device);
1406 vpfe_capture_dev.dev.platform_data = vpfe_cfg;
1407 platform_device_register(&dm365_isif_dev);
1408 platform_device_register(&vpfe_capture_dev);
1411 dm365_vpbe_dev.dev.platform_data = vpbe_cfg;
1412 platform_device_register(&dm365_osd_dev);
1413 platform_device_register(&dm365_venc_dev);
1414 platform_device_register(&dm365_vpbe_dev);
1415 platform_device_register(&dm365_vpbe_display);
1421 static int __init dm365_init_devices(void)
1425 if (!cpu_is_davinci_dm365())
1428 davinci_cfg_reg(DM365_INT_EDMA_CC);
1429 platform_device_register(&dm365_edma_device);
1431 platform_device_register(&dm365_mdio_device);
1432 platform_device_register(&dm365_emac_device);
1434 ret = davinci_init_wdt();
1436 pr_warn("%s: watchdog init failed: %d\n", __func__, ret);
1440 postcore_initcall(dm365_init_devices);