arch/arm/mach-davinci/dm365.c

   1 /*
   2  * TI DaVinci DM365 chip specific setup
   3  *
   4  * Copyright (C) 2009 Texas Instruments
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation version 2.
   9  *
  10  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  11  * kind, whether express or implied; without even the implied warranty
  12  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15 #include <linux/init.h>
  16 #include <linux/clk.h>
  17 #include <linux/serial_8250.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/dma-mapping.h>
  20 #include <linux/spi/spi.h>
  21
  22 #include <asm/mach/map.h>
  23
  24 #include <mach/cputype.h>
  25 #include <mach/edma.h>
  26 #include <mach/psc.h>
  27 #include <mach/mux.h>
  28 #include <mach/irqs.h>
  29 #include <mach/time.h>
  30 #include <mach/serial.h>
  31 #include <mach/common.h>
  32 #include <linux/platform_data/keyscan-davinci.h>
  33 #include <linux/platform_data/spi-davinci.h>
  34 #include <mach/gpio-davinci.h>
  35
  36 #include "davinci.h"
  37 #include "clock.h"
  38 #include "mux.h"
  39 #include "asp.h"
  40
  41 #define DM365_REF_FREQ          24000000        /* 24 MHz on the DM365 EVM */
  42
  43 /* Base of key scan register bank */
  44 #define DM365_KEYSCAN_BASE              0x01c69400
  45
  46 #define DM365_RTC_BASE                  0x01c69000
  47
  48 #define DAVINCI_DM365_VC_BASE           0x01d0c000
  49 #define DAVINCI_DMA_VC_TX               2
  50 #define DAVINCI_DMA_VC_RX               3
  51
  52 #define DM365_EMAC_BASE                 0x01d07000
  53 #define DM365_EMAC_MDIO_BASE            (DM365_EMAC_BASE + 0x4000)
  54 #define DM365_EMAC_CNTRL_OFFSET         0x0000
  55 #define DM365_EMAC_CNTRL_MOD_OFFSET     0x3000
  56 #define DM365_EMAC_CNTRL_RAM_OFFSET     0x1000
  57 #define DM365_EMAC_CNTRL_RAM_SIZE       0x2000
  58
  59 static struct pll_data pll1_data = {
  60         .num            = 1,
  61         .phys_base      = DAVINCI_PLL1_BASE,
  62         .flags          = PLL_HAS_POSTDIV | PLL_HAS_PREDIV,
  63 };
  64
  65 static struct pll_data pll2_data = {
  66         .num            = 2,
  67         .phys_base      = DAVINCI_PLL2_BASE,
  68         .flags          = PLL_HAS_POSTDIV | PLL_HAS_PREDIV,
  69 };
  70
  71 static struct clk ref_clk = {
  72         .name           = "ref_clk",
  73         .rate           = DM365_REF_FREQ,
  74 };
  75
  76 static struct clk pll1_clk = {
  77         .name           = "pll1",
  78         .parent         = &ref_clk,
  79         .flags          = CLK_PLL,
  80         .pll_data       = &pll1_data,
  81 };
  82
  83 static struct clk pll1_aux_clk = {
  84         .name           = "pll1_aux_clk",
  85         .parent         = &pll1_clk,
  86         .flags          = CLK_PLL | PRE_PLL,
  87 };
  88
  89 static struct clk pll1_sysclkbp = {
  90         .name           = "pll1_sysclkbp",
  91         .parent         = &pll1_clk,
  92         .flags          = CLK_PLL | PRE_PLL,
  93         .div_reg        = BPDIV
  94 };
  95
  96 static struct clk clkout0_clk = {
  97         .name           = "clkout0",
  98         .parent         = &pll1_clk,
  99         .flags          = CLK_PLL | PRE_PLL,
 100 };
 101
 102 static struct clk pll1_sysclk1 = {
 103         .name           = "pll1_sysclk1",
 104         .parent         = &pll1_clk,
 105         .flags          = CLK_PLL,
 106         .div_reg        = PLLDIV1,
 107 };
 108
 109 static struct clk pll1_sysclk2 = {
 110         .name           = "pll1_sysclk2",
 111         .parent         = &pll1_clk,
 112         .flags          = CLK_PLL,
 113         .div_reg        = PLLDIV2,
 114 };
 115
 116 static struct clk pll1_sysclk3 = {
 117         .name           = "pll1_sysclk3",
 118         .parent         = &pll1_clk,
 119         .flags          = CLK_PLL,
 120         .div_reg        = PLLDIV3,
 121 };
 122
 123 static struct clk pll1_sysclk4 = {
 124         .name           = "pll1_sysclk4",
 125         .parent         = &pll1_clk,
 126         .flags          = CLK_PLL,
 127         .div_reg        = PLLDIV4,
 128 };
 129
 130 static struct clk pll1_sysclk5 = {
 131         .name           = "pll1_sysclk5",
 132         .parent         = &pll1_clk,
 133         .flags          = CLK_PLL,
 134         .div_reg        = PLLDIV5,
 135 };
 136
 137 static struct clk pll1_sysclk6 = {
 138         .name           = "pll1_sysclk6",
 139         .parent         = &pll1_clk,
 140         .flags          = CLK_PLL,
 141         .div_reg        = PLLDIV6,
 142 };
 143
 144 static struct clk pll1_sysclk7 = {
 145         .name           = "pll1_sysclk7",
 146         .parent         = &pll1_clk,
 147         .flags          = CLK_PLL,
 148         .div_reg        = PLLDIV7,
 149 };
 150
 151 static struct clk pll1_sysclk8 = {
 152         .name           = "pll1_sysclk8",
 153         .parent         = &pll1_clk,
 154         .flags          = CLK_PLL,
 155         .div_reg        = PLLDIV8,
 156 };
 157
 158 static struct clk pll1_sysclk9 = {
 159         .name           = "pll1_sysclk9",
 160         .parent         = &pll1_clk,
 161         .flags          = CLK_PLL,
 162         .div_reg        = PLLDIV9,
 163 };
 164
 165 static struct clk pll2_clk = {
 166         .name           = "pll2",
 167         .parent         = &ref_clk,
 168         .flags          = CLK_PLL,
 169         .pll_data       = &pll2_data,
 170 };
 171
 172 static struct clk pll2_aux_clk = {
 173         .name           = "pll2_aux_clk",
 174         .parent         = &pll2_clk,
 175         .flags          = CLK_PLL | PRE_PLL,
 176 };
 177
 178 static struct clk clkout1_clk = {
 179         .name           = "clkout1",
 180         .parent         = &pll2_clk,
 181         .flags          = CLK_PLL | PRE_PLL,
 182 };
 183
 184 static struct clk pll2_sysclk1 = {
 185         .name           = "pll2_sysclk1",
 186         .parent         = &pll2_clk,
 187         .flags          = CLK_PLL,
 188         .div_reg        = PLLDIV1,
 189 };
 190
 191 static struct clk pll2_sysclk2 = {
 192         .name           = "pll2_sysclk2",
 193         .parent         = &pll2_clk,
 194         .flags          = CLK_PLL,
 195         .div_reg        = PLLDIV2,
 196 };
 197
 198 static struct clk pll2_sysclk3 = {
 199         .name           = "pll2_sysclk3",
 200         .parent         = &pll2_clk,
 201         .flags          = CLK_PLL,
 202         .div_reg        = PLLDIV3,
 203 };
 204
 205 static struct clk pll2_sysclk4 = {
 206         .name           = "pll2_sysclk4",
 207         .parent         = &pll2_clk,
 208         .flags          = CLK_PLL,
 209         .div_reg        = PLLDIV4,
 210 };
 211
 212 static struct clk pll2_sysclk5 = {
 213         .name           = "pll2_sysclk5",
 214         .parent         = &pll2_clk,
 215         .flags          = CLK_PLL,
 216         .div_reg        = PLLDIV5,
 217 };
 218
 219 static struct clk pll2_sysclk6 = {
 220         .name           = "pll2_sysclk6",
 221         .parent         = &pll2_clk,
 222         .flags          = CLK_PLL,
 223         .div_reg        = PLLDIV6,
 224 };
 225
 226 static struct clk pll2_sysclk7 = {
 227         .name           = "pll2_sysclk7",
 228         .parent         = &pll2_clk,
 229         .flags          = CLK_PLL,
 230         .div_reg        = PLLDIV7,
 231 };
 232
 233 static struct clk pll2_sysclk8 = {
 234         .name           = "pll2_sysclk8",
 235         .parent         = &pll2_clk,
 236         .flags          = CLK_PLL,
 237         .div_reg        = PLLDIV8,
 238 };
 239
 240 static struct clk pll2_sysclk9 = {
 241         .name           = "pll2_sysclk9",
 242         .parent         = &pll2_clk,
 243         .flags          = CLK_PLL,
 244         .div_reg        = PLLDIV9,
 245 };
 246
 247 static struct clk vpss_dac_clk = {
 248         .name           = "vpss_dac",
 249         .parent         = &pll1_sysclk3,
 250         .lpsc           = DM365_LPSC_DAC_CLK,
 251 };
 252
 253 static struct clk vpss_master_clk = {
 254         .name           = "vpss_master",
 255         .parent         = &pll1_sysclk5,
 256         .lpsc           = DM365_LPSC_VPSSMSTR,
 257         .flags          = CLK_PSC,
 258 };
 259
 260 static struct clk arm_clk = {
 261         .name           = "arm_clk",
 262         .parent         = &pll2_sysclk2,
 263         .lpsc           = DAVINCI_LPSC_ARM,
 264         .flags          = ALWAYS_ENABLED,
 265 };
 266
 267 static struct clk uart0_clk = {
 268         .name           = "uart0",
 269         .parent         = &pll1_aux_clk,
 270         .lpsc           = DAVINCI_LPSC_UART0,
 271 };
 272
 273 static struct clk uart1_clk = {
 274         .name           = "uart1",
 275         .parent         = &pll1_sysclk4,
 276         .lpsc           = DAVINCI_LPSC_UART1,
 277 };
 278
 279 static struct clk i2c_clk = {
 280         .name           = "i2c",
 281         .parent         = &pll1_aux_clk,
 282         .lpsc           = DAVINCI_LPSC_I2C,
 283 };
 284
 285 static struct clk mmcsd0_clk = {
 286         .name           = "mmcsd0",
 287         .parent         = &pll1_sysclk8,
 288         .lpsc           = DAVINCI_LPSC_MMC_SD,
 289 };
 290
 291 static struct clk mmcsd1_clk = {
 292         .name           = "mmcsd1",
 293         .parent         = &pll1_sysclk4,
 294         .lpsc           = DM365_LPSC_MMC_SD1,
 295 };
 296
 297 static struct clk spi0_clk = {
 298         .name           = "spi0",
 299         .parent         = &pll1_sysclk4,
 300         .lpsc           = DAVINCI_LPSC_SPI,
 301 };
 302
 303 static struct clk spi1_clk = {
 304         .name           = "spi1",
 305         .parent         = &pll1_sysclk4,
 306         .lpsc           = DM365_LPSC_SPI1,
 307 };
 308
 309 static struct clk spi2_clk = {
 310         .name           = "spi2",
 311         .parent         = &pll1_sysclk4,
 312         .lpsc           = DM365_LPSC_SPI2,
 313 };
 314
 315 static struct clk spi3_clk = {
 316         .name           = "spi3",
 317         .parent         = &pll1_sysclk4,
 318         .lpsc           = DM365_LPSC_SPI3,
 319 };
 320
 321 static struct clk spi4_clk = {
 322         .name           = "spi4",
 323         .parent         = &pll1_aux_clk,
 324         .lpsc           = DM365_LPSC_SPI4,
 325 };
 326
 327 static struct clk gpio_clk = {
 328         .name           = "gpio",
 329         .parent         = &pll1_sysclk4,
 330         .lpsc           = DAVINCI_LPSC_GPIO,
 331 };
 332
 333 static struct clk aemif_clk = {
 334         .name           = "aemif",
 335         .parent         = &pll1_sysclk4,
 336         .lpsc           = DAVINCI_LPSC_AEMIF,
 337 };
 338
 339 static struct clk pwm0_clk = {
 340         .name           = "pwm0",
 341         .parent         = &pll1_aux_clk,
 342         .lpsc           = DAVINCI_LPSC_PWM0,
 343 };
 344
 345 static struct clk pwm1_clk = {
 346         .name           = "pwm1",
 347         .parent         = &pll1_aux_clk,
 348         .lpsc           = DAVINCI_LPSC_PWM1,
 349 };
 350
 351 static struct clk pwm2_clk = {
 352         .name           = "pwm2",
 353         .parent         = &pll1_aux_clk,
 354         .lpsc           = DAVINCI_LPSC_PWM2,
 355 };
 356
 357 static struct clk pwm3_clk = {
 358         .name           = "pwm3",
 359         .parent         = &ref_clk,
 360         .lpsc           = DM365_LPSC_PWM3,
 361 };
 362
 363 static struct clk timer0_clk = {
 364         .name           = "timer0",
 365         .parent         = &pll1_aux_clk,
 366         .lpsc           = DAVINCI_LPSC_TIMER0,
 367 };
 368
 369 static struct clk timer1_clk = {
 370         .name           = "timer1",
 371         .parent         = &pll1_aux_clk,
 372         .lpsc           = DAVINCI_LPSC_TIMER1,
 373 };
 374
 375 static struct clk timer2_clk = {
 376         .name           = "timer2",
 377         .parent         = &pll1_aux_clk,
 378         .lpsc           = DAVINCI_LPSC_TIMER2,
 379         .usecount       = 1,
 380 };
 381
 382 static struct clk timer3_clk = {
 383         .name           = "timer3",
 384         .parent         = &pll1_aux_clk,
 385         .lpsc           = DM365_LPSC_TIMER3,
 386 };
 387
 388 static struct clk usb_clk = {
 389         .name           = "usb",
 390         .parent         = &pll1_aux_clk,
 391         .lpsc           = DAVINCI_LPSC_USB,
 392 };
 393
 394 static struct clk emac_clk = {
 395         .name           = "emac",
 396         .parent         = &pll1_sysclk4,
 397         .lpsc           = DM365_LPSC_EMAC,
 398 };
 399
 400 static struct clk voicecodec_clk = {
 401         .name           = "voice_codec",
 402         .parent         = &pll2_sysclk4,
 403         .lpsc           = DM365_LPSC_VOICE_CODEC,
 404 };
 405
 406 static struct clk asp0_clk = {
 407         .name           = "asp0",
 408         .parent         = &pll1_sysclk4,
 409         .lpsc           = DM365_LPSC_McBSP1,
 410 };
 411
 412 static struct clk rto_clk = {
 413         .name           = "rto",
 414         .parent         = &pll1_sysclk4,
 415         .lpsc           = DM365_LPSC_RTO,
 416 };
 417
 418 static struct clk mjcp_clk = {
 419         .name           = "mjcp",
 420         .parent         = &pll1_sysclk3,
 421         .lpsc           = DM365_LPSC_MJCP,
 422 };
 423
 424 static struct clk_lookup dm365_clks[] = {
 425         CLK(NULL, "ref", &ref_clk),
 426         CLK(NULL, "pll1", &pll1_clk),
 427         CLK(NULL, "pll1_aux", &pll1_aux_clk),
 428         CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp),
 429         CLK(NULL, "clkout0", &clkout0_clk),
 430         CLK(NULL, "pll1_sysclk1", &pll1_sysclk1),
 431         CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
 432         CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
 433         CLK(NULL, "pll1_sysclk4", &pll1_sysclk4),
 434         CLK(NULL, "pll1_sysclk5", &pll1_sysclk5),
 435         CLK(NULL, "pll1_sysclk6", &pll1_sysclk6),
 436         CLK(NULL, "pll1_sysclk7", &pll1_sysclk7),
 437         CLK(NULL, "pll1_sysclk8", &pll1_sysclk8),
 438         CLK(NULL, "pll1_sysclk9", &pll1_sysclk9),
 439         CLK(NULL, "pll2", &pll2_clk),
 440         CLK(NULL, "pll2_aux", &pll2_aux_clk),
 441         CLK(NULL, "clkout1", &clkout1_clk),
 442         CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
 443         CLK(NULL, "pll2_sysclk2", &pll2_sysclk2),
 444         CLK(NULL, "pll2_sysclk3", &pll2_sysclk3),
 445         CLK(NULL, "pll2_sysclk4", &pll2_sysclk4),
 446         CLK(NULL, "pll2_sysclk5", &pll2_sysclk5),
 447         CLK(NULL, "pll2_sysclk6", &pll2_sysclk6),
 448         CLK(NULL, "pll2_sysclk7", &pll2_sysclk7),
 449         CLK(NULL, "pll2_sysclk8", &pll2_sysclk8),
 450         CLK(NULL, "pll2_sysclk9", &pll2_sysclk9),
 451         CLK(NULL, "vpss_dac", &vpss_dac_clk),
 452         CLK(NULL, "vpss_master", &vpss_master_clk),
 453         CLK(NULL, "arm", &arm_clk),
 454         CLK(NULL, "uart0", &uart0_clk),
 455         CLK(NULL, "uart1", &uart1_clk),
 456         CLK("i2c_davinci.1", NULL, &i2c_clk),
 457         CLK("davinci_mmc.0", NULL, &mmcsd0_clk),
 458         CLK("davinci_mmc.1", NULL, &mmcsd1_clk),
 459         CLK("spi_davinci.0", NULL, &spi0_clk),
 460         CLK("spi_davinci.1", NULL, &spi1_clk),
 461         CLK("spi_davinci.2", NULL, &spi2_clk),
 462         CLK("spi_davinci.3", NULL, &spi3_clk),
 463         CLK("spi_davinci.4", NULL, &spi4_clk),
 464         CLK(NULL, "gpio", &gpio_clk),
 465         CLK(NULL, "aemif", &aemif_clk),
 466         CLK(NULL, "pwm0", &pwm0_clk),
 467         CLK(NULL, "pwm1", &pwm1_clk),
 468         CLK(NULL, "pwm2", &pwm2_clk),
 469         CLK(NULL, "pwm3", &pwm3_clk),
 470         CLK(NULL, "timer0", &timer0_clk),
 471         CLK(NULL, "timer1", &timer1_clk),
 472         CLK("watchdog", NULL, &timer2_clk),
 473         CLK(NULL, "timer3", &timer3_clk),
 474         CLK(NULL, "usb", &usb_clk),
 475         CLK("davinci_emac.1", NULL, &emac_clk),
 476         CLK("davinci_voicecodec", NULL, &voicecodec_clk),
 477         CLK("davinci-mcbsp", NULL, &asp0_clk),
 478         CLK(NULL, "rto", &rto_clk),
 479         CLK(NULL, "mjcp", &mjcp_clk),
 480         CLK(NULL, NULL, NULL),
 481 };
 482
 483 /*----------------------------------------------------------------------*/
 484
 485 #define INTMUX          0x18
 486 #define EVTMUX          0x1c
 487
 488
 489 static const struct mux_config dm365_pins[] = {
 490 #ifdef CONFIG_DAVINCI_MUX
 491 MUX_CFG(DM365,  MMCSD0,         0,   24,     1,   0,     false)
 492
 493 MUX_CFG(DM365,  SD1_CLK,        0,   16,    3,    1,     false)
 494 MUX_CFG(DM365,  SD1_CMD,        4,   30,    3,    1,     false)
 495 MUX_CFG(DM365,  SD1_DATA3,      4,   28,    3,    1,     false)
 496 MUX_CFG(DM365,  SD1_DATA2,      4,   26,    3,    1,     false)
 497 MUX_CFG(DM365,  SD1_DATA1,      4,   24,    3,    1,     false)
 498 MUX_CFG(DM365,  SD1_DATA0,      4,   22,    3,    1,     false)
 499
 500 MUX_CFG(DM365,  I2C_SDA,        3,   23,    3,    2,     false)
 501 MUX_CFG(DM365,  I2C_SCL,        3,   21,    3,    2,     false)
 502
 503 MUX_CFG(DM365,  AEMIF_AR_A14,   2,   0,     3,    1,     false)
 504 MUX_CFG(DM365,  AEMIF_AR_BA0,   2,   0,     3,    2,     false)
 505 MUX_CFG(DM365,  AEMIF_A3,       2,   2,     3,    1,     false)
 506 MUX_CFG(DM365,  AEMIF_A7,       2,   4,     3,    1,     false)
 507 MUX_CFG(DM365,  AEMIF_D15_8,    2,   6,     1,    1,     false)
 508 MUX_CFG(DM365,  AEMIF_CE0,      2,   7,     1,    0,     false)
 509 MUX_CFG(DM365,  AEMIF_CE1,      2,   8,     1,    0,     false)
 510 MUX_CFG(DM365,  AEMIF_WE_OE,    2,   9,     1,    0,     false)
 511
 512 MUX_CFG(DM365,  MCBSP0_BDX,     0,   23,    1,    1,     false)
 513 MUX_CFG(DM365,  MCBSP0_X,       0,   22,    1,    1,     false)
 514 MUX_CFG(DM365,  MCBSP0_BFSX,    0,   21,    1,    1,     false)
 515 MUX_CFG(DM365,  MCBSP0_BDR,     0,   20,    1,    1,     false)
 516 MUX_CFG(DM365,  MCBSP0_R,       0,   19,    1,    1,     false)
 517 MUX_CFG(DM365,  MCBSP0_BFSR,    0,   18,    1,    1,     false)
 518
 519 MUX_CFG(DM365,  SPI0_SCLK,      3,   28,    1,    1,     false)
 520 MUX_CFG(DM365,  SPI0_SDI,       3,   26,    3,    1,     false)
 521 MUX_CFG(DM365,  SPI0_SDO,       3,   25,    1,    1,     false)
 522 MUX_CFG(DM365,  SPI0_SDENA0,    3,   29,    3,    1,     false)
 523 MUX_CFG(DM365,  SPI0_SDENA1,    3,   26,    3,    2,     false)
 524
 525 MUX_CFG(DM365,  UART0_RXD,      3,   20,    1,    1,     false)
 526 MUX_CFG(DM365,  UART0_TXD,      3,   19,    1,    1,     false)
 527 MUX_CFG(DM365,  UART1_RXD,      3,   17,    3,    2,     false)
 528 MUX_CFG(DM365,  UART1_TXD,      3,   15,    3,    2,     false)
 529 MUX_CFG(DM365,  UART1_RTS,      3,   23,    3,    1,     false)
 530 MUX_CFG(DM365,  UART1_CTS,      3,   21,    3,    1,     false)
 531
 532 MUX_CFG(DM365,  EMAC_TX_EN,     3,   17,    3,    1,     false)
 533 MUX_CFG(DM365,  EMAC_TX_CLK,    3,   15,    3,    1,     false)
 534 MUX_CFG(DM365,  EMAC_COL,       3,   14,    1,    1,     false)
 535 MUX_CFG(DM365,  EMAC_TXD3,      3,   13,    1,    1,     false)
 536 MUX_CFG(DM365,  EMAC_TXD2,      3,   12,    1,    1,     false)
 537 MUX_CFG(DM365,  EMAC_TXD1,      3,   11,    1,    1,     false)
 538 MUX_CFG(DM365,  EMAC_TXD0,      3,   10,    1,    1,     false)
 539 MUX_CFG(DM365,  EMAC_RXD3,      3,   9,     1,    1,     false)
 540 MUX_CFG(DM365,  EMAC_RXD2,      3,   8,     1,    1,     false)
 541 MUX_CFG(DM365,  EMAC_RXD1,      3,   7,     1,    1,     false)
 542 MUX_CFG(DM365,  EMAC_RXD0,      3,   6,     1,    1,     false)
 543 MUX_CFG(DM365,  EMAC_RX_CLK,    3,   5,     1,    1,     false)
 544 MUX_CFG(DM365,  EMAC_RX_DV,     3,   4,     1,    1,     false)
 545 MUX_CFG(DM365,  EMAC_RX_ER,     3,   3,     1,    1,     false)
 546 MUX_CFG(DM365,  EMAC_CRS,       3,   2,     1,    1,     false)
 547 MUX_CFG(DM365,  EMAC_MDIO,      3,   1,     1,    1,     false)
 548 MUX_CFG(DM365,  EMAC_MDCLK,     3,   0,     1,    1,     false)
 549
 550 MUX_CFG(DM365,  KEYSCAN,        2,   0,     0x3f, 0x3f,  false)
 551
 552 MUX_CFG(DM365,  PWM0,           1,   0,     3,    2,     false)
 553 MUX_CFG(DM365,  PWM0_G23,       3,   26,    3,    3,     false)
 554 MUX_CFG(DM365,  PWM1,           1,   2,     3,    2,     false)
 555 MUX_CFG(DM365,  PWM1_G25,       3,   29,    3,    2,     false)
 556 MUX_CFG(DM365,  PWM2_G87,       1,   10,    3,    2,     false)
 557 MUX_CFG(DM365,  PWM2_G88,       1,   8,     3,    2,     false)
 558 MUX_CFG(DM365,  PWM2_G89,       1,   6,     3,    2,     false)
 559 MUX_CFG(DM365,  PWM2_G90,       1,   4,     3,    2,     false)
 560 MUX_CFG(DM365,  PWM3_G80,       1,   20,    3,    3,     false)
 561 MUX_CFG(DM365,  PWM3_G81,       1,   18,    3,    3,     false)
 562 MUX_CFG(DM365,  PWM3_G85,       1,   14,    3,    2,     false)
 563 MUX_CFG(DM365,  PWM3_G86,       1,   12,    3,    2,     false)
 564
 565 MUX_CFG(DM365,  SPI1_SCLK,      4,   2,     3,    1,     false)
 566 MUX_CFG(DM365,  SPI1_SDI,       3,   31,    1,    1,     false)
 567 MUX_CFG(DM365,  SPI1_SDO,       4,   0,     3,    1,     false)
 568 MUX_CFG(DM365,  SPI1_SDENA0,    4,   4,     3,    1,     false)
 569 MUX_CFG(DM365,  SPI1_SDENA1,    4,   0,     3,    2,     false)
 570
 571 MUX_CFG(DM365,  SPI2_SCLK,      4,   10,    3,    1,     false)
 572 MUX_CFG(DM365,  SPI2_SDI,       4,   6,     3,    1,     false)
 573 MUX_CFG(DM365,  SPI2_SDO,       4,   8,     3,    1,     false)
 574 MUX_CFG(DM365,  SPI2_SDENA0,    4,   12,    3,    1,     false)
 575 MUX_CFG(DM365,  SPI2_SDENA1,    4,   8,     3,    2,     false)
 576
 577 MUX_CFG(DM365,  SPI3_SCLK,      0,   0,     3,    2,     false)
 578 MUX_CFG(DM365,  SPI3_SDI,       0,   2,     3,    2,     false)
 579 MUX_CFG(DM365,  SPI3_SDO,       0,   6,     3,    2,     false)
 580 MUX_CFG(DM365,  SPI3_SDENA0,    0,   4,     3,    2,     false)
 581 MUX_CFG(DM365,  SPI3_SDENA1,    0,   6,     3,    3,     false)
 582
 583 MUX_CFG(DM365,  SPI4_SCLK,      4,   18,    3,    1,     false)
 584 MUX_CFG(DM365,  SPI4_SDI,       4,   14,    3,    1,     false)
 585 MUX_CFG(DM365,  SPI4_SDO,       4,   16,    3,    1,     false)
 586 MUX_CFG(DM365,  SPI4_SDENA0,    4,   20,    3,    1,     false)
 587 MUX_CFG(DM365,  SPI4_SDENA1,    4,   16,    3,    2,     false)
 588
 589 MUX_CFG(DM365,  CLKOUT0,        4,   20,    3,    3,     false)
 590 MUX_CFG(DM365,  CLKOUT1,        4,   16,    3,    3,     false)
 591 MUX_CFG(DM365,  CLKOUT2,        4,   8,     3,    3,     false)
 592
 593 MUX_CFG(DM365,  GPIO20,         3,   21,    3,    0,     false)
 594 MUX_CFG(DM365,  GPIO30,         4,   6,     3,    0,     false)
 595 MUX_CFG(DM365,  GPIO31,         4,   8,     3,    0,     false)
 596 MUX_CFG(DM365,  GPIO32,         4,   10,    3,    0,     false)
 597 MUX_CFG(DM365,  GPIO33,         4,   12,    3,    0,     false)
 598 MUX_CFG(DM365,  GPIO40,         4,   26,    3,    0,     false)
 599 MUX_CFG(DM365,  GPIO64_57,      2,   6,     1,    0,     false)
 600
 601 MUX_CFG(DM365,  VOUT_FIELD,     1,   18,    3,    1,     false)
 602 MUX_CFG(DM365,  VOUT_FIELD_G81, 1,   18,    3,    0,     false)
 603 MUX_CFG(DM365,  VOUT_HVSYNC,    1,   16,    1,    0,     false)
 604 MUX_CFG(DM365,  VOUT_COUTL_EN,  1,   0,     0xff, 0x55,  false)
 605 MUX_CFG(DM365,  VOUT_COUTH_EN,  1,   8,     0xff, 0x55,  false)
 606 MUX_CFG(DM365,  VIN_CAM_WEN,    0,   14,    3,    0,     false)
 607 MUX_CFG(DM365,  VIN_CAM_VD,     0,   13,    1,    0,     false)
 608 MUX_CFG(DM365,  VIN_CAM_HD,     0,   12,    1,    0,     false)
 609 MUX_CFG(DM365,  VIN_YIN4_7_EN,  0,   0,     0xff, 0,     false)
 610 MUX_CFG(DM365,  VIN_YIN0_3_EN,  0,   8,     0xf,  0,     false)
 611
 612 INT_CFG(DM365,  INT_EDMA_CC,         2,     1,    1,     false)
 613 INT_CFG(DM365,  INT_EDMA_TC0_ERR,    3,     1,    1,     false)
 614 INT_CFG(DM365,  INT_EDMA_TC1_ERR,    4,     1,    1,     false)
 615 INT_CFG(DM365,  INT_EDMA_TC2_ERR,    22,    1,    1,     false)
 616 INT_CFG(DM365,  INT_EDMA_TC3_ERR,    23,    1,    1,     false)
 617 INT_CFG(DM365,  INT_PRTCSS,          10,    1,    1,     false)
 618 INT_CFG(DM365,  INT_EMAC_RXTHRESH,   14,    1,    1,     false)
 619 INT_CFG(DM365,  INT_EMAC_RXPULSE,    15,    1,    1,     false)
 620 INT_CFG(DM365,  INT_EMAC_TXPULSE,    16,    1,    1,     false)
 621 INT_CFG(DM365,  INT_EMAC_MISCPULSE,  17,    1,    1,     false)
 622 INT_CFG(DM365,  INT_IMX0_ENABLE,     0,     1,    0,     false)
 623 INT_CFG(DM365,  INT_IMX0_DISABLE,    0,     1,    1,     false)
 624 INT_CFG(DM365,  INT_HDVICP_ENABLE,   0,     1,    1,     false)
 625 INT_CFG(DM365,  INT_HDVICP_DISABLE,  0,     1,    0,     false)
 626 INT_CFG(DM365,  INT_IMX1_ENABLE,     24,    1,    1,     false)
 627 INT_CFG(DM365,  INT_IMX1_DISABLE,    24,    1,    0,     false)
 628 INT_CFG(DM365,  INT_NSF_ENABLE,      25,    1,    1,     false)
 629 INT_CFG(DM365,  INT_NSF_DISABLE,     25,    1,    0,     false)
 630
 631 EVT_CFG(DM365,  EVT2_ASP_TX,         0,     1,    0,     false)
 632 EVT_CFG(DM365,  EVT3_ASP_RX,         1,     1,    0,     false)
 633 EVT_CFG(DM365,  EVT2_VC_TX,          0,     1,    1,     false)
 634 EVT_CFG(DM365,  EVT3_VC_RX,          1,     1,    1,     false)
 635 #endif
 636 };
 637
 638 static u64 dm365_spi0_dma_mask = DMA_BIT_MASK(32);
 639
 640 static struct davinci_spi_platform_data dm365_spi0_pdata = {
 641         .version        = SPI_VERSION_1,
 642         .num_chipselect = 2,
 643         .dma_event_q    = EVENTQ_3,
 644 };
 645
 646 static struct resource dm365_spi0_resources[] = {
 647         {
 648                 .start = 0x01c66000,
 649                 .end   = 0x01c667ff,
 650                 .flags = IORESOURCE_MEM,
 651         },
 652         {
 653                 .start = IRQ_DM365_SPIINT0_0,
 654                 .flags = IORESOURCE_IRQ,
 655         },
 656         {
 657                 .start = 17,
 658                 .flags = IORESOURCE_DMA,
 659         },
 660         {
 661                 .start = 16,
 662                 .flags = IORESOURCE_DMA,
 663         },
 664 };
 665
 666 static struct platform_device dm365_spi0_device = {
 667         .name = "spi_davinci",
 668         .id = 0,
 669         .dev = {
 670                 .dma_mask = &dm365_spi0_dma_mask,
 671                 .coherent_dma_mask = DMA_BIT_MASK(32),
 672                 .platform_data = &dm365_spi0_pdata,
 673         },
 674         .num_resources = ARRAY_SIZE(dm365_spi0_resources),
 675         .resource = dm365_spi0_resources,
 676 };
 677
 678 void __init dm365_init_spi0(unsigned chipselect_mask,
 679                 const struct spi_board_info *info, unsigned len)
 680 {
 681         davinci_cfg_reg(DM365_SPI0_SCLK);
 682         davinci_cfg_reg(DM365_SPI0_SDI);
 683         davinci_cfg_reg(DM365_SPI0_SDO);
 684
 685         /* not all slaves will be wired up */
 686         if (chipselect_mask & BIT(0))
 687                 davinci_cfg_reg(DM365_SPI0_SDENA0);
 688         if (chipselect_mask & BIT(1))
 689                 davinci_cfg_reg(DM365_SPI0_SDENA1);
 690
 691         spi_register_board_info(info, len);
 692
 693         platform_device_register(&dm365_spi0_device);
 694 }
 695
 696 static struct emac_platform_data dm365_emac_pdata = {
 697         .ctrl_reg_offset        = DM365_EMAC_CNTRL_OFFSET,
 698         .ctrl_mod_reg_offset    = DM365_EMAC_CNTRL_MOD_OFFSET,
 699         .ctrl_ram_offset        = DM365_EMAC_CNTRL_RAM_OFFSET,
 700         .ctrl_ram_size          = DM365_EMAC_CNTRL_RAM_SIZE,
 701         .version                = EMAC_VERSION_2,
 702 };
 703
 704 static struct resource dm365_emac_resources[] = {
 705         {
 706                 .start  = DM365_EMAC_BASE,
 707                 .end    = DM365_EMAC_BASE + SZ_16K - 1,
 708                 .flags  = IORESOURCE_MEM,
 709         },
 710         {
 711                 .start  = IRQ_DM365_EMAC_RXTHRESH,
 712                 .end    = IRQ_DM365_EMAC_RXTHRESH,
 713                 .flags  = IORESOURCE_IRQ,
 714         },
 715         {
 716                 .start  = IRQ_DM365_EMAC_RXPULSE,
 717                 .end    = IRQ_DM365_EMAC_RXPULSE,
 718                 .flags  = IORESOURCE_IRQ,
 719         },
 720         {
 721                 .start  = IRQ_DM365_EMAC_TXPULSE,
 722                 .end    = IRQ_DM365_EMAC_TXPULSE,
 723                 .flags  = IORESOURCE_IRQ,
 724         },
 725         {
 726                 .start  = IRQ_DM365_EMAC_MISCPULSE,
 727                 .end    = IRQ_DM365_EMAC_MISCPULSE,
 728                 .flags  = IORESOURCE_IRQ,
 729         },
 730 };
 731
 732 static struct platform_device dm365_emac_device = {
 733         .name           = "davinci_emac",
 734         .id             = 1,
 735         .dev = {
 736                 .platform_data  = &dm365_emac_pdata,
 737         },
 738         .num_resources  = ARRAY_SIZE(dm365_emac_resources),
 739         .resource       = dm365_emac_resources,
 740 };
 741
 742 static struct resource dm365_mdio_resources[] = {
 743         {
 744                 .start  = DM365_EMAC_MDIO_BASE,
 745                 .end    = DM365_EMAC_MDIO_BASE + SZ_4K - 1,
 746                 .flags  = IORESOURCE_MEM,
 747         },
 748 };
 749
 750 static struct platform_device dm365_mdio_device = {
 751         .name           = "davinci_mdio",
 752         .id             = 0,
 753         .num_resources  = ARRAY_SIZE(dm365_mdio_resources),
 754         .resource       = dm365_mdio_resources,
 755 };
 756
 757 static u8 dm365_default_priorities[DAVINCI_N_AINTC_IRQ] = {
 758         [IRQ_VDINT0]                    = 2,
 759         [IRQ_VDINT1]                    = 6,
 760         [IRQ_VDINT2]                    = 6,
 761         [IRQ_HISTINT]                   = 6,
 762         [IRQ_H3AINT]                    = 6,
 763         [IRQ_PRVUINT]                   = 6,
 764         [IRQ_RSZINT]                    = 6,
 765         [IRQ_DM365_INSFINT]             = 7,
 766         [IRQ_VENCINT]                   = 6,
 767         [IRQ_ASQINT]                    = 6,
 768         [IRQ_IMXINT]                    = 6,
 769         [IRQ_DM365_IMCOPINT]            = 4,
 770         [IRQ_USBINT]                    = 4,
 771         [IRQ_DM365_RTOINT]              = 7,
 772         [IRQ_DM365_TINT5]               = 7,
 773         [IRQ_DM365_TINT6]               = 5,
 774         [IRQ_CCINT0]                    = 5,
 775         [IRQ_CCERRINT]                  = 5,
 776         [IRQ_TCERRINT0]                 = 5,
 777         [IRQ_TCERRINT]                  = 7,
 778         [IRQ_PSCIN]                     = 4,
 779         [IRQ_DM365_SPINT2_1]            = 7,
 780         [IRQ_DM365_TINT7]               = 7,
 781         [IRQ_DM365_SDIOINT0]            = 7,
 782         [IRQ_MBXINT]                    = 7,
 783         [IRQ_MBRINT]                    = 7,
 784         [IRQ_MMCINT]                    = 7,
 785         [IRQ_DM365_MMCINT1]             = 7,
 786         [IRQ_DM365_PWMINT3]             = 7,
 787         [IRQ_AEMIFINT]                  = 2,
 788         [IRQ_DM365_SDIOINT1]            = 2,
 789         [IRQ_TINT0_TINT12]              = 7,
 790         [IRQ_TINT0_TINT34]              = 7,
 791         [IRQ_TINT1_TINT12]              = 7,
 792         [IRQ_TINT1_TINT34]              = 7,
 793         [IRQ_PWMINT0]                   = 7,
 794         [IRQ_PWMINT1]                   = 3,
 795         [IRQ_PWMINT2]                   = 3,
 796         [IRQ_I2C]                       = 3,
 797         [IRQ_UARTINT0]                  = 3,
 798         [IRQ_UARTINT1]                  = 3,
 799         [IRQ_DM365_RTCINT]              = 3,
 800         [IRQ_DM365_SPIINT0_0]           = 3,
 801         [IRQ_DM365_SPIINT3_0]           = 3,
 802         [IRQ_DM365_GPIO0]               = 3,
 803         [IRQ_DM365_GPIO1]               = 7,
 804         [IRQ_DM365_GPIO2]               = 4,
 805         [IRQ_DM365_GPIO3]               = 4,
 806         [IRQ_DM365_GPIO4]               = 7,
 807         [IRQ_DM365_GPIO5]               = 7,
 808         [IRQ_DM365_GPIO6]               = 7,
 809         [IRQ_DM365_GPIO7]               = 7,
 810         [IRQ_DM365_EMAC_RXTHRESH]       = 7,
 811         [IRQ_DM365_EMAC_RXPULSE]        = 7,
 812         [IRQ_DM365_EMAC_TXPULSE]        = 7,
 813         [IRQ_DM365_EMAC_MISCPULSE]      = 7,
 814         [IRQ_DM365_GPIO12]              = 7,
 815         [IRQ_DM365_GPIO13]              = 7,
 816         [IRQ_DM365_GPIO14]              = 7,
 817         [IRQ_DM365_GPIO15]              = 7,
 818         [IRQ_DM365_KEYINT]              = 7,
 819         [IRQ_DM365_TCERRINT2]           = 7,
 820         [IRQ_DM365_TCERRINT3]           = 7,
 821         [IRQ_DM365_EMUINT]              = 7,
 822 };
 823
 824 /* Four Transfer Controllers on DM365 */
 825 static const s8
 826 dm365_queue_tc_mapping[][2] = {
 827         /* {event queue no, TC no} */
 828         {0, 0},
 829         {1, 1},
 830         {2, 2},
 831         {3, 3},
 832         {-1, -1},
 833 };
 834
 835 static const s8
 836 dm365_queue_priority_mapping[][2] = {
 837         /* {event queue no, Priority} */
 838         {0, 7},
 839         {1, 7},
 840         {2, 7},
 841         {3, 0},
 842         {-1, -1},
 843 };
 844
 845 static struct edma_soc_info edma_cc0_info = {
 846         .n_channel              = 64,
 847         .n_region               = 4,
 848         .n_slot                 = 256,
 849         .n_tc                   = 4,
 850         .n_cc                   = 1,
 851         .queue_tc_mapping       = dm365_queue_tc_mapping,
 852         .queue_priority_mapping = dm365_queue_priority_mapping,
 853         .default_queue          = EVENTQ_3,
 854 };
 855
 856 static struct edma_soc_info *dm365_edma_info[EDMA_MAX_CC] = {
 857         &edma_cc0_info,
 858 };
 859
 860 static struct resource edma_resources[] = {
 861         {
 862                 .name   = "edma_cc0",
 863                 .start  = 0x01c00000,
 864                 .end    = 0x01c00000 + SZ_64K - 1,
 865                 .flags  = IORESOURCE_MEM,
 866         },
 867         {
 868                 .name   = "edma_tc0",
 869                 .start  = 0x01c10000,
 870                 .end    = 0x01c10000 + SZ_1K - 1,
 871                 .flags  = IORESOURCE_MEM,
 872         },
 873         {
 874                 .name   = "edma_tc1",
 875                 .start  = 0x01c10400,
 876                 .end    = 0x01c10400 + SZ_1K - 1,
 877                 .flags  = IORESOURCE_MEM,
 878         },
 879         {
 880                 .name   = "edma_tc2",
 881                 .start  = 0x01c10800,
 882                 .end    = 0x01c10800 + SZ_1K - 1,
 883                 .flags  = IORESOURCE_MEM,
 884         },
 885         {
 886                 .name   = "edma_tc3",
 887                 .start  = 0x01c10c00,
 888                 .end    = 0x01c10c00 + SZ_1K - 1,
 889                 .flags  = IORESOURCE_MEM,
 890         },
 891         {
 892                 .name   = "edma0",
 893                 .start  = IRQ_CCINT0,
 894                 .flags  = IORESOURCE_IRQ,
 895         },
 896         {
 897                 .name   = "edma0_err",
 898                 .start  = IRQ_CCERRINT,
 899                 .flags  = IORESOURCE_IRQ,
 900         },
 901         /* not using TC*_ERR */
 902 };
 903
 904 static struct platform_device dm365_edma_device = {
 905         .name                   = "edma",
 906         .id                     = 0,
 907         .dev.platform_data      = dm365_edma_info,
 908         .num_resources          = ARRAY_SIZE(edma_resources),
 909         .resource               = edma_resources,
 910 };
 911
 912 static struct resource dm365_asp_resources[] = {
 913         {
 914                 .start  = DAVINCI_DM365_ASP0_BASE,
 915                 .end    = DAVINCI_DM365_ASP0_BASE + SZ_8K - 1,
 916                 .flags  = IORESOURCE_MEM,
 917         },
 918         {
 919                 .start  = DAVINCI_DMA_ASP0_TX,
 920                 .end    = DAVINCI_DMA_ASP0_TX,
 921                 .flags  = IORESOURCE_DMA,
 922         },
 923         {
 924                 .start  = DAVINCI_DMA_ASP0_RX,
 925                 .end    = DAVINCI_DMA_ASP0_RX,
 926                 .flags  = IORESOURCE_DMA,
 927         },
 928 };
 929
 930 static struct platform_device dm365_asp_device = {
 931         .name           = "davinci-mcbsp",
 932         .id             = -1,
 933         .num_resources  = ARRAY_SIZE(dm365_asp_resources),
 934         .resource       = dm365_asp_resources,
 935 };
 936
 937 static struct resource dm365_vc_resources[] = {
 938         {
 939                 .start  = DAVINCI_DM365_VC_BASE,
 940                 .end    = DAVINCI_DM365_VC_BASE + SZ_1K - 1,
 941                 .flags  = IORESOURCE_MEM,
 942         },
 943         {
 944                 .start  = DAVINCI_DMA_VC_TX,
 945                 .end    = DAVINCI_DMA_VC_TX,
 946                 .flags  = IORESOURCE_DMA,
 947         },
 948         {
 949                 .start  = DAVINCI_DMA_VC_RX,
 950                 .end    = DAVINCI_DMA_VC_RX,
 951                 .flags  = IORESOURCE_DMA,
 952         },
 953 };
 954
 955 static struct platform_device dm365_vc_device = {
 956         .name           = "davinci_voicecodec",
 957         .id             = -1,
 958         .num_resources  = ARRAY_SIZE(dm365_vc_resources),
 959         .resource       = dm365_vc_resources,
 960 };
 961
 962 static struct resource dm365_rtc_resources[] = {
 963         {
 964                 .start = DM365_RTC_BASE,
 965                 .end = DM365_RTC_BASE + SZ_1K - 1,
 966                 .flags = IORESOURCE_MEM,
 967         },
 968         {
 969                 .start = IRQ_DM365_RTCINT,
 970                 .flags = IORESOURCE_IRQ,
 971         },
 972 };
 973
 974 static struct platform_device dm365_rtc_device = {
 975         .name = "rtc_davinci",
 976         .id = 0,
 977         .num_resources = ARRAY_SIZE(dm365_rtc_resources),
 978         .resource = dm365_rtc_resources,
 979 };
 980
 981 static struct map_desc dm365_io_desc[] = {
 982         {
 983                 .virtual        = IO_VIRT,
 984                 .pfn            = __phys_to_pfn(IO_PHYS),
 985                 .length         = IO_SIZE,
 986                 .type           = MT_DEVICE
 987         },
 988         {
 989                 .virtual        = SRAM_VIRT,
 990                 .pfn            = __phys_to_pfn(0x00010000),
 991                 .length         = SZ_32K,
 992                 .type           = MT_MEMORY_NONCACHED,
 993         },
 994 };
 995
 996 static struct resource dm365_ks_resources[] = {
 997         {
 998                 /* registers */
 999                 .start = DM365_KEYSCAN_BASE,
1000                 .end = DM365_KEYSCAN_BASE + SZ_1K - 1,
1001                 .flags = IORESOURCE_MEM,
1002         },
1003         {
1004                 /* interrupt */
1005                 .start = IRQ_DM365_KEYINT,
1006                 .end = IRQ_DM365_KEYINT,
1007                 .flags = IORESOURCE_IRQ,
1008         },
1009 };
1010
1011 static struct platform_device dm365_ks_device = {
1012         .name           = "davinci_keyscan",
1013         .id             = 0,
1014         .num_resources  = ARRAY_SIZE(dm365_ks_resources),
1015         .resource       = dm365_ks_resources,
1016 };
1017
1018 /* Contents of JTAG ID register used to identify exact cpu type */
1019 static struct davinci_id dm365_ids[] = {
1020         {
1021                 .variant        = 0x0,
1022                 .part_no        = 0xb83e,
1023                 .manufacturer   = 0x017,
1024                 .cpu_id         = DAVINCI_CPU_ID_DM365,
1025                 .name           = "dm365_rev1.1",
1026         },
1027         {
1028                 .variant        = 0x8,
1029                 .part_no        = 0xb83e,
1030                 .manufacturer   = 0x017,
1031                 .cpu_id         = DAVINCI_CPU_ID_DM365,
1032                 .name           = "dm365_rev1.2",
1033         },
1034 };
1035
1036 static u32 dm365_psc_bases[] = { DAVINCI_PWR_SLEEP_CNTRL_BASE };
1037
1038 static struct davinci_timer_info dm365_timer_info = {
1039         .timers         = davinci_timer_instance,
1040         .clockevent_id  = T0_BOT,
1041         .clocksource_id = T0_TOP,
1042 };
1043
1044 #define DM365_UART1_BASE        (IO_PHYS + 0x106000)
1045
1046 static struct plat_serial8250_port dm365_serial_platform_data[] = {
1047         {
1048                 .mapbase        = DAVINCI_UART0_BASE,
1049                 .irq            = IRQ_UARTINT0,
1050                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
1051                                   UPF_IOREMAP,
1052                 .iotype         = UPIO_MEM,
1053                 .regshift       = 2,
1054         },
1055         {
1056                 .mapbase        = DM365_UART1_BASE,
1057                 .irq            = IRQ_UARTINT1,
1058                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
1059                                   UPF_IOREMAP,
1060                 .iotype         = UPIO_MEM,
1061                 .regshift       = 2,
1062         },
1063         {
1064                 .flags          = 0
1065         },
1066 };
1067
1068 static struct platform_device dm365_serial_device = {
1069         .name                   = "serial8250",
1070         .id                     = PLAT8250_DEV_PLATFORM,
1071         .dev                    = {
1072                 .platform_data  = dm365_serial_platform_data,
1073         },
1074 };
1075
1076 static struct davinci_soc_info davinci_soc_info_dm365 = {
1077         .io_desc                = dm365_io_desc,
1078         .io_desc_num            = ARRAY_SIZE(dm365_io_desc),
1079         .jtag_id_reg            = 0x01c40028,
1080         .ids                    = dm365_ids,
1081         .ids_num                = ARRAY_SIZE(dm365_ids),
1082         .cpu_clks               = dm365_clks,
1083         .psc_bases              = dm365_psc_bases,
1084         .psc_bases_num          = ARRAY_SIZE(dm365_psc_bases),
1085         .pinmux_base            = DAVINCI_SYSTEM_MODULE_BASE,
1086         .pinmux_pins            = dm365_pins,
1087         .pinmux_pins_num        = ARRAY_SIZE(dm365_pins),
1088         .intc_base              = DAVINCI_ARM_INTC_BASE,
1089         .intc_type              = DAVINCI_INTC_TYPE_AINTC,
1090         .intc_irq_prios         = dm365_default_priorities,
1091         .intc_irq_num           = DAVINCI_N_AINTC_IRQ,
1092         .timer_info             = &dm365_timer_info,
1093         .gpio_type              = GPIO_TYPE_DAVINCI,
1094         .gpio_base              = DAVINCI_GPIO_BASE,
1095         .gpio_num               = 104,
1096         .gpio_irq               = IRQ_DM365_GPIO0,
1097         .gpio_unbanked          = 8,    /* really 16 ... skip muxed GPIOs */
1098         .serial_dev             = &dm365_serial_device,
1099         .emac_pdata             = &dm365_emac_pdata,
1100         .sram_dma               = 0x00010000,
1101         .sram_len               = SZ_32K,
1102 };
1103
1104 void __init dm365_init_asp(struct snd_platform_data *pdata)
1105 {
1106         davinci_cfg_reg(DM365_MCBSP0_BDX);
1107         davinci_cfg_reg(DM365_MCBSP0_X);
1108         davinci_cfg_reg(DM365_MCBSP0_BFSX);
1109         davinci_cfg_reg(DM365_MCBSP0_BDR);
1110         davinci_cfg_reg(DM365_MCBSP0_R);
1111         davinci_cfg_reg(DM365_MCBSP0_BFSR);
1112         davinci_cfg_reg(DM365_EVT2_ASP_TX);
1113         davinci_cfg_reg(DM365_EVT3_ASP_RX);
1114         dm365_asp_device.dev.platform_data = pdata;
1115         platform_device_register(&dm365_asp_device);
1116 }
1117
1118 void __init dm365_init_vc(struct snd_platform_data *pdata)
1119 {
1120         davinci_cfg_reg(DM365_EVT2_VC_TX);
1121         davinci_cfg_reg(DM365_EVT3_VC_RX);
1122         dm365_vc_device.dev.platform_data = pdata;
1123         platform_device_register(&dm365_vc_device);
1124 }
1125
1126 void __init dm365_init_ks(struct davinci_ks_platform_data *pdata)
1127 {
1128         dm365_ks_device.dev.platform_data = pdata;
1129         platform_device_register(&dm365_ks_device);
1130 }
1131
1132 void __init dm365_init_rtc(void)
1133 {
1134         davinci_cfg_reg(DM365_INT_PRTCSS);
1135         platform_device_register(&dm365_rtc_device);
1136 }
1137
1138 void __init dm365_init(void)
1139 {
1140         davinci_common_init(&davinci_soc_info_dm365);
1141         davinci_map_sysmod();
1142 }
1143
1144 static struct resource dm365_vpss_resources[] = {
1145         {
1146                 /* VPSS ISP5 Base address */
1147                 .name           = "isp5",
1148                 .start          = 0x01c70000,
1149                 .end            = 0x01c70000 + 0xff,
1150                 .flags          = IORESOURCE_MEM,
1151         },
1152         {
1153                 /* VPSS CLK Base address */
1154                 .name           = "vpss",
1155                 .start          = 0x01c70200,
1156                 .end            = 0x01c70200 + 0xff,
1157                 .flags          = IORESOURCE_MEM,
1158         },
1159 };
1160
1161 static struct platform_device dm365_vpss_device = {
1162        .name                   = "vpss",
1163        .id                     = -1,
1164        .dev.platform_data      = "dm365_vpss",
1165        .num_resources          = ARRAY_SIZE(dm365_vpss_resources),
1166        .resource               = dm365_vpss_resources,
1167 };
1168
1169 static struct resource vpfe_resources[] = {
1170         {
1171                 .start          = IRQ_VDINT0,
1172                 .end            = IRQ_VDINT0,
1173                 .flags          = IORESOURCE_IRQ,
1174         },
1175         {
1176                 .start          = IRQ_VDINT1,
1177                 .end            = IRQ_VDINT1,
1178                 .flags          = IORESOURCE_IRQ,
1179         },
1180 };
1181
1182 static u64 vpfe_capture_dma_mask = DMA_BIT_MASK(32);
1183 static struct platform_device vpfe_capture_dev = {
1184         .name           = CAPTURE_DRV_NAME,
1185         .id             = -1,
1186         .num_resources  = ARRAY_SIZE(vpfe_resources),
1187         .resource       = vpfe_resources,
1188         .dev = {
1189                 .dma_mask               = &vpfe_capture_dma_mask,
1190                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1191         },
1192 };
1193
1194 static void dm365_isif_setup_pinmux(void)
1195 {
1196         davinci_cfg_reg(DM365_VIN_CAM_WEN);
1197         davinci_cfg_reg(DM365_VIN_CAM_VD);
1198         davinci_cfg_reg(DM365_VIN_CAM_HD);
1199         davinci_cfg_reg(DM365_VIN_YIN4_7_EN);
1200         davinci_cfg_reg(DM365_VIN_YIN0_3_EN);
1201 }
1202
1203 static struct resource isif_resource[] = {
1204         /* ISIF Base address */
1205         {
1206                 .start          = 0x01c71000,
1207                 .end            = 0x01c71000 + 0x1ff,
1208                 .flags          = IORESOURCE_MEM,
1209         },
1210         /* ISIF Linearization table 0 */
1211         {
1212                 .start          = 0x1C7C000,
1213                 .end            = 0x1C7C000 + 0x2ff,
1214                 .flags          = IORESOURCE_MEM,
1215         },
1216         /* ISIF Linearization table 1 */
1217         {
1218                 .start          = 0x1C7C400,
1219                 .end            = 0x1C7C400 + 0x2ff,
1220                 .flags          = IORESOURCE_MEM,
1221         },
1222 };
1223 static struct platform_device dm365_isif_dev = {
1224         .name           = "isif",
1225         .id             = -1,
1226         .num_resources  = ARRAY_SIZE(isif_resource),
1227         .resource       = isif_resource,
1228         .dev = {
1229                 .dma_mask               = &vpfe_capture_dma_mask,
1230                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1231                 .platform_data          = dm365_isif_setup_pinmux,
1232         },
1233 };
1234
1235 static int __init dm365_init_devices(void)
1236 {
1237         if (!cpu_is_davinci_dm365())
1238                 return 0;
1239
1240         davinci_cfg_reg(DM365_INT_EDMA_CC);
1241         platform_device_register(&dm365_edma_device);
1242
1243         platform_device_register(&dm365_mdio_device);
1244         platform_device_register(&dm365_emac_device);
1245         clk_add_alias(NULL, dev_name(&dm365_mdio_device.dev),
1246                       NULL, &dm365_emac_device.dev);
1247
1248         /* Add isif clock alias */
1249         clk_add_alias("master", dm365_isif_dev.name, "vpss_master", NULL);
1250         platform_device_register(&dm365_vpss_device);
1251         platform_device_register(&dm365_isif_dev);
1252         platform_device_register(&vpfe_capture_dev);
1253         return 0;
1254 }
1255 postcore_initcall(dm365_init_devices);
1256
1257 void dm365_set_vpfe_config(struct vpfe_config *cfg)
1258 {
1259        vpfe_capture_dev.dev.platform_data = cfg;
1260 }