2 * TI DaVinci DM644x chip specific setup
4 * Author: Kevin Hilman, Deep Root Systems, LLC
6 * 2007 (c) Deep Root Systems, LLC. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
11 #include <linux/init.h>
12 #include <linux/clk.h>
13 #include <linux/serial_8250.h>
14 #include <linux/platform_device.h>
15 #include <linux/gpio.h>
17 #include <asm/mach/map.h>
19 #include <mach/dm644x.h>
20 #include <mach/cputype.h>
21 #include <mach/edma.h>
22 #include <mach/irqs.h>
25 #include <mach/time.h>
26 #include <mach/serial.h>
27 #include <mach/common.h>
34 * Device specific clocks
36 #define DM644X_REF_FREQ 27000000
38 static struct pll_data pll1_data = {
40 .phys_base = DAVINCI_PLL1_BASE,
43 static struct pll_data pll2_data = {
45 .phys_base = DAVINCI_PLL2_BASE,
48 static struct clk ref_clk = {
50 .rate = DM644X_REF_FREQ,
53 static struct clk pll1_clk = {
56 .pll_data = &pll1_data,
60 static struct clk pll1_sysclk1 = {
61 .name = "pll1_sysclk1",
67 static struct clk pll1_sysclk2 = {
68 .name = "pll1_sysclk2",
74 static struct clk pll1_sysclk3 = {
75 .name = "pll1_sysclk3",
81 static struct clk pll1_sysclk5 = {
82 .name = "pll1_sysclk5",
88 static struct clk pll1_aux_clk = {
89 .name = "pll1_aux_clk",
91 .flags = CLK_PLL | PRE_PLL,
94 static struct clk pll1_sysclkbp = {
95 .name = "pll1_sysclkbp",
97 .flags = CLK_PLL | PRE_PLL,
101 static struct clk pll2_clk = {
104 .pll_data = &pll2_data,
108 static struct clk pll2_sysclk1 = {
109 .name = "pll2_sysclk1",
115 static struct clk pll2_sysclk2 = {
116 .name = "pll2_sysclk2",
122 static struct clk pll2_sysclkbp = {
123 .name = "pll2_sysclkbp",
125 .flags = CLK_PLL | PRE_PLL,
129 static struct clk dsp_clk = {
131 .parent = &pll1_sysclk1,
132 .lpsc = DAVINCI_LPSC_GEM,
134 .usecount = 1, /* REVISIT how to disable? */
137 static struct clk arm_clk = {
139 .parent = &pll1_sysclk2,
140 .lpsc = DAVINCI_LPSC_ARM,
141 .flags = ALWAYS_ENABLED,
144 static struct clk vicp_clk = {
146 .parent = &pll1_sysclk2,
147 .lpsc = DAVINCI_LPSC_IMCOP,
149 .usecount = 1, /* REVISIT how to disable? */
152 static struct clk vpss_master_clk = {
153 .name = "vpss_master",
154 .parent = &pll1_sysclk3,
155 .lpsc = DAVINCI_LPSC_VPSSMSTR,
159 static struct clk vpss_slave_clk = {
160 .name = "vpss_slave",
161 .parent = &pll1_sysclk3,
162 .lpsc = DAVINCI_LPSC_VPSSSLV,
165 static struct clk uart0_clk = {
167 .parent = &pll1_aux_clk,
168 .lpsc = DAVINCI_LPSC_UART0,
171 static struct clk uart1_clk = {
173 .parent = &pll1_aux_clk,
174 .lpsc = DAVINCI_LPSC_UART1,
177 static struct clk uart2_clk = {
179 .parent = &pll1_aux_clk,
180 .lpsc = DAVINCI_LPSC_UART2,
183 static struct clk emac_clk = {
185 .parent = &pll1_sysclk5,
186 .lpsc = DAVINCI_LPSC_EMAC_WRAPPER,
189 static struct clk i2c_clk = {
191 .parent = &pll1_aux_clk,
192 .lpsc = DAVINCI_LPSC_I2C,
195 static struct clk ide_clk = {
197 .parent = &pll1_sysclk5,
198 .lpsc = DAVINCI_LPSC_ATA,
201 static struct clk asp_clk = {
203 .parent = &pll1_sysclk5,
204 .lpsc = DAVINCI_LPSC_McBSP,
207 static struct clk mmcsd_clk = {
209 .parent = &pll1_sysclk5,
210 .lpsc = DAVINCI_LPSC_MMC_SD,
213 static struct clk spi_clk = {
215 .parent = &pll1_sysclk5,
216 .lpsc = DAVINCI_LPSC_SPI,
219 static struct clk gpio_clk = {
221 .parent = &pll1_sysclk5,
222 .lpsc = DAVINCI_LPSC_GPIO,
225 static struct clk usb_clk = {
227 .parent = &pll1_sysclk5,
228 .lpsc = DAVINCI_LPSC_USB,
231 static struct clk vlynq_clk = {
233 .parent = &pll1_sysclk5,
234 .lpsc = DAVINCI_LPSC_VLYNQ,
237 static struct clk aemif_clk = {
239 .parent = &pll1_sysclk5,
240 .lpsc = DAVINCI_LPSC_AEMIF,
243 static struct clk pwm0_clk = {
245 .parent = &pll1_aux_clk,
246 .lpsc = DAVINCI_LPSC_PWM0,
249 static struct clk pwm1_clk = {
251 .parent = &pll1_aux_clk,
252 .lpsc = DAVINCI_LPSC_PWM1,
255 static struct clk pwm2_clk = {
257 .parent = &pll1_aux_clk,
258 .lpsc = DAVINCI_LPSC_PWM2,
261 static struct clk timer0_clk = {
263 .parent = &pll1_aux_clk,
264 .lpsc = DAVINCI_LPSC_TIMER0,
267 static struct clk timer1_clk = {
269 .parent = &pll1_aux_clk,
270 .lpsc = DAVINCI_LPSC_TIMER1,
273 static struct clk timer2_clk = {
275 .parent = &pll1_aux_clk,
276 .lpsc = DAVINCI_LPSC_TIMER2,
277 .usecount = 1, /* REVISIT: why cant' this be disabled? */
280 static struct clk_lookup dm644x_clks[] = {
281 CLK(NULL, "ref", &ref_clk),
282 CLK(NULL, "pll1", &pll1_clk),
283 CLK(NULL, "pll1_sysclk1", &pll1_sysclk1),
284 CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
285 CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
286 CLK(NULL, "pll1_sysclk5", &pll1_sysclk5),
287 CLK(NULL, "pll1_aux", &pll1_aux_clk),
288 CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp),
289 CLK(NULL, "pll2", &pll2_clk),
290 CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
291 CLK(NULL, "pll2_sysclk2", &pll2_sysclk2),
292 CLK(NULL, "pll2_sysclkbp", &pll2_sysclkbp),
293 CLK(NULL, "dsp", &dsp_clk),
294 CLK(NULL, "arm", &arm_clk),
295 CLK(NULL, "vicp", &vicp_clk),
296 CLK(NULL, "vpss_master", &vpss_master_clk),
297 CLK(NULL, "vpss_slave", &vpss_slave_clk),
298 CLK(NULL, "arm", &arm_clk),
299 CLK(NULL, "uart0", &uart0_clk),
300 CLK(NULL, "uart1", &uart1_clk),
301 CLK(NULL, "uart2", &uart2_clk),
302 CLK("davinci_emac.1", NULL, &emac_clk),
303 CLK("i2c_davinci.1", NULL, &i2c_clk),
304 CLK("palm_bk3710", NULL, &ide_clk),
305 CLK("davinci-asp", NULL, &asp_clk),
306 CLK("davinci_mmc.0", NULL, &mmcsd_clk),
307 CLK(NULL, "spi", &spi_clk),
308 CLK(NULL, "gpio", &gpio_clk),
309 CLK(NULL, "usb", &usb_clk),
310 CLK(NULL, "vlynq", &vlynq_clk),
311 CLK(NULL, "aemif", &aemif_clk),
312 CLK(NULL, "pwm0", &pwm0_clk),
313 CLK(NULL, "pwm1", &pwm1_clk),
314 CLK(NULL, "pwm2", &pwm2_clk),
315 CLK(NULL, "timer0", &timer0_clk),
316 CLK(NULL, "timer1", &timer1_clk),
317 CLK("watchdog", NULL, &timer2_clk),
318 CLK(NULL, NULL, NULL),
321 static struct emac_platform_data dm644x_emac_pdata = {
322 .ctrl_reg_offset = DM644X_EMAC_CNTRL_OFFSET,
323 .ctrl_mod_reg_offset = DM644X_EMAC_CNTRL_MOD_OFFSET,
324 .ctrl_ram_offset = DM644X_EMAC_CNTRL_RAM_OFFSET,
325 .mdio_reg_offset = DM644X_EMAC_MDIO_OFFSET,
326 .ctrl_ram_size = DM644X_EMAC_CNTRL_RAM_SIZE,
327 .version = EMAC_VERSION_1,
330 static struct resource dm644x_emac_resources[] = {
332 .start = DM644X_EMAC_BASE,
333 .end = DM644X_EMAC_BASE + 0x47ff,
334 .flags = IORESOURCE_MEM,
337 .start = IRQ_EMACINT,
339 .flags = IORESOURCE_IRQ,
343 static struct platform_device dm644x_emac_device = {
344 .name = "davinci_emac",
347 .platform_data = &dm644x_emac_pdata,
349 .num_resources = ARRAY_SIZE(dm644x_emac_resources),
350 .resource = dm644x_emac_resources,
354 * Device specific mux setup
356 * soc description mux mode mode mux dbg
357 * reg offset mask mode
359 static const struct mux_config dm644x_pins[] = {
360 #ifdef CONFIG_DAVINCI_MUX
361 MUX_CFG(DM644X, HDIREN, 0, 16, 1, 1, true)
362 MUX_CFG(DM644X, ATAEN, 0, 17, 1, 1, true)
363 MUX_CFG(DM644X, ATAEN_DISABLE, 0, 17, 1, 0, true)
365 MUX_CFG(DM644X, HPIEN_DISABLE, 0, 29, 1, 0, true)
367 MUX_CFG(DM644X, AEAW, 0, 0, 31, 31, true)
368 MUX_CFG(DM644X, AEAW0, 0, 0, 1, 0, true)
369 MUX_CFG(DM644X, AEAW1, 0, 1, 1, 0, true)
370 MUX_CFG(DM644X, AEAW2, 0, 2, 1, 0, true)
371 MUX_CFG(DM644X, AEAW3, 0, 3, 1, 0, true)
372 MUX_CFG(DM644X, AEAW4, 0, 4, 1, 0, true)
374 MUX_CFG(DM644X, MSTK, 1, 9, 1, 0, false)
376 MUX_CFG(DM644X, I2C, 1, 7, 1, 1, false)
378 MUX_CFG(DM644X, MCBSP, 1, 10, 1, 1, false)
380 MUX_CFG(DM644X, UART1, 1, 1, 1, 1, true)
381 MUX_CFG(DM644X, UART2, 1, 2, 1, 1, true)
383 MUX_CFG(DM644X, PWM0, 1, 4, 1, 1, false)
385 MUX_CFG(DM644X, PWM1, 1, 5, 1, 1, false)
387 MUX_CFG(DM644X, PWM2, 1, 6, 1, 1, false)
389 MUX_CFG(DM644X, VLYNQEN, 0, 15, 1, 1, false)
390 MUX_CFG(DM644X, VLSCREN, 0, 14, 1, 1, false)
391 MUX_CFG(DM644X, VLYNQWD, 0, 12, 3, 3, false)
393 MUX_CFG(DM644X, EMACEN, 0, 31, 1, 1, true)
395 MUX_CFG(DM644X, GPIO3V, 0, 31, 1, 0, true)
397 MUX_CFG(DM644X, GPIO0, 0, 24, 1, 0, true)
398 MUX_CFG(DM644X, GPIO3, 0, 25, 1, 0, false)
399 MUX_CFG(DM644X, GPIO43_44, 1, 7, 1, 0, false)
400 MUX_CFG(DM644X, GPIO46_47, 0, 22, 1, 0, true)
402 MUX_CFG(DM644X, RGB666, 0, 22, 1, 1, true)
404 MUX_CFG(DM644X, LOEEN, 0, 24, 1, 1, true)
405 MUX_CFG(DM644X, LFLDEN, 0, 25, 1, 1, false)
409 /* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
410 static u8 dm644x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
427 [IRQ_CCINT0] = 5, /* dma */
428 [IRQ_CCERRINT] = 5, /* dma */
429 [IRQ_TCERRINT0] = 5, /* dma */
430 [IRQ_TCERRINT] = 5, /* dma */
443 [IRQ_TINT0_TINT12] = 2, /* clockevent */
444 [IRQ_TINT0_TINT34] = 2, /* clocksource */
445 [IRQ_TINT1_TINT12] = 7, /* DSP timer */
446 [IRQ_TINT1_TINT34] = 7, /* system tick */
477 /*----------------------------------------------------------------------*/
480 queue_tc_mapping[][2] = {
481 /* {event queue no, TC no} */
488 queue_priority_mapping[][2] = {
489 /* {event queue no, Priority} */
495 static struct edma_soc_info edma_cc0_info = {
501 .queue_tc_mapping = queue_tc_mapping,
502 .queue_priority_mapping = queue_priority_mapping,
505 static struct edma_soc_info *dm644x_edma_info[EDMA_MAX_CC] = {
509 static struct resource edma_resources[] = {
513 .end = 0x01c00000 + SZ_64K - 1,
514 .flags = IORESOURCE_MEM,
519 .end = 0x01c10000 + SZ_1K - 1,
520 .flags = IORESOURCE_MEM,
525 .end = 0x01c10400 + SZ_1K - 1,
526 .flags = IORESOURCE_MEM,
531 .flags = IORESOURCE_IRQ,
535 .start = IRQ_CCERRINT,
536 .flags = IORESOURCE_IRQ,
538 /* not using TC*_ERR */
541 static struct platform_device dm644x_edma_device = {
544 .dev.platform_data = dm644x_edma_info,
545 .num_resources = ARRAY_SIZE(edma_resources),
546 .resource = edma_resources,
549 /* DM6446 EVM uses ASP0; line-out is a pair of RCA jacks */
550 static struct resource dm644x_asp_resources[] = {
552 .start = DAVINCI_ASP0_BASE,
553 .end = DAVINCI_ASP0_BASE + SZ_8K - 1,
554 .flags = IORESOURCE_MEM,
557 .start = DAVINCI_DMA_ASP0_TX,
558 .end = DAVINCI_DMA_ASP0_TX,
559 .flags = IORESOURCE_DMA,
562 .start = DAVINCI_DMA_ASP0_RX,
563 .end = DAVINCI_DMA_ASP0_RX,
564 .flags = IORESOURCE_DMA,
568 static struct platform_device dm644x_asp_device = {
569 .name = "davinci-asp",
571 .num_resources = ARRAY_SIZE(dm644x_asp_resources),
572 .resource = dm644x_asp_resources,
575 static struct resource dm644x_vpss_resources[] = {
577 /* VPSS Base address */
580 .end = 0x01c73400 + 0xff,
581 .flags = IORESOURCE_MEM,
585 static struct platform_device dm644x_vpss_device = {
588 .dev.platform_data = "dm644x_vpss",
589 .num_resources = ARRAY_SIZE(dm644x_vpss_resources),
590 .resource = dm644x_vpss_resources,
593 static struct resource vpfe_resources[] = {
597 .flags = IORESOURCE_IRQ,
602 .flags = IORESOURCE_IRQ,
606 static u64 vpfe_capture_dma_mask = DMA_BIT_MASK(32);
607 static struct resource dm644x_ccdc_resource[] = {
608 /* CCDC Base address */
611 .end = 0x01c70400 + 0xff,
612 .flags = IORESOURCE_MEM,
616 static struct platform_device dm644x_ccdc_dev = {
617 .name = "dm644x_ccdc",
619 .num_resources = ARRAY_SIZE(dm644x_ccdc_resource),
620 .resource = dm644x_ccdc_resource,
622 .dma_mask = &vpfe_capture_dma_mask,
623 .coherent_dma_mask = DMA_BIT_MASK(32),
627 static struct platform_device vpfe_capture_dev = {
628 .name = CAPTURE_DRV_NAME,
630 .num_resources = ARRAY_SIZE(vpfe_resources),
631 .resource = vpfe_resources,
633 .dma_mask = &vpfe_capture_dma_mask,
634 .coherent_dma_mask = DMA_BIT_MASK(32),
638 void dm644x_set_vpfe_config(struct vpfe_config *cfg)
640 vpfe_capture_dev.dev.platform_data = cfg;
643 /*----------------------------------------------------------------------*/
645 static struct map_desc dm644x_io_desc[] = {
648 .pfn = __phys_to_pfn(IO_PHYS),
653 .virtual = SRAM_VIRT,
654 .pfn = __phys_to_pfn(0x00008000),
656 .type = MT_MEMORY_NONCACHED,
660 /* Contents of JTAG ID register used to identify exact cpu type */
661 static struct davinci_id dm644x_ids[] = {
665 .manufacturer = 0x017,
666 .cpu_id = DAVINCI_CPU_ID_DM6446,
672 .manufacturer = 0x017,
673 .cpu_id = DAVINCI_CPU_ID_DM6446,
678 static u32 dm644x_psc_bases[] = { DAVINCI_PWR_SLEEP_CNTRL_BASE };
681 * T0_BOT: Timer 0, bottom: clockevent source for hrtimers
682 * T0_TOP: Timer 0, top : clocksource for generic timekeeping
683 * T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code)
684 * T1_TOP: Timer 1, top : <unused>
686 static struct davinci_timer_info dm644x_timer_info = {
687 .timers = davinci_timer_instance,
688 .clockevent_id = T0_BOT,
689 .clocksource_id = T0_TOP,
692 static struct plat_serial8250_port dm644x_serial_platform_data[] = {
694 .mapbase = DAVINCI_UART0_BASE,
696 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
702 .mapbase = DAVINCI_UART1_BASE,
704 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
710 .mapbase = DAVINCI_UART2_BASE,
712 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
722 static struct platform_device dm644x_serial_device = {
723 .name = "serial8250",
724 .id = PLAT8250_DEV_PLATFORM,
726 .platform_data = dm644x_serial_platform_data,
730 static struct davinci_soc_info davinci_soc_info_dm644x = {
731 .io_desc = dm644x_io_desc,
732 .io_desc_num = ARRAY_SIZE(dm644x_io_desc),
733 .jtag_id_reg = 0x01c40028,
735 .ids_num = ARRAY_SIZE(dm644x_ids),
736 .cpu_clks = dm644x_clks,
737 .psc_bases = dm644x_psc_bases,
738 .psc_bases_num = ARRAY_SIZE(dm644x_psc_bases),
739 .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
740 .pinmux_pins = dm644x_pins,
741 .pinmux_pins_num = ARRAY_SIZE(dm644x_pins),
742 .intc_base = DAVINCI_ARM_INTC_BASE,
743 .intc_type = DAVINCI_INTC_TYPE_AINTC,
744 .intc_irq_prios = dm644x_default_priorities,
745 .intc_irq_num = DAVINCI_N_AINTC_IRQ,
746 .timer_info = &dm644x_timer_info,
747 .gpio_type = GPIO_TYPE_DAVINCI,
748 .gpio_base = DAVINCI_GPIO_BASE,
750 .gpio_irq = IRQ_GPIOBNK0,
751 .serial_dev = &dm644x_serial_device,
752 .emac_pdata = &dm644x_emac_pdata,
753 .sram_dma = 0x00008000,
755 .reset_device = &davinci_wdt_device,
758 void __init dm644x_init_asp(struct snd_platform_data *pdata)
760 davinci_cfg_reg(DM644X_MCBSP);
761 dm644x_asp_device.dev.platform_data = pdata;
762 platform_device_register(&dm644x_asp_device);
765 void __init dm644x_init(void)
767 davinci_common_init(&davinci_soc_info_dm644x);
770 static int __init dm644x_init_devices(void)
772 if (!cpu_is_davinci_dm644x())
775 /* Add ccdc clock aliases */
776 clk_add_alias("master", dm644x_ccdc_dev.name, "vpss_master", NULL);
777 clk_add_alias("slave", dm644x_ccdc_dev.name, "vpss_slave", NULL);
778 platform_device_register(&dm644x_edma_device);
779 platform_device_register(&dm644x_emac_device);
780 platform_device_register(&dm644x_vpss_device);
781 platform_device_register(&dm644x_ccdc_dev);
782 platform_device_register(&vpfe_capture_dev);
786 postcore_initcall(dm644x_init_devices);