2 * TI DaVinci DM644x chip specific setup
4 * Author: Kevin Hilman, Deep Root Systems, LLC
6 * 2007 (c) Deep Root Systems, LLC. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
11 #include <linux/dma-mapping.h>
12 #include <linux/init.h>
13 #include <linux/clk.h>
14 #include <linux/serial_8250.h>
15 #include <linux/platform_device.h>
16 #include <linux/platform_data/edma.h>
17 #include <linux/platform_data/gpio-davinci.h>
19 #include <asm/mach/map.h>
21 #include <mach/cputype.h>
22 #include <mach/irqs.h>
25 #include <mach/time.h>
26 #include <mach/serial.h>
27 #include <mach/common.h>
34 #define DAVINCI_VPIF_BASE (0x01C12000)
36 #define VDD3P3V_VID_MASK (BIT_MASK(3) | BIT_MASK(2) | BIT_MASK(1) |\
38 #define VSCLKDIS_MASK (BIT_MASK(11) | BIT_MASK(10) | BIT_MASK(9) |\
42 * Device specific clocks
44 #define DM646X_REF_FREQ 27000000
45 #define DM646X_AUX_FREQ 24000000
47 #define DM646X_EMAC_BASE 0x01c80000
48 #define DM646X_EMAC_MDIO_BASE (DM646X_EMAC_BASE + 0x4000)
49 #define DM646X_EMAC_CNTRL_OFFSET 0x0000
50 #define DM646X_EMAC_CNTRL_MOD_OFFSET 0x1000
51 #define DM646X_EMAC_CNTRL_RAM_OFFSET 0x2000
52 #define DM646X_EMAC_CNTRL_RAM_SIZE 0x2000
54 static struct pll_data pll1_data = {
56 .phys_base = DAVINCI_PLL1_BASE,
59 static struct pll_data pll2_data = {
61 .phys_base = DAVINCI_PLL2_BASE,
64 static struct clk ref_clk = {
66 .rate = DM646X_REF_FREQ,
67 .set_rate = davinci_simple_set_rate,
70 static struct clk aux_clkin = {
72 .rate = DM646X_AUX_FREQ,
75 static struct clk pll1_clk = {
78 .pll_data = &pll1_data,
82 static struct clk pll1_sysclk1 = {
83 .name = "pll1_sysclk1",
89 static struct clk pll1_sysclk2 = {
90 .name = "pll1_sysclk2",
96 static struct clk pll1_sysclk3 = {
97 .name = "pll1_sysclk3",
103 static struct clk pll1_sysclk4 = {
104 .name = "pll1_sysclk4",
110 static struct clk pll1_sysclk5 = {
111 .name = "pll1_sysclk5",
117 static struct clk pll1_sysclk6 = {
118 .name = "pll1_sysclk6",
124 static struct clk pll1_sysclk8 = {
125 .name = "pll1_sysclk8",
131 static struct clk pll1_sysclk9 = {
132 .name = "pll1_sysclk9",
138 static struct clk pll1_sysclkbp = {
139 .name = "pll1_sysclkbp",
141 .flags = CLK_PLL | PRE_PLL,
145 static struct clk pll1_aux_clk = {
146 .name = "pll1_aux_clk",
148 .flags = CLK_PLL | PRE_PLL,
151 static struct clk pll2_clk = {
154 .pll_data = &pll2_data,
158 static struct clk pll2_sysclk1 = {
159 .name = "pll2_sysclk1",
165 static struct clk dsp_clk = {
167 .parent = &pll1_sysclk1,
168 .lpsc = DM646X_LPSC_C64X_CPU,
169 .usecount = 1, /* REVISIT how to disable? */
172 static struct clk arm_clk = {
174 .parent = &pll1_sysclk2,
175 .lpsc = DM646X_LPSC_ARM,
176 .flags = ALWAYS_ENABLED,
179 static struct clk edma_cc_clk = {
181 .parent = &pll1_sysclk2,
182 .lpsc = DM646X_LPSC_TPCC,
183 .flags = ALWAYS_ENABLED,
186 static struct clk edma_tc0_clk = {
188 .parent = &pll1_sysclk2,
189 .lpsc = DM646X_LPSC_TPTC0,
190 .flags = ALWAYS_ENABLED,
193 static struct clk edma_tc1_clk = {
195 .parent = &pll1_sysclk2,
196 .lpsc = DM646X_LPSC_TPTC1,
197 .flags = ALWAYS_ENABLED,
200 static struct clk edma_tc2_clk = {
202 .parent = &pll1_sysclk2,
203 .lpsc = DM646X_LPSC_TPTC2,
204 .flags = ALWAYS_ENABLED,
207 static struct clk edma_tc3_clk = {
209 .parent = &pll1_sysclk2,
210 .lpsc = DM646X_LPSC_TPTC3,
211 .flags = ALWAYS_ENABLED,
214 static struct clk uart0_clk = {
216 .parent = &aux_clkin,
217 .lpsc = DM646X_LPSC_UART0,
220 static struct clk uart1_clk = {
222 .parent = &aux_clkin,
223 .lpsc = DM646X_LPSC_UART1,
226 static struct clk uart2_clk = {
228 .parent = &aux_clkin,
229 .lpsc = DM646X_LPSC_UART2,
232 static struct clk i2c_clk = {
234 .parent = &pll1_sysclk3,
235 .lpsc = DM646X_LPSC_I2C,
238 static struct clk gpio_clk = {
240 .parent = &pll1_sysclk3,
241 .lpsc = DM646X_LPSC_GPIO,
244 static struct clk mcasp0_clk = {
246 .parent = &pll1_sysclk3,
247 .lpsc = DM646X_LPSC_McASP0,
250 static struct clk mcasp1_clk = {
252 .parent = &pll1_sysclk3,
253 .lpsc = DM646X_LPSC_McASP1,
256 static struct clk aemif_clk = {
258 .parent = &pll1_sysclk3,
259 .lpsc = DM646X_LPSC_AEMIF,
260 .flags = ALWAYS_ENABLED,
263 static struct clk emac_clk = {
265 .parent = &pll1_sysclk3,
266 .lpsc = DM646X_LPSC_EMAC,
269 static struct clk pwm0_clk = {
271 .parent = &pll1_sysclk3,
272 .lpsc = DM646X_LPSC_PWM0,
273 .usecount = 1, /* REVIST: disabling hangs system */
276 static struct clk pwm1_clk = {
278 .parent = &pll1_sysclk3,
279 .lpsc = DM646X_LPSC_PWM1,
280 .usecount = 1, /* REVIST: disabling hangs system */
283 static struct clk timer0_clk = {
285 .parent = &pll1_sysclk3,
286 .lpsc = DM646X_LPSC_TIMER0,
289 static struct clk timer1_clk = {
291 .parent = &pll1_sysclk3,
292 .lpsc = DM646X_LPSC_TIMER1,
295 static struct clk timer2_clk = {
297 .parent = &pll1_sysclk3,
298 .flags = ALWAYS_ENABLED, /* no LPSC, always enabled; c.f. spruep9a */
302 static struct clk ide_clk = {
304 .parent = &pll1_sysclk4,
305 .lpsc = DAVINCI_LPSC_ATA,
308 static struct clk vpif0_clk = {
311 .lpsc = DM646X_LPSC_VPSSMSTR,
312 .flags = ALWAYS_ENABLED,
315 static struct clk vpif1_clk = {
318 .lpsc = DM646X_LPSC_VPSSSLV,
319 .flags = ALWAYS_ENABLED,
322 static struct clk_lookup dm646x_clks[] = {
323 CLK(NULL, "ref", &ref_clk),
324 CLK(NULL, "aux", &aux_clkin),
325 CLK(NULL, "pll1", &pll1_clk),
326 CLK(NULL, "pll1_sysclk", &pll1_sysclk1),
327 CLK(NULL, "pll1_sysclk", &pll1_sysclk2),
328 CLK(NULL, "pll1_sysclk", &pll1_sysclk3),
329 CLK(NULL, "pll1_sysclk", &pll1_sysclk4),
330 CLK(NULL, "pll1_sysclk", &pll1_sysclk5),
331 CLK(NULL, "pll1_sysclk", &pll1_sysclk6),
332 CLK(NULL, "pll1_sysclk", &pll1_sysclk8),
333 CLK(NULL, "pll1_sysclk", &pll1_sysclk9),
334 CLK(NULL, "pll1_sysclk", &pll1_sysclkbp),
335 CLK(NULL, "pll1_aux", &pll1_aux_clk),
336 CLK(NULL, "pll2", &pll2_clk),
337 CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
338 CLK(NULL, "dsp", &dsp_clk),
339 CLK(NULL, "arm", &arm_clk),
340 CLK(NULL, "edma_cc", &edma_cc_clk),
341 CLK(NULL, "edma_tc0", &edma_tc0_clk),
342 CLK(NULL, "edma_tc1", &edma_tc1_clk),
343 CLK(NULL, "edma_tc2", &edma_tc2_clk),
344 CLK(NULL, "edma_tc3", &edma_tc3_clk),
345 CLK("serial8250.0", NULL, &uart0_clk),
346 CLK("serial8250.1", NULL, &uart1_clk),
347 CLK("serial8250.2", NULL, &uart2_clk),
348 CLK("i2c_davinci.1", NULL, &i2c_clk),
349 CLK(NULL, "gpio", &gpio_clk),
350 CLK("davinci-mcasp.0", NULL, &mcasp0_clk),
351 CLK("davinci-mcasp.1", NULL, &mcasp1_clk),
352 CLK(NULL, "aemif", &aemif_clk),
353 CLK("davinci_emac.1", NULL, &emac_clk),
354 CLK("davinci_mdio.0", "fck", &emac_clk),
355 CLK(NULL, "pwm0", &pwm0_clk),
356 CLK(NULL, "pwm1", &pwm1_clk),
357 CLK(NULL, "timer0", &timer0_clk),
358 CLK(NULL, "timer1", &timer1_clk),
359 CLK("davinci-wdt", NULL, &timer2_clk),
360 CLK("palm_bk3710", NULL, &ide_clk),
361 CLK(NULL, "vpif0", &vpif0_clk),
362 CLK(NULL, "vpif1", &vpif1_clk),
363 CLK(NULL, NULL, NULL),
366 static struct emac_platform_data dm646x_emac_pdata = {
367 .ctrl_reg_offset = DM646X_EMAC_CNTRL_OFFSET,
368 .ctrl_mod_reg_offset = DM646X_EMAC_CNTRL_MOD_OFFSET,
369 .ctrl_ram_offset = DM646X_EMAC_CNTRL_RAM_OFFSET,
370 .ctrl_ram_size = DM646X_EMAC_CNTRL_RAM_SIZE,
371 .version = EMAC_VERSION_2,
374 static struct resource dm646x_emac_resources[] = {
376 .start = DM646X_EMAC_BASE,
377 .end = DM646X_EMAC_BASE + SZ_16K - 1,
378 .flags = IORESOURCE_MEM,
381 .start = IRQ_DM646X_EMACRXTHINT,
382 .end = IRQ_DM646X_EMACRXTHINT,
383 .flags = IORESOURCE_IRQ,
386 .start = IRQ_DM646X_EMACRXINT,
387 .end = IRQ_DM646X_EMACRXINT,
388 .flags = IORESOURCE_IRQ,
391 .start = IRQ_DM646X_EMACTXINT,
392 .end = IRQ_DM646X_EMACTXINT,
393 .flags = IORESOURCE_IRQ,
396 .start = IRQ_DM646X_EMACMISCINT,
397 .end = IRQ_DM646X_EMACMISCINT,
398 .flags = IORESOURCE_IRQ,
402 static struct platform_device dm646x_emac_device = {
403 .name = "davinci_emac",
406 .platform_data = &dm646x_emac_pdata,
408 .num_resources = ARRAY_SIZE(dm646x_emac_resources),
409 .resource = dm646x_emac_resources,
412 static struct resource dm646x_mdio_resources[] = {
414 .start = DM646X_EMAC_MDIO_BASE,
415 .end = DM646X_EMAC_MDIO_BASE + SZ_4K - 1,
416 .flags = IORESOURCE_MEM,
420 static struct platform_device dm646x_mdio_device = {
421 .name = "davinci_mdio",
423 .num_resources = ARRAY_SIZE(dm646x_mdio_resources),
424 .resource = dm646x_mdio_resources,
428 * Device specific mux setup
430 * soc description mux mode mode mux dbg
431 * reg offset mask mode
433 static const struct mux_config dm646x_pins[] = {
434 #ifdef CONFIG_DAVINCI_MUX
435 MUX_CFG(DM646X, ATAEN, 0, 0, 5, 1, true)
437 MUX_CFG(DM646X, AUDCK1, 0, 29, 1, 0, false)
439 MUX_CFG(DM646X, AUDCK0, 0, 28, 1, 0, false)
441 MUX_CFG(DM646X, CRGMUX, 0, 24, 7, 5, true)
443 MUX_CFG(DM646X, STSOMUX_DISABLE, 0, 22, 3, 0, true)
445 MUX_CFG(DM646X, STSIMUX_DISABLE, 0, 20, 3, 0, true)
447 MUX_CFG(DM646X, PTSOMUX_DISABLE, 0, 18, 3, 0, true)
449 MUX_CFG(DM646X, PTSIMUX_DISABLE, 0, 16, 3, 0, true)
451 MUX_CFG(DM646X, STSOMUX, 0, 22, 3, 2, true)
453 MUX_CFG(DM646X, STSIMUX, 0, 20, 3, 2, true)
455 MUX_CFG(DM646X, PTSOMUX_PARALLEL, 0, 18, 3, 2, true)
457 MUX_CFG(DM646X, PTSIMUX_PARALLEL, 0, 16, 3, 2, true)
459 MUX_CFG(DM646X, PTSOMUX_SERIAL, 0, 18, 3, 3, true)
461 MUX_CFG(DM646X, PTSIMUX_SERIAL, 0, 16, 3, 3, true)
465 static u8 dm646x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
466 [IRQ_DM646X_VP_VERTINT0] = 7,
467 [IRQ_DM646X_VP_VERTINT1] = 7,
468 [IRQ_DM646X_VP_VERTINT2] = 7,
469 [IRQ_DM646X_VP_VERTINT3] = 7,
470 [IRQ_DM646X_VP_ERRINT] = 7,
471 [IRQ_DM646X_RESERVED_1] = 7,
472 [IRQ_DM646X_RESERVED_2] = 7,
473 [IRQ_DM646X_WDINT] = 7,
474 [IRQ_DM646X_CRGENINT0] = 7,
475 [IRQ_DM646X_CRGENINT1] = 7,
476 [IRQ_DM646X_TSIFINT0] = 7,
477 [IRQ_DM646X_TSIFINT1] = 7,
478 [IRQ_DM646X_VDCEINT] = 7,
479 [IRQ_DM646X_USBINT] = 7,
480 [IRQ_DM646X_USBDMAINT] = 7,
481 [IRQ_DM646X_PCIINT] = 7,
482 [IRQ_CCINT0] = 7, /* dma */
483 [IRQ_CCERRINT] = 7, /* dma */
484 [IRQ_TCERRINT0] = 7, /* dma */
485 [IRQ_TCERRINT] = 7, /* dma */
486 [IRQ_DM646X_TCERRINT2] = 7,
487 [IRQ_DM646X_TCERRINT3] = 7,
488 [IRQ_DM646X_IDE] = 7,
489 [IRQ_DM646X_HPIINT] = 7,
490 [IRQ_DM646X_EMACRXTHINT] = 7,
491 [IRQ_DM646X_EMACRXINT] = 7,
492 [IRQ_DM646X_EMACTXINT] = 7,
493 [IRQ_DM646X_EMACMISCINT] = 7,
494 [IRQ_DM646X_MCASP0TXINT] = 7,
495 [IRQ_DM646X_MCASP0RXINT] = 7,
497 [IRQ_DM646X_RESERVED_3] = 7,
498 [IRQ_DM646X_MCASP1TXINT] = 7, /* clockevent */
499 [IRQ_TINT0_TINT34] = 7, /* clocksource */
500 [IRQ_TINT1_TINT12] = 7, /* DSP timer */
501 [IRQ_TINT1_TINT34] = 7, /* system tick */
504 [IRQ_DM646X_VLQINT] = 7,
508 [IRQ_DM646X_UARTINT2] = 7,
509 [IRQ_DM646X_SPINT0] = 7,
510 [IRQ_DM646X_SPINT1] = 7,
511 [IRQ_DM646X_DSP2ARMINT] = 7,
512 [IRQ_DM646X_RESERVED_4] = 7,
513 [IRQ_DM646X_PSCINT] = 7,
514 [IRQ_DM646X_GPIO0] = 7,
515 [IRQ_DM646X_GPIO1] = 7,
516 [IRQ_DM646X_GPIO2] = 7,
517 [IRQ_DM646X_GPIO3] = 7,
518 [IRQ_DM646X_GPIO4] = 7,
519 [IRQ_DM646X_GPIO5] = 7,
520 [IRQ_DM646X_GPIO6] = 7,
521 [IRQ_DM646X_GPIO7] = 7,
522 [IRQ_DM646X_GPIOBNK0] = 7,
523 [IRQ_DM646X_GPIOBNK1] = 7,
524 [IRQ_DM646X_GPIOBNK2] = 7,
525 [IRQ_DM646X_DDRINT] = 7,
526 [IRQ_DM646X_AEMIFINT] = 7,
532 /*----------------------------------------------------------------------*/
534 /* Four Transfer Controllers on DM646x */
536 dm646x_queue_priority_mapping[][2] = {
537 /* {event queue no, Priority} */
545 static struct edma_soc_info edma_cc0_info = {
547 .n_region = 6, /* 0-1, 4-7 */
551 .queue_priority_mapping = dm646x_queue_priority_mapping,
552 .default_queue = EVENTQ_1,
555 static struct edma_soc_info *dm646x_edma_info[EDMA_MAX_CC] = {
559 static struct resource edma_resources[] = {
563 .end = 0x01c00000 + SZ_64K - 1,
564 .flags = IORESOURCE_MEM,
569 .end = 0x01c10000 + SZ_1K - 1,
570 .flags = IORESOURCE_MEM,
575 .end = 0x01c10400 + SZ_1K - 1,
576 .flags = IORESOURCE_MEM,
581 .end = 0x01c10800 + SZ_1K - 1,
582 .flags = IORESOURCE_MEM,
587 .end = 0x01c10c00 + SZ_1K - 1,
588 .flags = IORESOURCE_MEM,
593 .flags = IORESOURCE_IRQ,
597 .start = IRQ_CCERRINT,
598 .flags = IORESOURCE_IRQ,
600 /* not using TC*_ERR */
603 static struct platform_device dm646x_edma_device = {
606 .dev.platform_data = dm646x_edma_info,
607 .num_resources = ARRAY_SIZE(edma_resources),
608 .resource = edma_resources,
611 static struct resource dm646x_mcasp0_resources[] = {
614 .start = DAVINCI_DM646X_MCASP0_REG_BASE,
615 .end = DAVINCI_DM646X_MCASP0_REG_BASE + (SZ_1K << 1) - 1,
616 .flags = IORESOURCE_MEM,
618 /* first TX, then RX */
620 .start = DAVINCI_DM646X_DMA_MCASP0_AXEVT0,
621 .end = DAVINCI_DM646X_DMA_MCASP0_AXEVT0,
622 .flags = IORESOURCE_DMA,
625 .start = DAVINCI_DM646X_DMA_MCASP0_AREVT0,
626 .end = DAVINCI_DM646X_DMA_MCASP0_AREVT0,
627 .flags = IORESOURCE_DMA,
631 static struct resource dm646x_mcasp1_resources[] = {
634 .start = DAVINCI_DM646X_MCASP1_REG_BASE,
635 .end = DAVINCI_DM646X_MCASP1_REG_BASE + (SZ_1K << 1) - 1,
636 .flags = IORESOURCE_MEM,
638 /* DIT mode, only TX event */
640 .start = DAVINCI_DM646X_DMA_MCASP1_AXEVT1,
641 .end = DAVINCI_DM646X_DMA_MCASP1_AXEVT1,
642 .flags = IORESOURCE_DMA,
644 /* DIT mode, dummy entry */
648 .flags = IORESOURCE_DMA,
652 static struct platform_device dm646x_mcasp0_device = {
653 .name = "davinci-mcasp",
655 .num_resources = ARRAY_SIZE(dm646x_mcasp0_resources),
656 .resource = dm646x_mcasp0_resources,
659 static struct platform_device dm646x_mcasp1_device = {
660 .name = "davinci-mcasp",
662 .num_resources = ARRAY_SIZE(dm646x_mcasp1_resources),
663 .resource = dm646x_mcasp1_resources,
666 static struct platform_device dm646x_dit_device = {
671 static u64 vpif_dma_mask = DMA_BIT_MASK(32);
673 static struct resource vpif_resource[] = {
675 .start = DAVINCI_VPIF_BASE,
676 .end = DAVINCI_VPIF_BASE + 0x03ff,
677 .flags = IORESOURCE_MEM,
681 static struct platform_device vpif_dev = {
685 .dma_mask = &vpif_dma_mask,
686 .coherent_dma_mask = DMA_BIT_MASK(32),
688 .resource = vpif_resource,
689 .num_resources = ARRAY_SIZE(vpif_resource),
692 static struct resource vpif_display_resource[] = {
694 .start = IRQ_DM646X_VP_VERTINT2,
695 .end = IRQ_DM646X_VP_VERTINT2,
696 .flags = IORESOURCE_IRQ,
699 .start = IRQ_DM646X_VP_VERTINT3,
700 .end = IRQ_DM646X_VP_VERTINT3,
701 .flags = IORESOURCE_IRQ,
705 static struct platform_device vpif_display_dev = {
706 .name = "vpif_display",
709 .dma_mask = &vpif_dma_mask,
710 .coherent_dma_mask = DMA_BIT_MASK(32),
712 .resource = vpif_display_resource,
713 .num_resources = ARRAY_SIZE(vpif_display_resource),
716 static struct resource vpif_capture_resource[] = {
718 .start = IRQ_DM646X_VP_VERTINT0,
719 .end = IRQ_DM646X_VP_VERTINT0,
720 .flags = IORESOURCE_IRQ,
723 .start = IRQ_DM646X_VP_VERTINT1,
724 .end = IRQ_DM646X_VP_VERTINT1,
725 .flags = IORESOURCE_IRQ,
729 static struct platform_device vpif_capture_dev = {
730 .name = "vpif_capture",
733 .dma_mask = &vpif_dma_mask,
734 .coherent_dma_mask = DMA_BIT_MASK(32),
736 .resource = vpif_capture_resource,
737 .num_resources = ARRAY_SIZE(vpif_capture_resource),
740 static struct resource dm646x_gpio_resources[] = {
742 .start = DAVINCI_GPIO_BASE,
743 .end = DAVINCI_GPIO_BASE + SZ_4K - 1,
744 .flags = IORESOURCE_MEM,
747 .start = IRQ_DM646X_GPIOBNK0,
748 .end = IRQ_DM646X_GPIOBNK2,
749 .flags = IORESOURCE_IRQ,
753 static struct davinci_gpio_platform_data dm646x_gpio_platform_data = {
757 int __init dm646x_gpio_register(void)
759 return davinci_gpio_register(dm646x_gpio_resources,
760 ARRAY_SIZE(dm646x_gpio_resources),
761 &dm646x_gpio_platform_data);
763 /*----------------------------------------------------------------------*/
765 static struct map_desc dm646x_io_desc[] = {
768 .pfn = __phys_to_pfn(IO_PHYS),
774 /* Contents of JTAG ID register used to identify exact cpu type */
775 static struct davinci_id dm646x_ids[] = {
779 .manufacturer = 0x017,
780 .cpu_id = DAVINCI_CPU_ID_DM6467,
781 .name = "dm6467_rev1.x",
786 .manufacturer = 0x017,
787 .cpu_id = DAVINCI_CPU_ID_DM6467,
788 .name = "dm6467_rev3.x",
792 static u32 dm646x_psc_bases[] = { DAVINCI_PWR_SLEEP_CNTRL_BASE };
795 * T0_BOT: Timer 0, bottom: clockevent source for hrtimers
796 * T0_TOP: Timer 0, top : clocksource for generic timekeeping
797 * T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code)
798 * T1_TOP: Timer 1, top : <unused>
800 static struct davinci_timer_info dm646x_timer_info = {
801 .timers = davinci_timer_instance,
802 .clockevent_id = T0_BOT,
803 .clocksource_id = T0_TOP,
806 static struct plat_serial8250_port dm646x_serial0_platform_data[] = {
808 .mapbase = DAVINCI_UART0_BASE,
810 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
812 .iotype = UPIO_MEM32,
819 static struct plat_serial8250_port dm646x_serial1_platform_data[] = {
821 .mapbase = DAVINCI_UART1_BASE,
823 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
825 .iotype = UPIO_MEM32,
832 static struct plat_serial8250_port dm646x_serial2_platform_data[] = {
834 .mapbase = DAVINCI_UART2_BASE,
835 .irq = IRQ_DM646X_UARTINT2,
836 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
838 .iotype = UPIO_MEM32,
846 struct platform_device dm646x_serial_device[] = {
848 .name = "serial8250",
849 .id = PLAT8250_DEV_PLATFORM,
851 .platform_data = dm646x_serial0_platform_data,
855 .name = "serial8250",
856 .id = PLAT8250_DEV_PLATFORM1,
858 .platform_data = dm646x_serial1_platform_data,
862 .name = "serial8250",
863 .id = PLAT8250_DEV_PLATFORM2,
865 .platform_data = dm646x_serial2_platform_data,
872 static struct davinci_soc_info davinci_soc_info_dm646x = {
873 .io_desc = dm646x_io_desc,
874 .io_desc_num = ARRAY_SIZE(dm646x_io_desc),
875 .jtag_id_reg = 0x01c40028,
877 .ids_num = ARRAY_SIZE(dm646x_ids),
878 .cpu_clks = dm646x_clks,
879 .psc_bases = dm646x_psc_bases,
880 .psc_bases_num = ARRAY_SIZE(dm646x_psc_bases),
881 .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
882 .pinmux_pins = dm646x_pins,
883 .pinmux_pins_num = ARRAY_SIZE(dm646x_pins),
884 .intc_base = DAVINCI_ARM_INTC_BASE,
885 .intc_type = DAVINCI_INTC_TYPE_AINTC,
886 .intc_irq_prios = dm646x_default_priorities,
887 .intc_irq_num = DAVINCI_N_AINTC_IRQ,
888 .timer_info = &dm646x_timer_info,
889 .emac_pdata = &dm646x_emac_pdata,
890 .sram_dma = 0x10010000,
894 void __init dm646x_init_mcasp0(struct snd_platform_data *pdata)
896 dm646x_mcasp0_device.dev.platform_data = pdata;
897 platform_device_register(&dm646x_mcasp0_device);
900 void __init dm646x_init_mcasp1(struct snd_platform_data *pdata)
902 dm646x_mcasp1_device.dev.platform_data = pdata;
903 platform_device_register(&dm646x_mcasp1_device);
904 platform_device_register(&dm646x_dit_device);
907 void dm646x_setup_vpif(struct vpif_display_config *display_config,
908 struct vpif_capture_config *capture_config)
912 value = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_VSCLKDIS));
913 value &= ~VSCLKDIS_MASK;
914 __raw_writel(value, DAVINCI_SYSMOD_VIRT(SYSMOD_VSCLKDIS));
916 value = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_VDD3P3VPWDN));
917 value &= ~VDD3P3V_VID_MASK;
918 __raw_writel(value, DAVINCI_SYSMOD_VIRT(SYSMOD_VDD3P3VPWDN));
920 davinci_cfg_reg(DM646X_STSOMUX_DISABLE);
921 davinci_cfg_reg(DM646X_STSIMUX_DISABLE);
922 davinci_cfg_reg(DM646X_PTSOMUX_DISABLE);
923 davinci_cfg_reg(DM646X_PTSIMUX_DISABLE);
925 vpif_display_dev.dev.platform_data = display_config;
926 vpif_capture_dev.dev.platform_data = capture_config;
927 platform_device_register(&vpif_dev);
928 platform_device_register(&vpif_display_dev);
929 platform_device_register(&vpif_capture_dev);
932 int __init dm646x_init_edma(struct edma_rsv_info *rsv)
934 edma_cc0_info.rsv = rsv;
936 return platform_device_register(&dm646x_edma_device);
939 void __init dm646x_init(void)
941 davinci_common_init(&davinci_soc_info_dm646x);
942 davinci_map_sysmod();
945 static int __init dm646x_init_devices(void)
949 if (!cpu_is_davinci_dm646x())
952 platform_device_register(&dm646x_mdio_device);
953 platform_device_register(&dm646x_emac_device);
955 ret = davinci_init_wdt();
957 pr_warn("%s: watchdog init failed: %d\n", __func__, ret);
961 postcore_initcall(dm646x_init_devices);