2 * TI DaVinci DM644x chip specific setup
4 * Author: Kevin Hilman, Deep Root Systems, LLC
6 * 2007 (c) Deep Root Systems, LLC. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
11 #include <linux/init.h>
12 #include <linux/clk.h>
13 #include <linux/serial_8250.h>
14 #include <linux/platform_device.h>
15 #include <linux/gpio.h>
17 #include <asm/mach/map.h>
19 #include <mach/dm646x.h>
20 #include <mach/cputype.h>
21 #include <mach/edma.h>
22 #include <mach/irqs.h>
25 #include <mach/time.h>
26 #include <mach/serial.h>
27 #include <mach/common.h>
33 #define DAVINCI_VPIF_BASE (0x01C12000)
34 #define VDD3P3V_PWDN_OFFSET (0x48)
35 #define VSCLKDIS_OFFSET (0x6C)
37 #define VDD3P3V_VID_MASK (BIT_MASK(3) | BIT_MASK(2) | BIT_MASK(1) |\
39 #define VSCLKDIS_MASK (BIT_MASK(11) | BIT_MASK(10) | BIT_MASK(9) |\
43 * Device specific clocks
45 #define DM646X_REF_FREQ 27000000
46 #define DM646X_AUX_FREQ 24000000
48 static struct pll_data pll1_data = {
50 .phys_base = DAVINCI_PLL1_BASE,
53 static struct pll_data pll2_data = {
55 .phys_base = DAVINCI_PLL2_BASE,
58 static struct clk ref_clk = {
60 .rate = DM646X_REF_FREQ,
63 static struct clk aux_clkin = {
65 .rate = DM646X_AUX_FREQ,
68 static struct clk pll1_clk = {
71 .pll_data = &pll1_data,
75 static struct clk pll1_sysclk1 = {
76 .name = "pll1_sysclk1",
82 static struct clk pll1_sysclk2 = {
83 .name = "pll1_sysclk2",
89 static struct clk pll1_sysclk3 = {
90 .name = "pll1_sysclk3",
96 static struct clk pll1_sysclk4 = {
97 .name = "pll1_sysclk4",
103 static struct clk pll1_sysclk5 = {
104 .name = "pll1_sysclk5",
110 static struct clk pll1_sysclk6 = {
111 .name = "pll1_sysclk6",
117 static struct clk pll1_sysclk8 = {
118 .name = "pll1_sysclk8",
124 static struct clk pll1_sysclk9 = {
125 .name = "pll1_sysclk9",
131 static struct clk pll1_sysclkbp = {
132 .name = "pll1_sysclkbp",
134 .flags = CLK_PLL | PRE_PLL,
138 static struct clk pll1_aux_clk = {
139 .name = "pll1_aux_clk",
141 .flags = CLK_PLL | PRE_PLL,
144 static struct clk pll2_clk = {
147 .pll_data = &pll2_data,
151 static struct clk pll2_sysclk1 = {
152 .name = "pll2_sysclk1",
158 static struct clk dsp_clk = {
160 .parent = &pll1_sysclk1,
161 .lpsc = DM646X_LPSC_C64X_CPU,
163 .usecount = 1, /* REVISIT how to disable? */
166 static struct clk arm_clk = {
168 .parent = &pll1_sysclk2,
169 .lpsc = DM646X_LPSC_ARM,
170 .flags = ALWAYS_ENABLED,
173 static struct clk edma_cc_clk = {
175 .parent = &pll1_sysclk2,
176 .lpsc = DM646X_LPSC_TPCC,
177 .flags = ALWAYS_ENABLED,
180 static struct clk edma_tc0_clk = {
182 .parent = &pll1_sysclk2,
183 .lpsc = DM646X_LPSC_TPTC0,
184 .flags = ALWAYS_ENABLED,
187 static struct clk edma_tc1_clk = {
189 .parent = &pll1_sysclk2,
190 .lpsc = DM646X_LPSC_TPTC1,
191 .flags = ALWAYS_ENABLED,
194 static struct clk edma_tc2_clk = {
196 .parent = &pll1_sysclk2,
197 .lpsc = DM646X_LPSC_TPTC2,
198 .flags = ALWAYS_ENABLED,
201 static struct clk edma_tc3_clk = {
203 .parent = &pll1_sysclk2,
204 .lpsc = DM646X_LPSC_TPTC3,
205 .flags = ALWAYS_ENABLED,
208 static struct clk uart0_clk = {
210 .parent = &aux_clkin,
211 .lpsc = DM646X_LPSC_UART0,
214 static struct clk uart1_clk = {
216 .parent = &aux_clkin,
217 .lpsc = DM646X_LPSC_UART1,
220 static struct clk uart2_clk = {
222 .parent = &aux_clkin,
223 .lpsc = DM646X_LPSC_UART2,
226 static struct clk i2c_clk = {
228 .parent = &pll1_sysclk3,
229 .lpsc = DM646X_LPSC_I2C,
232 static struct clk gpio_clk = {
234 .parent = &pll1_sysclk3,
235 .lpsc = DM646X_LPSC_GPIO,
238 static struct clk mcasp0_clk = {
240 .parent = &pll1_sysclk3,
241 .lpsc = DM646X_LPSC_McASP0,
244 static struct clk mcasp1_clk = {
246 .parent = &pll1_sysclk3,
247 .lpsc = DM646X_LPSC_McASP1,
250 static struct clk aemif_clk = {
252 .parent = &pll1_sysclk3,
253 .lpsc = DM646X_LPSC_AEMIF,
254 .flags = ALWAYS_ENABLED,
257 static struct clk emac_clk = {
259 .parent = &pll1_sysclk3,
260 .lpsc = DM646X_LPSC_EMAC,
263 static struct clk pwm0_clk = {
265 .parent = &pll1_sysclk3,
266 .lpsc = DM646X_LPSC_PWM0,
267 .usecount = 1, /* REVIST: disabling hangs system */
270 static struct clk pwm1_clk = {
272 .parent = &pll1_sysclk3,
273 .lpsc = DM646X_LPSC_PWM1,
274 .usecount = 1, /* REVIST: disabling hangs system */
277 static struct clk timer0_clk = {
279 .parent = &pll1_sysclk3,
280 .lpsc = DM646X_LPSC_TIMER0,
283 static struct clk timer1_clk = {
285 .parent = &pll1_sysclk3,
286 .lpsc = DM646X_LPSC_TIMER1,
289 static struct clk timer2_clk = {
291 .parent = &pll1_sysclk3,
292 .flags = ALWAYS_ENABLED, /* no LPSC, always enabled; c.f. spruep9a */
296 static struct clk ide_clk = {
298 .parent = &pll1_sysclk4,
299 .lpsc = DAVINCI_LPSC_ATA,
302 static struct clk vpif0_clk = {
305 .lpsc = DM646X_LPSC_VPSSMSTR,
306 .flags = ALWAYS_ENABLED,
309 static struct clk vpif1_clk = {
312 .lpsc = DM646X_LPSC_VPSSSLV,
313 .flags = ALWAYS_ENABLED,
316 struct davinci_clk dm646x_clks[] = {
317 CLK(NULL, "ref", &ref_clk),
318 CLK(NULL, "aux", &aux_clkin),
319 CLK(NULL, "pll1", &pll1_clk),
320 CLK(NULL, "pll1_sysclk", &pll1_sysclk1),
321 CLK(NULL, "pll1_sysclk", &pll1_sysclk2),
322 CLK(NULL, "pll1_sysclk", &pll1_sysclk3),
323 CLK(NULL, "pll1_sysclk", &pll1_sysclk4),
324 CLK(NULL, "pll1_sysclk", &pll1_sysclk5),
325 CLK(NULL, "pll1_sysclk", &pll1_sysclk6),
326 CLK(NULL, "pll1_sysclk", &pll1_sysclk8),
327 CLK(NULL, "pll1_sysclk", &pll1_sysclk9),
328 CLK(NULL, "pll1_sysclk", &pll1_sysclkbp),
329 CLK(NULL, "pll1_aux", &pll1_aux_clk),
330 CLK(NULL, "pll2", &pll2_clk),
331 CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
332 CLK(NULL, "dsp", &dsp_clk),
333 CLK(NULL, "arm", &arm_clk),
334 CLK(NULL, "edma_cc", &edma_cc_clk),
335 CLK(NULL, "edma_tc0", &edma_tc0_clk),
336 CLK(NULL, "edma_tc1", &edma_tc1_clk),
337 CLK(NULL, "edma_tc2", &edma_tc2_clk),
338 CLK(NULL, "edma_tc3", &edma_tc3_clk),
339 CLK(NULL, "uart0", &uart0_clk),
340 CLK(NULL, "uart1", &uart1_clk),
341 CLK(NULL, "uart2", &uart2_clk),
342 CLK("i2c_davinci.1", NULL, &i2c_clk),
343 CLK(NULL, "gpio", &gpio_clk),
344 CLK("davinci-mcasp.0", NULL, &mcasp0_clk),
345 CLK("davinci-mcasp.1", NULL, &mcasp1_clk),
346 CLK(NULL, "aemif", &aemif_clk),
347 CLK("davinci_emac.1", NULL, &emac_clk),
348 CLK(NULL, "pwm0", &pwm0_clk),
349 CLK(NULL, "pwm1", &pwm1_clk),
350 CLK(NULL, "timer0", &timer0_clk),
351 CLK(NULL, "timer1", &timer1_clk),
352 CLK("watchdog", NULL, &timer2_clk),
353 CLK("palm_bk3710", NULL, &ide_clk),
354 CLK(NULL, "vpif0", &vpif0_clk),
355 CLK(NULL, "vpif1", &vpif1_clk),
356 CLK(NULL, NULL, NULL),
359 static struct emac_platform_data dm646x_emac_pdata = {
360 .ctrl_reg_offset = DM646X_EMAC_CNTRL_OFFSET,
361 .ctrl_mod_reg_offset = DM646X_EMAC_CNTRL_MOD_OFFSET,
362 .ctrl_ram_offset = DM646X_EMAC_CNTRL_RAM_OFFSET,
363 .mdio_reg_offset = DM646X_EMAC_MDIO_OFFSET,
364 .ctrl_ram_size = DM646X_EMAC_CNTRL_RAM_SIZE,
365 .version = EMAC_VERSION_2,
368 static struct resource dm646x_emac_resources[] = {
370 .start = DM646X_EMAC_BASE,
371 .end = DM646X_EMAC_BASE + 0x47ff,
372 .flags = IORESOURCE_MEM,
375 .start = IRQ_DM646X_EMACRXTHINT,
376 .end = IRQ_DM646X_EMACRXTHINT,
377 .flags = IORESOURCE_IRQ,
380 .start = IRQ_DM646X_EMACRXINT,
381 .end = IRQ_DM646X_EMACRXINT,
382 .flags = IORESOURCE_IRQ,
385 .start = IRQ_DM646X_EMACTXINT,
386 .end = IRQ_DM646X_EMACTXINT,
387 .flags = IORESOURCE_IRQ,
390 .start = IRQ_DM646X_EMACMISCINT,
391 .end = IRQ_DM646X_EMACMISCINT,
392 .flags = IORESOURCE_IRQ,
396 static struct platform_device dm646x_emac_device = {
397 .name = "davinci_emac",
400 .platform_data = &dm646x_emac_pdata,
402 .num_resources = ARRAY_SIZE(dm646x_emac_resources),
403 .resource = dm646x_emac_resources,
410 * Device specific mux setup
412 * soc description mux mode mode mux dbg
413 * reg offset mask mode
415 static const struct mux_config dm646x_pins[] = {
416 #ifdef CONFIG_DAVINCI_MUX
417 MUX_CFG(DM646X, ATAEN, 0, 0, 5, 1, true)
419 MUX_CFG(DM646X, AUDCK1, 0, 29, 1, 0, false)
421 MUX_CFG(DM646X, AUDCK0, 0, 28, 1, 0, false)
423 MUX_CFG(DM646X, CRGMUX, 0, 24, 7, 5, true)
425 MUX_CFG(DM646X, STSOMUX_DISABLE, 0, 22, 3, 0, true)
427 MUX_CFG(DM646X, STSIMUX_DISABLE, 0, 20, 3, 0, true)
429 MUX_CFG(DM646X, PTSOMUX_DISABLE, 0, 18, 3, 0, true)
431 MUX_CFG(DM646X, PTSIMUX_DISABLE, 0, 16, 3, 0, true)
433 MUX_CFG(DM646X, STSOMUX, 0, 22, 3, 2, true)
435 MUX_CFG(DM646X, STSIMUX, 0, 20, 3, 2, true)
437 MUX_CFG(DM646X, PTSOMUX_PARALLEL, 0, 18, 3, 2, true)
439 MUX_CFG(DM646X, PTSIMUX_PARALLEL, 0, 16, 3, 2, true)
441 MUX_CFG(DM646X, PTSOMUX_SERIAL, 0, 18, 3, 3, true)
443 MUX_CFG(DM646X, PTSIMUX_SERIAL, 0, 16, 3, 3, true)
447 static u8 dm646x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
448 [IRQ_DM646X_VP_VERTINT0] = 7,
449 [IRQ_DM646X_VP_VERTINT1] = 7,
450 [IRQ_DM646X_VP_VERTINT2] = 7,
451 [IRQ_DM646X_VP_VERTINT3] = 7,
452 [IRQ_DM646X_VP_ERRINT] = 7,
453 [IRQ_DM646X_RESERVED_1] = 7,
454 [IRQ_DM646X_RESERVED_2] = 7,
455 [IRQ_DM646X_WDINT] = 7,
456 [IRQ_DM646X_CRGENINT0] = 7,
457 [IRQ_DM646X_CRGENINT1] = 7,
458 [IRQ_DM646X_TSIFINT0] = 7,
459 [IRQ_DM646X_TSIFINT1] = 7,
460 [IRQ_DM646X_VDCEINT] = 7,
461 [IRQ_DM646X_USBINT] = 7,
462 [IRQ_DM646X_USBDMAINT] = 7,
463 [IRQ_DM646X_PCIINT] = 7,
464 [IRQ_CCINT0] = 7, /* dma */
465 [IRQ_CCERRINT] = 7, /* dma */
466 [IRQ_TCERRINT0] = 7, /* dma */
467 [IRQ_TCERRINT] = 7, /* dma */
468 [IRQ_DM646X_TCERRINT2] = 7,
469 [IRQ_DM646X_TCERRINT3] = 7,
470 [IRQ_DM646X_IDE] = 7,
471 [IRQ_DM646X_HPIINT] = 7,
472 [IRQ_DM646X_EMACRXTHINT] = 7,
473 [IRQ_DM646X_EMACRXINT] = 7,
474 [IRQ_DM646X_EMACTXINT] = 7,
475 [IRQ_DM646X_EMACMISCINT] = 7,
476 [IRQ_DM646X_MCASP0TXINT] = 7,
477 [IRQ_DM646X_MCASP0RXINT] = 7,
479 [IRQ_DM646X_RESERVED_3] = 7,
480 [IRQ_DM646X_MCASP1TXINT] = 7, /* clockevent */
481 [IRQ_TINT0_TINT34] = 7, /* clocksource */
482 [IRQ_TINT1_TINT12] = 7, /* DSP timer */
483 [IRQ_TINT1_TINT34] = 7, /* system tick */
486 [IRQ_DM646X_VLQINT] = 7,
490 [IRQ_DM646X_UARTINT2] = 7,
491 [IRQ_DM646X_SPINT0] = 7,
492 [IRQ_DM646X_SPINT1] = 7,
493 [IRQ_DM646X_DSP2ARMINT] = 7,
494 [IRQ_DM646X_RESERVED_4] = 7,
495 [IRQ_DM646X_PSCINT] = 7,
496 [IRQ_DM646X_GPIO0] = 7,
497 [IRQ_DM646X_GPIO1] = 7,
498 [IRQ_DM646X_GPIO2] = 7,
499 [IRQ_DM646X_GPIO3] = 7,
500 [IRQ_DM646X_GPIO4] = 7,
501 [IRQ_DM646X_GPIO5] = 7,
502 [IRQ_DM646X_GPIO6] = 7,
503 [IRQ_DM646X_GPIO7] = 7,
504 [IRQ_DM646X_GPIOBNK0] = 7,
505 [IRQ_DM646X_GPIOBNK1] = 7,
506 [IRQ_DM646X_GPIOBNK2] = 7,
507 [IRQ_DM646X_DDRINT] = 7,
508 [IRQ_DM646X_AEMIFINT] = 7,
514 /*----------------------------------------------------------------------*/
516 static const s8 dma_chan_dm646x_no_event[] = {
524 /* Four Transfer Controllers on DM646x */
526 dm646x_queue_tc_mapping[][2] = {
527 /* {event queue no, TC no} */
536 dm646x_queue_priority_mapping[][2] = {
537 /* {event queue no, Priority} */
545 static struct edma_soc_info dm646x_edma_info[] = {
548 .n_region = 6, /* 0-1, 4-7 */
552 .noevent = dma_chan_dm646x_no_event,
553 .queue_tc_mapping = dm646x_queue_tc_mapping,
554 .queue_priority_mapping = dm646x_queue_priority_mapping,
558 static struct resource edma_resources[] = {
562 .end = 0x01c00000 + SZ_64K - 1,
563 .flags = IORESOURCE_MEM,
568 .end = 0x01c10000 + SZ_1K - 1,
569 .flags = IORESOURCE_MEM,
574 .end = 0x01c10400 + SZ_1K - 1,
575 .flags = IORESOURCE_MEM,
580 .end = 0x01c10800 + SZ_1K - 1,
581 .flags = IORESOURCE_MEM,
586 .end = 0x01c10c00 + SZ_1K - 1,
587 .flags = IORESOURCE_MEM,
592 .flags = IORESOURCE_IRQ,
596 .start = IRQ_CCERRINT,
597 .flags = IORESOURCE_IRQ,
599 /* not using TC*_ERR */
602 static struct platform_device dm646x_edma_device = {
605 .dev.platform_data = dm646x_edma_info,
606 .num_resources = ARRAY_SIZE(edma_resources),
607 .resource = edma_resources,
610 static struct resource ide_resources[] = {
612 .start = DM646X_ATA_REG_BASE,
613 .end = DM646X_ATA_REG_BASE + 0x7ff,
614 .flags = IORESOURCE_MEM,
617 .start = IRQ_DM646X_IDE,
618 .end = IRQ_DM646X_IDE,
619 .flags = IORESOURCE_IRQ,
623 static u64 ide_dma_mask = DMA_BIT_MASK(32);
625 static struct platform_device ide_dev = {
626 .name = "palm_bk3710",
628 .resource = ide_resources,
629 .num_resources = ARRAY_SIZE(ide_resources),
631 .dma_mask = &ide_dma_mask,
632 .coherent_dma_mask = DMA_BIT_MASK(32),
636 static struct resource dm646x_mcasp0_resources[] = {
639 .start = DAVINCI_DM646X_MCASP0_REG_BASE,
640 .end = DAVINCI_DM646X_MCASP0_REG_BASE + (SZ_1K << 1) - 1,
641 .flags = IORESOURCE_MEM,
643 /* first TX, then RX */
645 .start = DAVINCI_DM646X_DMA_MCASP0_AXEVT0,
646 .end = DAVINCI_DM646X_DMA_MCASP0_AXEVT0,
647 .flags = IORESOURCE_DMA,
650 .start = DAVINCI_DM646X_DMA_MCASP0_AREVT0,
651 .end = DAVINCI_DM646X_DMA_MCASP0_AREVT0,
652 .flags = IORESOURCE_DMA,
656 static struct resource dm646x_mcasp1_resources[] = {
659 .start = DAVINCI_DM646X_MCASP1_REG_BASE,
660 .end = DAVINCI_DM646X_MCASP1_REG_BASE + (SZ_1K << 1) - 1,
661 .flags = IORESOURCE_MEM,
663 /* DIT mode, only TX event */
665 .start = DAVINCI_DM646X_DMA_MCASP1_AXEVT1,
666 .end = DAVINCI_DM646X_DMA_MCASP1_AXEVT1,
667 .flags = IORESOURCE_DMA,
669 /* DIT mode, dummy entry */
673 .flags = IORESOURCE_DMA,
677 static struct platform_device dm646x_mcasp0_device = {
678 .name = "davinci-mcasp",
680 .num_resources = ARRAY_SIZE(dm646x_mcasp0_resources),
681 .resource = dm646x_mcasp0_resources,
684 static struct platform_device dm646x_mcasp1_device = {
685 .name = "davinci-mcasp",
687 .num_resources = ARRAY_SIZE(dm646x_mcasp1_resources),
688 .resource = dm646x_mcasp1_resources,
691 static struct platform_device dm646x_dit_device = {
696 static u64 vpif_dma_mask = DMA_BIT_MASK(32);
698 static struct resource vpif_resource[] = {
700 .start = DAVINCI_VPIF_BASE,
701 .end = DAVINCI_VPIF_BASE + 0x03ff,
702 .flags = IORESOURCE_MEM,
706 static struct platform_device vpif_dev = {
710 .dma_mask = &vpif_dma_mask,
711 .coherent_dma_mask = DMA_BIT_MASK(32),
713 .resource = vpif_resource,
714 .num_resources = ARRAY_SIZE(vpif_resource),
717 static struct resource vpif_display_resource[] = {
719 .start = IRQ_DM646X_VP_VERTINT2,
720 .end = IRQ_DM646X_VP_VERTINT2,
721 .flags = IORESOURCE_IRQ,
724 .start = IRQ_DM646X_VP_VERTINT3,
725 .end = IRQ_DM646X_VP_VERTINT3,
726 .flags = IORESOURCE_IRQ,
730 static struct platform_device vpif_display_dev = {
731 .name = "vpif_display",
734 .dma_mask = &vpif_dma_mask,
735 .coherent_dma_mask = DMA_BIT_MASK(32),
737 .resource = vpif_display_resource,
738 .num_resources = ARRAY_SIZE(vpif_display_resource),
741 static struct resource vpif_capture_resource[] = {
743 .start = IRQ_DM646X_VP_VERTINT0,
744 .end = IRQ_DM646X_VP_VERTINT0,
745 .flags = IORESOURCE_IRQ,
748 .start = IRQ_DM646X_VP_VERTINT1,
749 .end = IRQ_DM646X_VP_VERTINT1,
750 .flags = IORESOURCE_IRQ,
754 static struct platform_device vpif_capture_dev = {
755 .name = "vpif_capture",
758 .dma_mask = &vpif_dma_mask,
759 .coherent_dma_mask = DMA_BIT_MASK(32),
761 .resource = vpif_capture_resource,
762 .num_resources = ARRAY_SIZE(vpif_capture_resource),
765 /*----------------------------------------------------------------------*/
767 static struct map_desc dm646x_io_desc[] = {
770 .pfn = __phys_to_pfn(IO_PHYS),
775 .virtual = SRAM_VIRT,
776 .pfn = __phys_to_pfn(0x00010000),
778 /* MT_MEMORY_NONCACHED requires supersection alignment */
783 /* Contents of JTAG ID register used to identify exact cpu type */
784 static struct davinci_id dm646x_ids[] = {
788 .manufacturer = 0x017,
789 .cpu_id = DAVINCI_CPU_ID_DM6467,
790 .name = "dm6467_rev1.x",
795 .manufacturer = 0x017,
796 .cpu_id = DAVINCI_CPU_ID_DM6467,
797 .name = "dm6467_rev3.x",
801 static void __iomem *dm646x_psc_bases[] = {
802 IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE),
806 * T0_BOT: Timer 0, bottom: clockevent source for hrtimers
807 * T0_TOP: Timer 0, top : clocksource for generic timekeeping
808 * T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code)
809 * T1_TOP: Timer 1, top : <unused>
811 struct davinci_timer_info dm646x_timer_info = {
812 .timers = davinci_timer_instance,
813 .clockevent_id = T0_BOT,
814 .clocksource_id = T0_TOP,
817 static struct plat_serial8250_port dm646x_serial_platform_data[] = {
819 .mapbase = DAVINCI_UART0_BASE,
821 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
823 .iotype = UPIO_MEM32,
827 .mapbase = DAVINCI_UART1_BASE,
829 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
831 .iotype = UPIO_MEM32,
835 .mapbase = DAVINCI_UART2_BASE,
836 .irq = IRQ_DM646X_UARTINT2,
837 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
839 .iotype = UPIO_MEM32,
847 static struct platform_device dm646x_serial_device = {
848 .name = "serial8250",
849 .id = PLAT8250_DEV_PLATFORM,
851 .platform_data = dm646x_serial_platform_data,
855 static struct davinci_soc_info davinci_soc_info_dm646x = {
856 .io_desc = dm646x_io_desc,
857 .io_desc_num = ARRAY_SIZE(dm646x_io_desc),
858 .jtag_id_base = IO_ADDRESS(0x01c40028),
860 .ids_num = ARRAY_SIZE(dm646x_ids),
861 .cpu_clks = dm646x_clks,
862 .psc_bases = dm646x_psc_bases,
863 .psc_bases_num = ARRAY_SIZE(dm646x_psc_bases),
864 .pinmux_base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE),
865 .pinmux_pins = dm646x_pins,
866 .pinmux_pins_num = ARRAY_SIZE(dm646x_pins),
867 .intc_base = IO_ADDRESS(DAVINCI_ARM_INTC_BASE),
868 .intc_type = DAVINCI_INTC_TYPE_AINTC,
869 .intc_irq_prios = dm646x_default_priorities,
870 .intc_irq_num = DAVINCI_N_AINTC_IRQ,
871 .timer_info = &dm646x_timer_info,
872 .gpio_base = IO_ADDRESS(DAVINCI_GPIO_BASE),
873 .gpio_num = 43, /* Only 33 usable */
874 .gpio_irq = IRQ_DM646X_GPIOBNK0,
875 .serial_dev = &dm646x_serial_device,
876 .emac_pdata = &dm646x_emac_pdata,
877 .sram_dma = 0x10010000,
881 void __init dm646x_init_ide()
883 davinci_cfg_reg(DM646X_ATAEN);
884 platform_device_register(&ide_dev);
887 void __init dm646x_init_mcasp0(struct snd_platform_data *pdata)
889 dm646x_mcasp0_device.dev.platform_data = pdata;
890 platform_device_register(&dm646x_mcasp0_device);
893 void __init dm646x_init_mcasp1(struct snd_platform_data *pdata)
895 dm646x_mcasp1_device.dev.platform_data = pdata;
896 platform_device_register(&dm646x_mcasp1_device);
897 platform_device_register(&dm646x_dit_device);
900 void dm646x_setup_vpif(struct vpif_display_config *display_config,
901 struct vpif_capture_config *capture_config)
904 void __iomem *base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE);
906 value = __raw_readl(base + VSCLKDIS_OFFSET);
907 value &= ~VSCLKDIS_MASK;
908 __raw_writel(value, base + VSCLKDIS_OFFSET);
910 value = __raw_readl(base + VDD3P3V_PWDN_OFFSET);
911 value &= ~VDD3P3V_VID_MASK;
912 __raw_writel(value, base + VDD3P3V_PWDN_OFFSET);
914 davinci_cfg_reg(DM646X_STSOMUX_DISABLE);
915 davinci_cfg_reg(DM646X_STSIMUX_DISABLE);
916 davinci_cfg_reg(DM646X_PTSOMUX_DISABLE);
917 davinci_cfg_reg(DM646X_PTSIMUX_DISABLE);
919 vpif_display_dev.dev.platform_data = display_config;
920 vpif_capture_dev.dev.platform_data = capture_config;
921 platform_device_register(&vpif_dev);
922 platform_device_register(&vpif_display_dev);
923 platform_device_register(&vpif_capture_dev);
926 void __init dm646x_init(void)
928 davinci_common_init(&davinci_soc_info_dm646x);
931 static int __init dm646x_init_devices(void)
933 if (!cpu_is_davinci_dm646x())
936 platform_device_register(&dm646x_edma_device);
937 platform_device_register(&dm646x_emac_device);
940 postcore_initcall(dm646x_init_devices);