2 * TI DaVinci DM644x chip specific setup
4 * Author: Kevin Hilman, Deep Root Systems, LLC
6 * 2007 (c) Deep Root Systems, LLC. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
11 #include <linux/init.h>
12 #include <linux/clk.h>
13 #include <linux/serial_8250.h>
14 #include <linux/platform_device.h>
15 #include <linux/gpio.h>
17 #include <asm/mach/map.h>
19 #include <mach/dm646x.h>
20 #include <mach/cputype.h>
21 #include <mach/edma.h>
22 #include <mach/irqs.h>
25 #include <mach/time.h>
26 #include <mach/serial.h>
27 #include <mach/common.h>
33 #define DAVINCI_VPIF_BASE (0x01C12000)
34 #define VDD3P3V_PWDN_OFFSET (0x48)
35 #define VSCLKDIS_OFFSET (0x6C)
37 #define VDD3P3V_VID_MASK (BIT_MASK(3) | BIT_MASK(2) | BIT_MASK(1) |\
39 #define VSCLKDIS_MASK (BIT_MASK(11) | BIT_MASK(10) | BIT_MASK(9) |\
43 * Device specific clocks
45 #define DM646X_AUX_FREQ 24000000
47 static struct pll_data pll1_data = {
49 .phys_base = DAVINCI_PLL1_BASE,
52 static struct pll_data pll2_data = {
54 .phys_base = DAVINCI_PLL2_BASE,
57 static struct clk ref_clk = {
61 static struct clk aux_clkin = {
63 .rate = DM646X_AUX_FREQ,
66 static struct clk pll1_clk = {
69 .pll_data = &pll1_data,
73 static struct clk pll1_sysclk1 = {
74 .name = "pll1_sysclk1",
80 static struct clk pll1_sysclk2 = {
81 .name = "pll1_sysclk2",
87 static struct clk pll1_sysclk3 = {
88 .name = "pll1_sysclk3",
94 static struct clk pll1_sysclk4 = {
95 .name = "pll1_sysclk4",
101 static struct clk pll1_sysclk5 = {
102 .name = "pll1_sysclk5",
108 static struct clk pll1_sysclk6 = {
109 .name = "pll1_sysclk6",
115 static struct clk pll1_sysclk8 = {
116 .name = "pll1_sysclk8",
122 static struct clk pll1_sysclk9 = {
123 .name = "pll1_sysclk9",
129 static struct clk pll1_sysclkbp = {
130 .name = "pll1_sysclkbp",
132 .flags = CLK_PLL | PRE_PLL,
136 static struct clk pll1_aux_clk = {
137 .name = "pll1_aux_clk",
139 .flags = CLK_PLL | PRE_PLL,
142 static struct clk pll2_clk = {
145 .pll_data = &pll2_data,
149 static struct clk pll2_sysclk1 = {
150 .name = "pll2_sysclk1",
156 static struct clk dsp_clk = {
158 .parent = &pll1_sysclk1,
159 .lpsc = DM646X_LPSC_C64X_CPU,
161 .usecount = 1, /* REVISIT how to disable? */
164 static struct clk arm_clk = {
166 .parent = &pll1_sysclk2,
167 .lpsc = DM646X_LPSC_ARM,
168 .flags = ALWAYS_ENABLED,
171 static struct clk edma_cc_clk = {
173 .parent = &pll1_sysclk2,
174 .lpsc = DM646X_LPSC_TPCC,
175 .flags = ALWAYS_ENABLED,
178 static struct clk edma_tc0_clk = {
180 .parent = &pll1_sysclk2,
181 .lpsc = DM646X_LPSC_TPTC0,
182 .flags = ALWAYS_ENABLED,
185 static struct clk edma_tc1_clk = {
187 .parent = &pll1_sysclk2,
188 .lpsc = DM646X_LPSC_TPTC1,
189 .flags = ALWAYS_ENABLED,
192 static struct clk edma_tc2_clk = {
194 .parent = &pll1_sysclk2,
195 .lpsc = DM646X_LPSC_TPTC2,
196 .flags = ALWAYS_ENABLED,
199 static struct clk edma_tc3_clk = {
201 .parent = &pll1_sysclk2,
202 .lpsc = DM646X_LPSC_TPTC3,
203 .flags = ALWAYS_ENABLED,
206 static struct clk uart0_clk = {
208 .parent = &aux_clkin,
209 .lpsc = DM646X_LPSC_UART0,
212 static struct clk uart1_clk = {
214 .parent = &aux_clkin,
215 .lpsc = DM646X_LPSC_UART1,
218 static struct clk uart2_clk = {
220 .parent = &aux_clkin,
221 .lpsc = DM646X_LPSC_UART2,
224 static struct clk i2c_clk = {
226 .parent = &pll1_sysclk3,
227 .lpsc = DM646X_LPSC_I2C,
230 static struct clk gpio_clk = {
232 .parent = &pll1_sysclk3,
233 .lpsc = DM646X_LPSC_GPIO,
236 static struct clk mcasp0_clk = {
238 .parent = &pll1_sysclk3,
239 .lpsc = DM646X_LPSC_McASP0,
242 static struct clk mcasp1_clk = {
244 .parent = &pll1_sysclk3,
245 .lpsc = DM646X_LPSC_McASP1,
248 static struct clk aemif_clk = {
250 .parent = &pll1_sysclk3,
251 .lpsc = DM646X_LPSC_AEMIF,
252 .flags = ALWAYS_ENABLED,
255 static struct clk emac_clk = {
257 .parent = &pll1_sysclk3,
258 .lpsc = DM646X_LPSC_EMAC,
261 static struct clk pwm0_clk = {
263 .parent = &pll1_sysclk3,
264 .lpsc = DM646X_LPSC_PWM0,
265 .usecount = 1, /* REVIST: disabling hangs system */
268 static struct clk pwm1_clk = {
270 .parent = &pll1_sysclk3,
271 .lpsc = DM646X_LPSC_PWM1,
272 .usecount = 1, /* REVIST: disabling hangs system */
275 static struct clk timer0_clk = {
277 .parent = &pll1_sysclk3,
278 .lpsc = DM646X_LPSC_TIMER0,
281 static struct clk timer1_clk = {
283 .parent = &pll1_sysclk3,
284 .lpsc = DM646X_LPSC_TIMER1,
287 static struct clk timer2_clk = {
289 .parent = &pll1_sysclk3,
290 .flags = ALWAYS_ENABLED, /* no LPSC, always enabled; c.f. spruep9a */
294 static struct clk ide_clk = {
296 .parent = &pll1_sysclk4,
297 .lpsc = DAVINCI_LPSC_ATA,
300 static struct clk vpif0_clk = {
303 .lpsc = DM646X_LPSC_VPSSMSTR,
304 .flags = ALWAYS_ENABLED,
307 static struct clk vpif1_clk = {
310 .lpsc = DM646X_LPSC_VPSSSLV,
311 .flags = ALWAYS_ENABLED,
314 struct clk_lookup dm646x_clks[] = {
315 CLK(NULL, "ref", &ref_clk),
316 CLK(NULL, "aux", &aux_clkin),
317 CLK(NULL, "pll1", &pll1_clk),
318 CLK(NULL, "pll1_sysclk", &pll1_sysclk1),
319 CLK(NULL, "pll1_sysclk", &pll1_sysclk2),
320 CLK(NULL, "pll1_sysclk", &pll1_sysclk3),
321 CLK(NULL, "pll1_sysclk", &pll1_sysclk4),
322 CLK(NULL, "pll1_sysclk", &pll1_sysclk5),
323 CLK(NULL, "pll1_sysclk", &pll1_sysclk6),
324 CLK(NULL, "pll1_sysclk", &pll1_sysclk8),
325 CLK(NULL, "pll1_sysclk", &pll1_sysclk9),
326 CLK(NULL, "pll1_sysclk", &pll1_sysclkbp),
327 CLK(NULL, "pll1_aux", &pll1_aux_clk),
328 CLK(NULL, "pll2", &pll2_clk),
329 CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
330 CLK(NULL, "dsp", &dsp_clk),
331 CLK(NULL, "arm", &arm_clk),
332 CLK(NULL, "edma_cc", &edma_cc_clk),
333 CLK(NULL, "edma_tc0", &edma_tc0_clk),
334 CLK(NULL, "edma_tc1", &edma_tc1_clk),
335 CLK(NULL, "edma_tc2", &edma_tc2_clk),
336 CLK(NULL, "edma_tc3", &edma_tc3_clk),
337 CLK(NULL, "uart0", &uart0_clk),
338 CLK(NULL, "uart1", &uart1_clk),
339 CLK(NULL, "uart2", &uart2_clk),
340 CLK("i2c_davinci.1", NULL, &i2c_clk),
341 CLK(NULL, "gpio", &gpio_clk),
342 CLK("davinci-mcasp.0", NULL, &mcasp0_clk),
343 CLK("davinci-mcasp.1", NULL, &mcasp1_clk),
344 CLK(NULL, "aemif", &aemif_clk),
345 CLK("davinci_emac.1", NULL, &emac_clk),
346 CLK(NULL, "pwm0", &pwm0_clk),
347 CLK(NULL, "pwm1", &pwm1_clk),
348 CLK(NULL, "timer0", &timer0_clk),
349 CLK(NULL, "timer1", &timer1_clk),
350 CLK("watchdog", NULL, &timer2_clk),
351 CLK("palm_bk3710", NULL, &ide_clk),
352 CLK(NULL, "vpif0", &vpif0_clk),
353 CLK(NULL, "vpif1", &vpif1_clk),
354 CLK(NULL, NULL, NULL),
357 static struct emac_platform_data dm646x_emac_pdata = {
358 .ctrl_reg_offset = DM646X_EMAC_CNTRL_OFFSET,
359 .ctrl_mod_reg_offset = DM646X_EMAC_CNTRL_MOD_OFFSET,
360 .ctrl_ram_offset = DM646X_EMAC_CNTRL_RAM_OFFSET,
361 .mdio_reg_offset = DM646X_EMAC_MDIO_OFFSET,
362 .ctrl_ram_size = DM646X_EMAC_CNTRL_RAM_SIZE,
363 .version = EMAC_VERSION_2,
366 static struct resource dm646x_emac_resources[] = {
368 .start = DM646X_EMAC_BASE,
369 .end = DM646X_EMAC_BASE + 0x47ff,
370 .flags = IORESOURCE_MEM,
373 .start = IRQ_DM646X_EMACRXTHINT,
374 .end = IRQ_DM646X_EMACRXTHINT,
375 .flags = IORESOURCE_IRQ,
378 .start = IRQ_DM646X_EMACRXINT,
379 .end = IRQ_DM646X_EMACRXINT,
380 .flags = IORESOURCE_IRQ,
383 .start = IRQ_DM646X_EMACTXINT,
384 .end = IRQ_DM646X_EMACTXINT,
385 .flags = IORESOURCE_IRQ,
388 .start = IRQ_DM646X_EMACMISCINT,
389 .end = IRQ_DM646X_EMACMISCINT,
390 .flags = IORESOURCE_IRQ,
394 static struct platform_device dm646x_emac_device = {
395 .name = "davinci_emac",
398 .platform_data = &dm646x_emac_pdata,
400 .num_resources = ARRAY_SIZE(dm646x_emac_resources),
401 .resource = dm646x_emac_resources,
408 * Device specific mux setup
410 * soc description mux mode mode mux dbg
411 * reg offset mask mode
413 static const struct mux_config dm646x_pins[] = {
414 #ifdef CONFIG_DAVINCI_MUX
415 MUX_CFG(DM646X, ATAEN, 0, 0, 5, 1, true)
417 MUX_CFG(DM646X, AUDCK1, 0, 29, 1, 0, false)
419 MUX_CFG(DM646X, AUDCK0, 0, 28, 1, 0, false)
421 MUX_CFG(DM646X, CRGMUX, 0, 24, 7, 5, true)
423 MUX_CFG(DM646X, STSOMUX_DISABLE, 0, 22, 3, 0, true)
425 MUX_CFG(DM646X, STSIMUX_DISABLE, 0, 20, 3, 0, true)
427 MUX_CFG(DM646X, PTSOMUX_DISABLE, 0, 18, 3, 0, true)
429 MUX_CFG(DM646X, PTSIMUX_DISABLE, 0, 16, 3, 0, true)
431 MUX_CFG(DM646X, STSOMUX, 0, 22, 3, 2, true)
433 MUX_CFG(DM646X, STSIMUX, 0, 20, 3, 2, true)
435 MUX_CFG(DM646X, PTSOMUX_PARALLEL, 0, 18, 3, 2, true)
437 MUX_CFG(DM646X, PTSIMUX_PARALLEL, 0, 16, 3, 2, true)
439 MUX_CFG(DM646X, PTSOMUX_SERIAL, 0, 18, 3, 3, true)
441 MUX_CFG(DM646X, PTSIMUX_SERIAL, 0, 16, 3, 3, true)
445 static u8 dm646x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
446 [IRQ_DM646X_VP_VERTINT0] = 7,
447 [IRQ_DM646X_VP_VERTINT1] = 7,
448 [IRQ_DM646X_VP_VERTINT2] = 7,
449 [IRQ_DM646X_VP_VERTINT3] = 7,
450 [IRQ_DM646X_VP_ERRINT] = 7,
451 [IRQ_DM646X_RESERVED_1] = 7,
452 [IRQ_DM646X_RESERVED_2] = 7,
453 [IRQ_DM646X_WDINT] = 7,
454 [IRQ_DM646X_CRGENINT0] = 7,
455 [IRQ_DM646X_CRGENINT1] = 7,
456 [IRQ_DM646X_TSIFINT0] = 7,
457 [IRQ_DM646X_TSIFINT1] = 7,
458 [IRQ_DM646X_VDCEINT] = 7,
459 [IRQ_DM646X_USBINT] = 7,
460 [IRQ_DM646X_USBDMAINT] = 7,
461 [IRQ_DM646X_PCIINT] = 7,
462 [IRQ_CCINT0] = 7, /* dma */
463 [IRQ_CCERRINT] = 7, /* dma */
464 [IRQ_TCERRINT0] = 7, /* dma */
465 [IRQ_TCERRINT] = 7, /* dma */
466 [IRQ_DM646X_TCERRINT2] = 7,
467 [IRQ_DM646X_TCERRINT3] = 7,
468 [IRQ_DM646X_IDE] = 7,
469 [IRQ_DM646X_HPIINT] = 7,
470 [IRQ_DM646X_EMACRXTHINT] = 7,
471 [IRQ_DM646X_EMACRXINT] = 7,
472 [IRQ_DM646X_EMACTXINT] = 7,
473 [IRQ_DM646X_EMACMISCINT] = 7,
474 [IRQ_DM646X_MCASP0TXINT] = 7,
475 [IRQ_DM646X_MCASP0RXINT] = 7,
477 [IRQ_DM646X_RESERVED_3] = 7,
478 [IRQ_DM646X_MCASP1TXINT] = 7, /* clockevent */
479 [IRQ_TINT0_TINT34] = 7, /* clocksource */
480 [IRQ_TINT1_TINT12] = 7, /* DSP timer */
481 [IRQ_TINT1_TINT34] = 7, /* system tick */
484 [IRQ_DM646X_VLQINT] = 7,
488 [IRQ_DM646X_UARTINT2] = 7,
489 [IRQ_DM646X_SPINT0] = 7,
490 [IRQ_DM646X_SPINT1] = 7,
491 [IRQ_DM646X_DSP2ARMINT] = 7,
492 [IRQ_DM646X_RESERVED_4] = 7,
493 [IRQ_DM646X_PSCINT] = 7,
494 [IRQ_DM646X_GPIO0] = 7,
495 [IRQ_DM646X_GPIO1] = 7,
496 [IRQ_DM646X_GPIO2] = 7,
497 [IRQ_DM646X_GPIO3] = 7,
498 [IRQ_DM646X_GPIO4] = 7,
499 [IRQ_DM646X_GPIO5] = 7,
500 [IRQ_DM646X_GPIO6] = 7,
501 [IRQ_DM646X_GPIO7] = 7,
502 [IRQ_DM646X_GPIOBNK0] = 7,
503 [IRQ_DM646X_GPIOBNK1] = 7,
504 [IRQ_DM646X_GPIOBNK2] = 7,
505 [IRQ_DM646X_DDRINT] = 7,
506 [IRQ_DM646X_AEMIFINT] = 7,
512 /*----------------------------------------------------------------------*/
514 /* Four Transfer Controllers on DM646x */
516 dm646x_queue_tc_mapping[][2] = {
517 /* {event queue no, TC no} */
526 dm646x_queue_priority_mapping[][2] = {
527 /* {event queue no, Priority} */
535 static struct edma_soc_info dm646x_edma_info[] = {
538 .n_region = 6, /* 0-1, 4-7 */
542 .queue_tc_mapping = dm646x_queue_tc_mapping,
543 .queue_priority_mapping = dm646x_queue_priority_mapping,
547 static struct resource edma_resources[] = {
551 .end = 0x01c00000 + SZ_64K - 1,
552 .flags = IORESOURCE_MEM,
557 .end = 0x01c10000 + SZ_1K - 1,
558 .flags = IORESOURCE_MEM,
563 .end = 0x01c10400 + SZ_1K - 1,
564 .flags = IORESOURCE_MEM,
569 .end = 0x01c10800 + SZ_1K - 1,
570 .flags = IORESOURCE_MEM,
575 .end = 0x01c10c00 + SZ_1K - 1,
576 .flags = IORESOURCE_MEM,
581 .flags = IORESOURCE_IRQ,
585 .start = IRQ_CCERRINT,
586 .flags = IORESOURCE_IRQ,
588 /* not using TC*_ERR */
591 static struct platform_device dm646x_edma_device = {
594 .dev.platform_data = dm646x_edma_info,
595 .num_resources = ARRAY_SIZE(edma_resources),
596 .resource = edma_resources,
599 static struct resource ide_resources[] = {
601 .start = DM646X_ATA_REG_BASE,
602 .end = DM646X_ATA_REG_BASE + 0x7ff,
603 .flags = IORESOURCE_MEM,
606 .start = IRQ_DM646X_IDE,
607 .end = IRQ_DM646X_IDE,
608 .flags = IORESOURCE_IRQ,
612 static u64 ide_dma_mask = DMA_BIT_MASK(32);
614 static struct platform_device ide_dev = {
615 .name = "palm_bk3710",
617 .resource = ide_resources,
618 .num_resources = ARRAY_SIZE(ide_resources),
620 .dma_mask = &ide_dma_mask,
621 .coherent_dma_mask = DMA_BIT_MASK(32),
625 static struct resource dm646x_mcasp0_resources[] = {
628 .start = DAVINCI_DM646X_MCASP0_REG_BASE,
629 .end = DAVINCI_DM646X_MCASP0_REG_BASE + (SZ_1K << 1) - 1,
630 .flags = IORESOURCE_MEM,
632 /* first TX, then RX */
634 .start = DAVINCI_DM646X_DMA_MCASP0_AXEVT0,
635 .end = DAVINCI_DM646X_DMA_MCASP0_AXEVT0,
636 .flags = IORESOURCE_DMA,
639 .start = DAVINCI_DM646X_DMA_MCASP0_AREVT0,
640 .end = DAVINCI_DM646X_DMA_MCASP0_AREVT0,
641 .flags = IORESOURCE_DMA,
645 static struct resource dm646x_mcasp1_resources[] = {
648 .start = DAVINCI_DM646X_MCASP1_REG_BASE,
649 .end = DAVINCI_DM646X_MCASP1_REG_BASE + (SZ_1K << 1) - 1,
650 .flags = IORESOURCE_MEM,
652 /* DIT mode, only TX event */
654 .start = DAVINCI_DM646X_DMA_MCASP1_AXEVT1,
655 .end = DAVINCI_DM646X_DMA_MCASP1_AXEVT1,
656 .flags = IORESOURCE_DMA,
658 /* DIT mode, dummy entry */
662 .flags = IORESOURCE_DMA,
666 static struct platform_device dm646x_mcasp0_device = {
667 .name = "davinci-mcasp",
669 .num_resources = ARRAY_SIZE(dm646x_mcasp0_resources),
670 .resource = dm646x_mcasp0_resources,
673 static struct platform_device dm646x_mcasp1_device = {
674 .name = "davinci-mcasp",
676 .num_resources = ARRAY_SIZE(dm646x_mcasp1_resources),
677 .resource = dm646x_mcasp1_resources,
680 static struct platform_device dm646x_dit_device = {
685 static u64 vpif_dma_mask = DMA_BIT_MASK(32);
687 static struct resource vpif_resource[] = {
689 .start = DAVINCI_VPIF_BASE,
690 .end = DAVINCI_VPIF_BASE + 0x03ff,
691 .flags = IORESOURCE_MEM,
695 static struct platform_device vpif_dev = {
699 .dma_mask = &vpif_dma_mask,
700 .coherent_dma_mask = DMA_BIT_MASK(32),
702 .resource = vpif_resource,
703 .num_resources = ARRAY_SIZE(vpif_resource),
706 static struct resource vpif_display_resource[] = {
708 .start = IRQ_DM646X_VP_VERTINT2,
709 .end = IRQ_DM646X_VP_VERTINT2,
710 .flags = IORESOURCE_IRQ,
713 .start = IRQ_DM646X_VP_VERTINT3,
714 .end = IRQ_DM646X_VP_VERTINT3,
715 .flags = IORESOURCE_IRQ,
719 static struct platform_device vpif_display_dev = {
720 .name = "vpif_display",
723 .dma_mask = &vpif_dma_mask,
724 .coherent_dma_mask = DMA_BIT_MASK(32),
726 .resource = vpif_display_resource,
727 .num_resources = ARRAY_SIZE(vpif_display_resource),
730 static struct resource vpif_capture_resource[] = {
732 .start = IRQ_DM646X_VP_VERTINT0,
733 .end = IRQ_DM646X_VP_VERTINT0,
734 .flags = IORESOURCE_IRQ,
737 .start = IRQ_DM646X_VP_VERTINT1,
738 .end = IRQ_DM646X_VP_VERTINT1,
739 .flags = IORESOURCE_IRQ,
743 static struct platform_device vpif_capture_dev = {
744 .name = "vpif_capture",
747 .dma_mask = &vpif_dma_mask,
748 .coherent_dma_mask = DMA_BIT_MASK(32),
750 .resource = vpif_capture_resource,
751 .num_resources = ARRAY_SIZE(vpif_capture_resource),
754 /*----------------------------------------------------------------------*/
756 static struct map_desc dm646x_io_desc[] = {
759 .pfn = __phys_to_pfn(IO_PHYS),
764 .virtual = SRAM_VIRT,
765 .pfn = __phys_to_pfn(0x00010000),
767 /* MT_MEMORY_NONCACHED requires supersection alignment */
772 /* Contents of JTAG ID register used to identify exact cpu type */
773 static struct davinci_id dm646x_ids[] = {
777 .manufacturer = 0x017,
778 .cpu_id = DAVINCI_CPU_ID_DM6467,
779 .name = "dm6467_rev1.x",
784 .manufacturer = 0x017,
785 .cpu_id = DAVINCI_CPU_ID_DM6467,
786 .name = "dm6467_rev3.x",
790 static void __iomem *dm646x_psc_bases[] = {
791 IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE),
795 * T0_BOT: Timer 0, bottom: clockevent source for hrtimers
796 * T0_TOP: Timer 0, top : clocksource for generic timekeeping
797 * T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code)
798 * T1_TOP: Timer 1, top : <unused>
800 struct davinci_timer_info dm646x_timer_info = {
801 .timers = davinci_timer_instance,
802 .clockevent_id = T0_BOT,
803 .clocksource_id = T0_TOP,
806 static struct plat_serial8250_port dm646x_serial_platform_data[] = {
808 .mapbase = DAVINCI_UART0_BASE,
810 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
812 .iotype = UPIO_MEM32,
816 .mapbase = DAVINCI_UART1_BASE,
818 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
820 .iotype = UPIO_MEM32,
824 .mapbase = DAVINCI_UART2_BASE,
825 .irq = IRQ_DM646X_UARTINT2,
826 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
828 .iotype = UPIO_MEM32,
836 static struct platform_device dm646x_serial_device = {
837 .name = "serial8250",
838 .id = PLAT8250_DEV_PLATFORM,
840 .platform_data = dm646x_serial_platform_data,
844 static struct davinci_soc_info davinci_soc_info_dm646x = {
845 .io_desc = dm646x_io_desc,
846 .io_desc_num = ARRAY_SIZE(dm646x_io_desc),
847 .jtag_id_base = IO_ADDRESS(0x01c40028),
849 .ids_num = ARRAY_SIZE(dm646x_ids),
850 .cpu_clks = dm646x_clks,
851 .psc_bases = dm646x_psc_bases,
852 .psc_bases_num = ARRAY_SIZE(dm646x_psc_bases),
853 .pinmux_base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE),
854 .pinmux_pins = dm646x_pins,
855 .pinmux_pins_num = ARRAY_SIZE(dm646x_pins),
856 .intc_base = IO_ADDRESS(DAVINCI_ARM_INTC_BASE),
857 .intc_type = DAVINCI_INTC_TYPE_AINTC,
858 .intc_irq_prios = dm646x_default_priorities,
859 .intc_irq_num = DAVINCI_N_AINTC_IRQ,
860 .timer_info = &dm646x_timer_info,
861 .gpio_base = IO_ADDRESS(DAVINCI_GPIO_BASE),
862 .gpio_num = 43, /* Only 33 usable */
863 .gpio_irq = IRQ_DM646X_GPIOBNK0,
864 .serial_dev = &dm646x_serial_device,
865 .emac_pdata = &dm646x_emac_pdata,
866 .sram_dma = 0x10010000,
870 void __init dm646x_init_ide()
872 davinci_cfg_reg(DM646X_ATAEN);
873 platform_device_register(&ide_dev);
876 void __init dm646x_init_mcasp0(struct snd_platform_data *pdata)
878 dm646x_mcasp0_device.dev.platform_data = pdata;
879 platform_device_register(&dm646x_mcasp0_device);
882 void __init dm646x_init_mcasp1(struct snd_platform_data *pdata)
884 dm646x_mcasp1_device.dev.platform_data = pdata;
885 platform_device_register(&dm646x_mcasp1_device);
886 platform_device_register(&dm646x_dit_device);
889 void dm646x_setup_vpif(struct vpif_display_config *display_config,
890 struct vpif_capture_config *capture_config)
893 void __iomem *base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE);
895 value = __raw_readl(base + VSCLKDIS_OFFSET);
896 value &= ~VSCLKDIS_MASK;
897 __raw_writel(value, base + VSCLKDIS_OFFSET);
899 value = __raw_readl(base + VDD3P3V_PWDN_OFFSET);
900 value &= ~VDD3P3V_VID_MASK;
901 __raw_writel(value, base + VDD3P3V_PWDN_OFFSET);
903 davinci_cfg_reg(DM646X_STSOMUX_DISABLE);
904 davinci_cfg_reg(DM646X_STSIMUX_DISABLE);
905 davinci_cfg_reg(DM646X_PTSOMUX_DISABLE);
906 davinci_cfg_reg(DM646X_PTSIMUX_DISABLE);
908 vpif_display_dev.dev.platform_data = display_config;
909 vpif_capture_dev.dev.platform_data = capture_config;
910 platform_device_register(&vpif_dev);
911 platform_device_register(&vpif_display_dev);
912 platform_device_register(&vpif_capture_dev);
915 void __init dm646x_init(void)
917 dm646x_board_setup_refclk(&ref_clk);
918 davinci_common_init(&davinci_soc_info_dm646x);
921 static int __init dm646x_init_devices(void)
923 if (!cpu_is_davinci_dm646x())
926 platform_device_register(&dm646x_edma_device);
927 platform_device_register(&dm646x_emac_device);
930 postcore_initcall(dm646x_init_devices);